Interfacing to a TI 5416 DSP via the Host Port Interface (HPI)
Background on the TI 5416 DSP and Overview

The Texas Instruments TI 5416 fixed-point DSP finds its home in many mid range DSP applications. It is supported by the TI 5416 DSK, which proved very attractive as the choice for this example because it exposes the HPI on one of the three expansion headers of the DSK board. The HPI allows a host processor access to the internal RAM of the 5416, thereby enabling the transfer of data between the host processor and the 5416.
By interfacing the FX2 to the 5416's HPI, this allows developers of embedded audio and imaging applications to easily add a high speed USB port. The FX2 can also bootload the 5416 DSP code via the HPI. In this example, users will be shown how to interface the FX2 to the 5416 HPI using the GPIF to accomplish two things: 1) read and write to the internal RAM block of the 5416, and 2) bootload the 5416 by downloading the DSP code from the PC. For detailed information about how the HPI block of the 5416 works, please refer to the TI documentation mentioned in the references section at the end of this document. Note that the information presented here may also be applicable to other TI DSPs that expose the HPI port.

Hardware Connections
This section discusses the definition of the GPIF interconnect which is shown below in Figure 13.
Figure 13. GPIF Interconnect to TI 5416 HPI

PA3, PA2 ----> HCNTL[1:0]
Port pins PA3 and PA2 are used to provide address lines to select either the HPIC, HPIA, or HPID registers of the HPI. The FX2 reads and writes data by accessing these registers.

FD[7:0] <----> HD[7:0]
The lower portion of the GPIF data bus (FD[7:0]) is connected to the HPI data bus (HD[7:0]). The FX2 uses this connection for exchange of information between itself and the HPI.

CTL0 ----> HRNW
CTL0 is connected to the HRNW signal of the HPI. If HRNW is a 1, this indicates a read access to the HPI. If HRNW is a 0, this indicates a write access to the HPI.

CTL1 ----> HDS1
CTL1 is connected to the HDS1/ strobe of the HPI. The falling edge of HDS1/ marks the beginning of the HPI access, and samples the value of HRNW, HCNTL[1:0], and HBIL. The rising edge of HDS1/ marks the end of the HPI access.

CTL2 ----> HBIL
CTL2 is connected to the HBIL signal of the HPI. A complete HPI access consists of a two byte transfer. If HBIL is 0, this indicates to the HPI that the first byte is being transferred. To indicate to the HPI that the second byte is being transferred, HBIL must be 1.

RDY0 <---- HRDY
RDY0 is connected to the HRDY/ signal of the HPI. HRDY/ is low when the HPI is completing the internal portion of a complete HPI access. Another access to the HPI must not be performed until the internal portion of the transfer is complete. This signal is monitored by the GPIF.

INT0 <---- HINT, INT2
The INT0/ interrupt signal on the FX2 is conected the HINT/ output of the HPI. When the DSP is reset, the HINT/ will be asserted. The DSP can also use this as a general purpose interrupt to the FX2. The HINT/ signal is also tied to the 5416&rsquo;s INT2/ pin to allow the FX2 to be able to bootload the DSP code.

GND <----> GND
Ground

HCS, HPI_16
HPI_16 is tied to ground to make the HPI operate in 8-bit mode (HPI-8). The HPI can operate in 16-bit mode (HPI-16) if the 5416&rsquo;s external memory interface is not used (EMIF). For most DSP applications, the EMIF will already be used for memory expansion. Using the HPI in 8-bit mode also simplifies the GPIF interface. HCS/ is tied to ground to allow continuous access to the HPI.

HDS2, HAS, HPI_EN
HPI_EN is tied to VCC to enable the HPI port. HAS/ and HDS2/ are tied to VCC since they are not necessary for this interface (attributed in part to the flexibility of the GPIF interface).

The assignment of CTL and RDY lines was optimized for the FX2 56-pin package. The connection between the TI 5416 DSK board and the FX2 development board was accomplished through the use of a ribbon cable set. The TI 5416 DSK board exposes headers that require breakout panels (available from www.dspglobal.com) for prototyping purposes. The ribbon cables connect between a breakout panel installed on the DSK board's P3 and the FX2 prototype board mounted onto the FX2 development board. Figure 14 shows a snap of the actual hardware setup.

Figure 14. Shot of Actual Hardware Setup

Application-specific Data Flow

Now that the GPIF interconnect has been presented, it's important to understand the overall data flow for this design example. EP2OUT (4x buffered) is the source endpoint used for data writes to the HPI and EP6IN (4x buffered) is the sink endpoint used for data reads from the HPI. EP0, the FX2's control endpoint, is used for writes to the HPIC and HPIA registers.
Before a data read or write can commence to and from a specific address in the DSP, the HPIA needs to be setup with the appropriate source or destination address. The HPIC also needs to be setup to set the BOB bit to 1, which allows the first byte of transfer to be the LSB and the second byte of the transfer to be the MSB (as organized in the DSP memory). Since the 5416 supports an extended address scheme, the XPHIA bit in the HPIC register needs to be set if FX2 wants to access the upper seven bits of the HPIA register. The XPHIA bit also needs to be set if proper auto-increment of the address is to occur when consecutive data read and write accesses are made.
Figure 15 and Figure 16 show the data flow models for this example. GPIF single transactions are used to write out the data from EP0 to the HPIC and HPIA registers. GPIF FIFO transactions are used for data reads and writes using EP6IN and EP2OUT in auto mode, respectively.

Figure 15. Data Flow Model in the OUT direction

Figure 16. Data Flow Model in the IN direction