16-bit Interface to External Synchronous Cypress FIFO CY7C4625-15AC
Overview

The end objective of this example is to be able to perform a bulk loop back function with the external FIFO. The FX2 will write data out FD[15:0] to the external FIFO and read data back from FD[15:0] (the outputs from the external FIFO Q[15:0] are also connected to FD[15:0]). The bulk transfers can be exercised by using the EZ-USB Control Panel or bulkloop.exe utility supplied with the EZ-USB development kit software.

Hardware Connections
This section discusses the definition of the GPIF interconnect which is shown below in Figure 4-1.
Figure 4-1. GPIF Interconnect Diagram

IFCLK ----> WCLK, RCLK
IFCLK is connected to the write and read clock inputs (WCLK, RCLK) of the external FIFO. Data is clocked into the external FIFO on every rising edge of WCLK while WEN/ is asserted. Likewise, new data is presented on Q[15:0] on every rising edge of RCLK while REN/ and OE/ are asserted. The external FIFO can accept an input clock frequency of up to 66.7Mhz so it can handle the incoming IFCLK frequency (either 30MHz or 48MHz).

FD[15:0] <----> D[15:0] Q[15:0]
The GPIF data bus (FD[15:0]) is connected to the external FIFO&rsquo;s input data bus (D[15:0]) to allow for word wide operations. The output data bus of the external FIFO (Q[15:0]) is also connected to the GPIF data bus to allow the FX2 to read back the data contents. In order to ensure that bus contention will never occur, the OE/ signal must be manipulated appropriately.

CTL0 ----> WEN
CTL0 is connected to the write enable line (WEN/) of the external FIFO. While WEN/ is held low, data is written into the external FIFO on every rising edge of WCLK.

CTL1 ----> REN
CTL1 is connected to the read enable line (REN/) of the external FIFO. While REN/ and OE/ are held low, new data is presented on Q[15:0] on every rising edge of RCLK.

CTL2 ----> OE
CTL2 is connected to the output enable line (OE/) of the external FIFO. While REN/ and OE/ are held low, new data is presented on Q[15:0] on every rising edge of RCLK.

RDY0 <---- EF
RDY0 is connected to the empty flag (EF/) of the external FIFO. EF/ is asserted low if the external FIFO is empty. The GPIF can use this to regulate data transfers when reading from the external FIFO.

RDY1 <---- FF
RDY1 is connected to the full flag (FF/) of the external FIFO. FF/ is asserted low if the external FIFO is full. The GPIF can use this to regulate data transfers when writing to the external FIFO.

PA2 ----> RS
PA2 is connected to the reset signal of the external FIFO. PA2 is not part of the GPIF interconnect but is still part of the overall system design. PA2 is used as an I/O pin to reset the external FIFO to a known state before GPIF data transfers commence.

The GPIF Designer block diagram for the single transaction portion of the FIFO design example is shown below.

The assignment of CTLx and RDYn lines is optimized for the FX2 56-pin package. The CTLx lines are used as input strobes into the external FIFO, and the status outputs from the external FIFO (EF and FF) are used to monitor under run and over run conditions. The basic rule of thumb is: one should never read from an empty FIFO or write to a full FIFO.
The external FIFO was mounted onto an FX2 development board by using the prototype board supplied with the development kit. The external FIFO was placed on a 64-pin TQFP package surface mount adapter (available from Twin Industries at www.twinhunter.com) and piggybacked on top of the prototype board. Figure 9 shows a snapshot of the actual hardware setup. For full hardware specifications on the external FIFO, its datasheet can be downloaded from the Cypress website. For a pin-out list for the prototype board connection to the FX2 development board and a full schematic for the external FIFO prototype board, see the software contents available with this primer.

Figure 9. Shot of Actual Hardware Setup

Application-specific Data Flow

Now that the GPIF interconnect has been presented, it's important to understand the overall data flow for this design example. Endpoint 2 OUT (EP2OUT) is used as the source endpoint for GPIF writes to the external FIFO, and Endpoint 6 IN (EP6IN) is used as the sink endpoint for GPIF reads from the external FIFO. Remember that the IN and OUT directions are USB host-centric, therefore EP2OUT contains the data packets sent by the USB host (in this case the PC) and EP6IN contains the data packets sent to the USB host. Figures 4-2 and 4-3 show the data flow models for this particular example.

Figure 4-2. Data Flow Model in the OUT direction Figure 4-3. Data Flow Model in the IN direction

Manual mode versus Auto mode

FX2 endpoints can basically operate in two modes, Manual (AUTOIN/AUTOOUT=0) or Auto (AUTOIN/AUTOOUT=1). In short, manual mode makes the CPU responsible for committing the USB packet to the peripheral domain and vice versa. In order to maximize the USB 2.0 bandwidth, auto mode should be used. This allows USB packets to be committed automatically to the peripheral domain and vice versa by removing the CPU from the data path. This example demonstrates the use of auto mode.

Two examples in one

The FIFO example is really two examples in one because two versions of the firmware are discussed. Sections 4.1.4-4.1.6 present a version that uses GPIF single transactions to read and write to the external FIFO, which then sets the stage for Sections 4.1.7-4.1.9. Sections 4.1.7-4.1.9 discuss a version that uses GPIF FIFO transactions and the endpoints in auto mode, thus maximizing the USB 2.0 bandwidth. This two-phased approach is in line with the methodology presented in section 3.3, and by understanding the two approaches, the user should be able to discern what it takes to move from a simple working example to an example that utilizes the full USB 2.0 bandwidth capabilities of the FX2.