#ifndef FX2_REGS_H
#define FX2_REGS_H

#ifdef ALLOCATE_EXTERN
 #define	XBYTE( name, addr) xdata volatile unsigned char name _at_ addr
#else
 #define	XBYTE( name, addr) extern xdata volatile unsigned char name
#endif

// ============================================================================
// General configuration
// ============================================================================
XBYTE( CPUCS             , 0xE600); // Control & Status
XBYTE( IFCONFIG          , 0xE601); // Interface Configuration
XBYTE( PINFLAGSAB        , 0xE602); // FIFO FLAGA and FLAGB Assignments
XBYTE( PINFLAGSCD        , 0xE603); // FIFO FLAGC and FLAGD Assignments
XBYTE( FIFORESET         , 0xE604); // Restore FIFOS to default state
XBYTE( BREAKPT           , 0xE605); // Breakpoint
XBYTE( BPADDRH           , 0xE606); // Breakpoint Address H
XBYTE( BPADDRL           , 0xE607); // Breakpoint Address L
XBYTE( UART230           , 0xE608); // 230 Kbaud clock for T0,T1,T2
XBYTE( FIFOPINPOLAR      , 0xE609); // FIFO polarities
XBYTE( REVID             , 0xE60A); // Chip Revision
XBYTE( REVCTL            , 0xE60B); // Chip Revision Control

// ============================================================================
// Endpoint configuration registers
// ============================================================================
XBYTE( EP1OUTCFG         , 0xE610); // Endpoint 1-OUT Configuration
XBYTE( EP1INCFG          , 0xE611); // Endpoint 1-IN Configuration
XBYTE( EP2CFG            , 0xE612); // Endpoint 2 Configuration
XBYTE( EP4CFG            , 0xE613); // Endpoint 4 Configuration
XBYTE( EP6CFG            , 0xE614); // Endpoint 6 Configuration
XBYTE( EP8CFG            , 0xE615); // Endpoint 8 Configuration
XBYTE( EP2FIFOCFG        , 0xE618); // Endpoint 2 FIFO configuration
XBYTE( EP4FIFOCFG        , 0xE619); // Endpoint 4 FIFO configuration
XBYTE( EP6FIFOCFG        , 0xE61A); // Endpoint 6 FIFO configuration
XBYTE( EP8FIFOCFG        , 0xE61B); // Endpoint 8 FIFO configuration
XBYTE( EP2AUTOINLENH     , 0xE620); // Endpoint 2 Packet Length H (IN only)
XBYTE( EP2AUTOINLENL     , 0xE621); // Endpoint 2 Packet Length L (IN only)
XBYTE( EP4AUTOINLENH     , 0xE622); // Endpoint 4 Packet Length H (IN only)
XBYTE( EP4AUTOINLENL     , 0xE623); // Endpoint 4 Packet Length L (IN only)
XBYTE( EP6AUTOINLENH     , 0xE624); // Endpoint 6 Packet Length H (IN only)
XBYTE( EP6AUTOINLENL     , 0xE625); // Endpoint 6 Packet Length L (IN only)
XBYTE( EP8AUTOINLENH     , 0xE626); // Endpoint 8 Packet Length H (IN only)
XBYTE( EP8AUTOINLENL     , 0xE627); // Endpoint 8 Packet Length L (IN only)
XBYTE( EP2FIFOPFH        , 0xE630); // EP2 Programmable Flag trigger H
XBYTE( EP2FIFOPFL        , 0xE631); // EP2 Programmable Flag trigger L
XBYTE( EP4FIFOPFH        , 0xE632); // EP4 Programmable Flag trigger H
XBYTE( EP4FIFOPFL        , 0xE633); // EP4 Programmable Flag trigger L
XBYTE( EP6FIFOPFH        , 0xE634); // EP6 Programmable Flag trigger H
XBYTE( EP6FIFOPFL        , 0xE635); // EP6 Programmable Flag trigger L
XBYTE( EP8FIFOPFH        , 0xE636); // EP8 Programmable Flag trigger H
XBYTE( EP8FIFOPFL        , 0xE637); // EP8 Programmable Flag trigger L
XBYTE( EP2ISOINPKTS      , 0xE640); // EP2 (if ISO) IN Packets per frame (1-3)
XBYTE( EP4ISOINPKTS      , 0xE641); // EP4 (if ISO) IN Packets per frame (1-3)
XBYTE( EP6ISOINPKTS      , 0xE642); // EP6 (if ISO) IN Packets per frame (1-3)
XBYTE( EP8ISOINPKTS      , 0xE643); // EP8 (if ISO) IN Packets per frame (1-3)
XBYTE( INPKTEND          , 0xE648); // Force IN Packet End
XBYTE( OUTPKTEND         , 0xE649); // Force OUT Packet End

// ============================================================================
// Interrupts
// ============================================================================
XBYTE( EP2FIFOIE         , 0xE650); // Endpoint 2 Flag Interrupt Enable
XBYTE( EP2FIFOIRQ        , 0xE651); // Endpoint 2 Flag Interrupt Request
XBYTE( EP4FIFOIE         , 0xE652); // Endpoint 4 Flag Interrupt Enable
XBYTE( EP4FIFOIRQ        , 0xE653); // Endpoint 4 Flag Interrupt Request
XBYTE( EP6FIFOIE         , 0xE654); // Endpoint 6 Flag Interrupt Enable
XBYTE( EP6FIFOIRQ        , 0xE655); // Endpoint 6 Flag Interrupt Request
XBYTE( EP8FIFOIE         , 0xE656); // Endpoint 8 Flag Interrupt Enable
XBYTE( EP8FIFOIRQ        , 0xE657); // Endpoint 8 Flag Interrupt Request

XBYTE( IBNIE             , 0xE658); // IN-BULK-NAK Interrupt Enable
XBYTE( IBNIRQ            , 0xE659); // IN-BULK-NAK interrupt Request

XBYTE( NAKIE             , 0xE65A); // Endpoint Ping NAK interrupt Enable
XBYTE( NAKIRQ            , 0xE65B); // Endpoint Ping NAK interrupt Request

XBYTE( USBIE             , 0xE65C); // USB Int Enables
XBYTE( USBIRQ            , 0xE65D); // USB Interrupt Requests

XBYTE( EPIE              , 0xE65E); // Endpoint Interrupt Enables
XBYTE( EPIRQ             , 0xE65F); // Endpoint Interrupt Requests

XBYTE( GPIFIE            , 0xE660); // GPIF Interrupt Enable
XBYTE( GPIFIRQ           , 0xE661); // GPIF Interrupt Request

XBYTE( USBERRIE          , 0xE662); // USB Error Interrupt Enables
XBYTE( USBERRIRQ         , 0xE663); // USB Error Interrupt Requests
XBYTE( ERRCNTLIM         , 0xE664); // USB Error counter and limit

XBYTE( CLRERRCNT         , 0xE665); // Clear Error Counter EC[3..0]

XBYTE( INT2IVEC          , 0xE666); // Interupt 2 (USB) Autovector
XBYTE( INT4IVEC          , 0xE667); // Interupt 4 (FIFOS & GPIF) Autovector
XBYTE( INTSETUP          , 0xE668); // Interrupt 2&4 Setup

// ============================================================================
// Input/Output
// ============================================================================
XBYTE( PORTACFG			 , 0xE670); // I/O Port A Alternate Configuration
XBYTE( PORTCCFG			 , 0xE671); // I/O Port C Alternate Configuration
XBYTE( PORTECFG			 , 0xE672); // I/O Port E Alternate Configuration

XBYTE( I2CS				 , 0xE678); // I2C Control & Status
XBYTE( I2DAT			 , 0xE679); // I2C Data
XBYTE( I2CTL			 , 0xE67A); // I2C Control

XBYTE( XAUTODAT1		 , 0xE67B); // Autopointer1 MOVX access
XBYTE( XAUTODAT2		 , 0xE67C); // Autopointer2 MOVX access

// ============================================================================
// USB Control
// ============================================================================
XBYTE( USBCS             , 0xE680); // USB Control & Status
XBYTE( SUSPEND           , 0xE681); // Put chip into suspend
XBYTE( WAKEUPCS          , 0xE682); // Wakeup source and polarity
XBYTE( TOGCTL            , 0xE683); // Toggle Control
XBYTE( USBFRAMEH         , 0xE684); // USB Frame count H
XBYTE( USBFRAMEL         , 0xE685); // USB Frame count L
XBYTE( MICROFRAME        , 0xE686); // Microframe count, 0-7
XBYTE( FNADDR            , 0xE687); // USB Function address

// ============================================================================
// Endpoints
// ============================================================================
XBYTE( EP0BCH            , 0xE68A); // Endpoint 0 Byte Count H
XBYTE( EP0BCL            , 0xE68B); // Endpoint 0 Byte Count L
XBYTE( EP1OUTBC          , 0xE68D); // Endpoint 1 OUT Byte Count
XBYTE( EP1INBC           , 0xE68F); // Endpoint 1 IN Byte Count
XBYTE( EP2BCH            , 0xE690); // Endpoint 2 Byte Count H
XBYTE( EP2BCL            , 0xE691); // Endpoint 2 Byte Count L
XBYTE( EP4BCH            , 0xE694); // Endpoint 4 Byte Count H
XBYTE( EP4BCL            , 0xE695); // Endpoint 4 Byte Count L
XBYTE( EP6BCH            , 0xE698); // Endpoint 6 Byte Count H
XBYTE( EP6BCL            , 0xE699); // Endpoint 6 Byte Count L
XBYTE( EP8BCH            , 0xE69C); // Endpoint 8 Byte Count H
XBYTE( EP8BCL            , 0xE69D); // Endpoint 8 Byte Count L

XBYTE( EP0CS             , 0xE6A0); // Endpoint  Control and Status
XBYTE( EP1OUTCS          , 0xE6A1); // Endpoint 1 OUT Control and Status
XBYTE( EP1INCS           , 0xE6A2); // Endpoint 1 IN Control and Status
XBYTE( EP2CS             , 0xE6A3); // Endpoint 2 Control and Status
XBYTE( EP4CS             , 0xE6A4); // Endpoint 4 Control and Status
XBYTE( EP6CS             , 0xE6A5); // Endpoint 6 Control and Status
XBYTE( EP8CS             , 0xE6A6); // Endpoint 8 Control and Status

XBYTE( EP2FIFOFLGS       , 0xE6A7); // Endpoint 2 Flags
XBYTE( EP4FIFOFLGS       , 0xE6A8); // Endpoint 4 Flags
XBYTE( EP6FIFOFLGS       , 0xE6A9); // Endpoint 6 Flags
XBYTE( EP8FIFOFLGS       , 0xE6AA); // Endpoint 8 Flags

XBYTE( EP2FIFOBCH        , 0xE6AB); // EP2 FIFO total byte count H
XBYTE( EP2FIFOBCL        , 0xE6AC); // EP2 FIFO total byte count L
XBYTE( EP4FIFOBCH        , 0xE6AD); // EP4 FIFO total byte count H
XBYTE( EP4FIFOBCL        , 0xE6AE); // EP4 FIFO total byte count L
XBYTE( EP6FIFOBCH        , 0xE6AF); // EP6 FIFO total byte count H
XBYTE( EP6FIFOBCL        , 0xE6B0); // EP6 FIFO total byte count L
XBYTE( EP8FIFOBCH        , 0xE6B1); // EP8 FIFO total byte count H
XBYTE( EP8FIFOBCL        , 0xE6B2); // EP8 FIFO total byte count L

XBYTE( SUDPTRH           , 0xE6B3); // Setup Data Pointer high address byte
XBYTE( SUDPTRL           , 0xE6B4); // Setup Data Pointer low address byte
XBYTE( SUDPTRCTL         , 0xE6B5); // Setup Data Pointer Auto Mode

XBYTE( SETUPDAT[8]       , 0xE6B8); // 8 bytes of SETUP data

// ============================================================================
// GPIF
// ============================================================================
XBYTE( GPIFWFSELECT      , 0xE6C0); // Waveform Selector
XBYTE( GPIFIDLECS        , 0xE6C1); // GPIF Done, GPIF IDLE drive mode
XBYTE( GPIFIDLECTL       , 0xE6C2); // Inactive Bus, CTL states
XBYTE( GPIFCTLCFG        , 0xE6C3); // CTL OUT pin drive
XBYTE( GPIFADRH          , 0xE6C4); // GPIF Address H
XBYTE( GPIFADRL          , 0xE6C5); // GPIF Address L

XBYTE( GPIFTCB3          , 0xE6CE); // GPIF Transaction Count Byte 3
XBYTE( GPIFTCB2          , 0xE6CF); // GPIF Transaction Count Byte 2
XBYTE( GPIFTCB1          , 0xE6D0); // GPIF Transaction Count Byte 1
XBYTE( GPIFTCB0          , 0xE6D1); // GPIF Transaction Count Byte 0

#define EP2GPIFTCH GPIFTCB1			// these are here for backwards compatibility
#define EP2GPIFTCL GPIFTCB0			// 
#define EP4GPIFTCH GPIFTCB1			// these are here for backwards compatibility
#define EP4GPIFTCL GPIFTCB0			// 
#define EP6GPIFTCH GPIFTCB1			// these are here for backwards compatibility
#define EP6GPIFTCL GPIFTCB0			// 
#define EP8GPIFTCH GPIFTCB1			// these are here for backwards compatibility
#define EP8GPIFTCL GPIFTCB0   		// 

XBYTE( EP2GPIFFLGSEL     , 0xE6D2); // EP2 GPIF Flag select
XBYTE( EP2GPIFPFSTOP     , 0xE6D3); // Stop GPIF EP2 transaction on prog. flag
XBYTE( EP2GPIFTRIG       , 0xE6D4); // EP2 FIFO Trigger
XBYTE( EP4GPIFFLGSEL     , 0xE6DA); // EP4 GPIF Flag select
XBYTE( EP4GPIFPFSTOP     , 0xE6DB); // Stop GPIF EP4 transaction on prog. flag
XBYTE( EP4GPIFTRIG       , 0xE6DC); // EP4 FIFO Trigger
XBYTE( EP6GPIFFLGSEL     , 0xE6E2); // EP6 GPIF Flag select
XBYTE( EP6GPIFPFSTOP     , 0xE6E3); // Stop GPIF EP6 transaction on prog. flag
XBYTE( EP6GPIFTRIG       , 0xE6E4); // EP6 FIFO Trigger
XBYTE( EP8GPIFFLGSEL     , 0xE6EA); // EP8 GPIF Flag select
XBYTE( EP8GPIFPFSTOP     , 0xE6EB); // Stop GPIF EP8 transaction on prog. flag
XBYTE( EP8GPIFTRIG       , 0xE6EC); // EP8 FIFO Trigger
XBYTE( XGPIFSGLDATH      , 0xE6F0); // GPIF Data H (16-bit mode only)
XBYTE( XGPIFSGLDATLX     , 0xE6F1); // Read/Write GPIF Data L & trigger transac
XBYTE( XGPIFSGLDATLNOX   , 0xE6F2); // Read GPIF Data L, no transac trigger
XBYTE( GPIFREADYCFG      , 0xE6F3); // Internal RDY,Sync/Async, RDY5CFG
XBYTE( GPIFREADYSTAT     , 0xE6F4); // RDY pin states
XBYTE( GPIFABORT         , 0xE6F5); // Abort GPIF cycles
 
// ============================================================================
// UDMA
// ============================================================================
XBYTE( FLOWSTATE         , 0xE6C6); // Defines GPIF flow state
XBYTE( FLOWLOGIC         , 0xE6C7); // Defines flow/hold decision criteria
XBYTE( FLOWEQ0CTL        , 0xE6C8); // CTL states during active flow state
XBYTE( FLOWEQ1CTL        , 0xE6C9); // CTL states during hold flow state
XBYTE( FLOWHOLDOFF       , 0xE6CA);
XBYTE( FLOWSTB           , 0xE6CB); // CTL/RDY Signal to use as master data strobe
XBYTE( FLOWSTBEDGE       , 0xE6CC); // Defines active master strobe edge
XBYTE( FLOWSTBHPERIOD    , 0xE6CD); // Half Period of output master strobe
XBYTE( GPIFHOLDAMOUNT    , 0xE60C); // Data delay shift
XBYTE( UDMACRCH          , 0xE67D); // CRC Upper byte
XBYTE( UDMACRCL          , 0xE67E); // CRC Lower byte
XBYTE( UDMACRCQUAL       , 0xE67F); // UDMA In only, host terminated use only

// ============================================================================
// Endpoint Buffers
// ============================================================================
XBYTE( EP0BUF		[64] , 0xE740); // EP0 IN-OUT buffer
XBYTE( EP1OUTBUF	[64] , 0xE780); // EP1-OUT buffer
XBYTE( EP1INBUF		[64] , 0xE7C0); // EP1-IN buffer
XBYTE( EP2FIFOBUF [1024] , 0xF000); // 512/1024-byte EP2 buffer (IN or OUT)
XBYTE( EP4FIFOBUF [1024] , 0xF400); // 512 byte EP4 buffer 		(IN or OUT)
XBYTE( EP6FIFOBUF [1024] , 0xF800); // 512/1024-byte EP6 buffer (IN or OUT)
XBYTE( EP8FIFOBUF [1024] , 0xFC00); // 512 byte EP8 buffer 		(IN or OUT)

// ============================================================================
// Error Correction Code (ECC) Registers (FX2LP/FX1 only)
// ============================================================================
XBYTE( ECCCFG            , 0xE628); // ECC Configuration
XBYTE( ECCRESET          , 0xE629); // ECC Reset
XBYTE( ECC1B0            , 0xE62A); // ECC1 Byte 0
XBYTE( ECC1B1            , 0xE62B); // ECC1 Byte 1
XBYTE( ECC1B2            , 0xE62C); // ECC1 Byte 2
XBYTE( ECC2B0            , 0xE62D); // ECC2 Byte 0
XBYTE( ECC2B1            , 0xE62E); // ECC2 Byte 1
XBYTE( ECC2B2            , 0xE62F); // ECC2 Byte 2
 
// ============================================================================
// Feature Registers  (FX2LP/FX1 only)
// ============================================================================
XBYTE( GPCR2			 , 0xE50D);	// Chip Features

// ============================================================================
// Special Function Registers (sfr)
// ============================================================================
#include <fx2_regs_sfr8x.h>
#include <fx2_regs_sfr9x.h>
#include <fx2_regs_sfrAx.h>
#include <fx2_regs_sfrBx.h>
#include <fx2_regs_sfrCx.h>
#include <fx2_regs_sfrDx.h>
#include <fx2_regs_sfrEx.h>
#include <fx2_regs_sfrFx.h>

// ============================================================================
// Bit masks
// ============================================================================
// ----------------------------------------------------------------------------
// CPU Control & Status Register (CPUCS)
// ----------------------------------------------------------------------------
#define bmPRTCSTB		bmBIT5
#define bmCLKSPD	   (bmBIT4 | bmBIT3)
#define bmCLKSPD1		bmBIT4
#define bmCLKSPD0		bmBIT3
#define bmCLKINV		bmBIT2
#define bmCLKOE			bmBIT1
#define bm8051RES		bmBIT0

// ----------------------------------------------------------------------------
// Port A (PORTACFG)
// ----------------------------------------------------------------------------
#define bmFLAGD			bmBIT7
#define bmINT1			bmBIT1
#define bmINT0			bmBIT0

// ----------------------------------------------------------------------------
// Port C (PORTCCFG)
// ----------------------------------------------------------------------------
#define bmGPIFA7		bmBIT7
#define bmGPIFA6		bmBIT6
#define bmGPIFA5		bmBIT5
#define bmGPIFA4		bmBIT4
#define bmGPIFA3		bmBIT3
#define bmGPIFA2		bmBIT2
#define bmGPIFA1		bmBIT1
#define bmGPIFA0		bmBIT0

// ----------------------------------------------------------------------------
// Port E (PORTECFG)
// ----------------------------------------------------------------------------
#define bmGPIFA8		bmBIT7
#define bmT2EX			bmBIT6
#define bmINT6			bmBIT5
#define bmRXD1OUT		bmBIT4
#define bmRXD0OUT		bmBIT3
#define bmT2OUT			bmBIT2
#define bmT1OUT			bmBIT1
#define bmT0OUT			bmBIT0

// ----------------------------------------------------------------------------
// I2C Control & Status Register (I2CS)
// ----------------------------------------------------------------------------
#define bmSTART			bmBIT7
#define bmSTOP			bmBIT6
#define bmLASTRD		bmBIT5
#define bmID		   (bmBIT4 | bmBIT3)
#define bmBERR			bmBIT2
#define bmACK			bmBIT1
#define bmDONE			bmBIT0

// ----------------------------------------------------------------------------
// I2C Control Register (I2CTL)
// ----------------------------------------------------------------------------
#define bmSTOPIE		bmBIT1
#define bm400KHZ		bmBIT0

// ----------------------------------------------------------------------------
// Interrupt 2 (USB) Autovector Register (INT2IVEC)
// ----------------------------------------------------------------------------
#define bmIV4			bmBIT6
#define bmIV3			bmBIT5
#define bmIV2			bmBIT4
#define bmIV1			bmBIT3
#define bmIV0			bmBIT2

// ----------------------------------------------------------------------------
// USB Interrupt Request & Enable Registers (USBIE/USBIRQ)
// ----------------------------------------------------------------------------
#define bmEP0ACK		bmBIT6
#define bmHSGRANT		bmBIT5
#define bmURES			bmBIT4
#define bmSUSP			bmBIT3
#define bmSUTOK			bmBIT2
#define bmSOF			bmBIT1
#define bmSUDAV			bmBIT0

// ----------------------------------------------------------------------------
// USB Interrupt Request & Enable Registers (EPIE/EPIRQ)
// ----------------------------------------------------------------------------
#define	bmEP8			bmBIT7
#define	bmEP6			bmBIT6
#define	bmEP4			bmBIT5
#define	bmEP2			bmBIT4
#define	bmEP1OUT		bmBIT3
#define	bmEP1IN			bmBIT2
#define	bmEP0OUT		bmBIT1
#define	bmEP0IN			bmBIT0

// ----------------------------------------------------------------------------
// GPIF Interrupt Request & Enable Registers (GPIFIE/GPIFIRQ)
// ----------------------------------------------------------------------------
#define	bmGPIFWF		bmBIT1
#define	bmGPIFDONE		bmBIT0


// ----------------------------------------------------------------------------
// Breakpoint register (BREAKPT)
// ----------------------------------------------------------------------------
#define bmBREAK			bmBIT3
#define bmBPPULSE		bmBIT2
#define bmBPEN			bmBIT1

// ----------------------------------------------------------------------------
// Interrupt 2 & 4 Setup (INTSETUP)
// ----------------------------------------------------------------------------
#define bmAV2EN			bmBIT3
#define INT4IN			bmBIT1
#define bmAV4EN			bmBIT0

// ----------------------------------------------------------------------------
// USB Control & Status Register (USBCS)
// ----------------------------------------------------------------------------
#define bmHSM			bmBIT7
#define bmDISCON		bmBIT3
#define bmNOSYNSOF		bmBIT2
#define bmRENUM			bmBIT1
#define bmSIGRESUME		bmBIT0

// ----------------------------------------------------------------------------
// Wakeup Control and Status Register (WAKEUPCS)
// ----------------------------------------------------------------------------
#define bmWU2			bmBIT7
#define bmWU			bmBIT6
#define bmWU2POL		bmBIT5
#define bmWUPOL			bmBIT4
#define bmDPEN			bmBIT2
#define bmWU2EN			bmBIT1
#define bmWUEN			bmBIT0

// ----------------------------------------------------------------------------
// End Point 0 Control & Status Register (EP0CS)
// ----------------------------------------------------------------------------
#define bmHSNAK			bmBIT7

// ----------------------------------------------------------------------------
// End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS)
// ----------------------------------------------------------------------------
#define bmEPBUSY		bmBIT1
#define bmEPSTALL		bmBIT0

// ----------------------------------------------------------------------------
// End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS)
// ----------------------------------------------------------------------------
#define bmNPAK		   (bmBIT6 | bmBIT5 | bmBIT4)
#define bmEPFULL		bmBIT3
#define bmEPEMPTY		bmBIT2

/* Endpoint Status (EP2468STAT) SFR bits */
#define bmEP8FULL		bmBIT7
#define bmEP8EMPTY		bmBIT6
#define bmEP6FULL		bmBIT5
#define bmEP6EMPTY		bmBIT4
#define bmEP4FULL		bmBIT3
#define bmEP4EMPTY		bmBIT2
#define bmEP2FULL		bmBIT1
#define bmEP2EMPTY		bmBIT0


// ----------------------------------------------------------------------------
// SETUP Data Pointer Auto Mode (SUDPTRCTL)
// ----------------------------------------------------------------------------
#define bmSDPAUTO    	bmBIT0

// ----------------------------------------------------------------------------
// Endpoint Data Toggle Control (TOGCTL)
// ----------------------------------------------------------------------------
#define bmQUERYTOGGLE	bmBIT7
#define bmSETTOGGLE		bmBIT6
#define bmRESETTOGGLE	bmBIT5
#define bmTOGCTLEPMASK	bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0

// ----------------------------------------------------------------------------
// IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ)
// ----------------------------------------------------------------------------
#define bmEP8IBN		bmBIT5
#define bmEP6IBN		bmBIT4
#define bmEP4IBN		bmBIT3
#define bmEP2IBN		bmBIT2
#define bmEP1IBN		bmBIT1
#define bmEP0IBN		bmBIT0

// ----------------------------------------------------------------------------
// PING-NAK enable and request bits (NAKIE/NAKIRQ)
// ----------------------------------------------------------------------------
#define bmEP8PING		bmBIT7
#define bmEP6PING		bmBIT6
#define bmEP4PING		bmBIT5
#define bmEP2PING		bmBIT4
#define bmEP1PING		bmBIT3
#define bmEP0PING		bmBIT2
#define bmIBN			bmBIT0

// ----------------------------------------------------------------------------
// Interface Configuration bits (IFCONFIG)
// ----------------------------------------------------------------------------
#define bmIFCLKSRC		bmBIT7
#define bm3048MHZ		bmBIT6
#define bmIFCLKOE		bmBIT5
#define bmIFCLKPOL		bmBIT4
#define bmASYNC			bmBIT3
#define bmGSTATE		bmBIT2
#define bmIFCFG1		bmBIT1
#define bmIFCFG0		bmBIT0

#define bmIFCFGMASK	   (bmIFCFG0 | bmIFCFG1)
#define bmIFGPIF		bmIFCFG1

// ----------------------------------------------------------------------------
// EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG)
// ----------------------------------------------------------------------------
#define bmINFM			bmBIT6
#define bmOEP			bmBIT5
#define bmAUTOOUT		bmBIT4
#define bmAUTOIN		bmBIT3
#define bmZEROLENIN		bmBIT2
#define bmWORDWIDE		bmBIT0

// ----------------------------------------------------------------------------
// Chip Revision Control Bits (REVCTL) - used to ebable/disable revision
// specific features.
// ----------------------------------------------------------------------------
#define bmNOAUTOARM		bmBIT1
#define bmSKIPCOMMIT	bmBIT0

// ----------------------------------------------------------------------------
// FIFO polarity (FIFOPINPOLAR)
// ----------------------------------------------------------------------------
#define bmPKTEND        bmBIT5
#define bmSLOE          bmBIT4
#define bmSLRD          bmBIT3
#define bmSLWR          bmBIT2
#define bmEF            bmBIT1
#define bmFF            bmBIT0

// ----------------------------------------------------------------------------
// FIFO Reset bits (FIFORESET)
// ----------------------------------------------------------------------------
#define bmNAKALL		bmBIT7

// ----------------------------------------------------------------------------
// Chip Feature Register (GPCR2)
// ----------------------------------------------------------------------------
#define bmFULLSPEEDONLY	bmBIT4

#endif