Block Diagram

The first tab page presents a block diagram representing the logical connection of the FX/FX2 to an attached slave device. The configuration of this diagram controls the parameters available during creation of the four waveform descriptors (on the next 4 tab pages).

For instance, the number of CTL lines available when creating a waveform is configured using the block diagram.
Only one block diagram is saved in any GPIF Designer project file (*.GPF).
Once waveforms have been designed, changing the block diagram may give rise to undesired changes in the waveforms. For this reason, it is highly recommended that the first step in designing GPIF waveforms be the proper configuration of the Block Diagram.

Chip Selection

The first step in configuration of the block diagram should be to designate the Cypress FX/FX2 chip and pin-package for which you will be designing.

The large, blue, left rectange represents the FX/FX2 chip. Right-click in the main body of that rectangle to bring-up the chip-selection dialog box.

Changing chips, after waveforms have already been configured, will not erase those waveforms. However, because the available CTL and RDY lines may have changed, those waveforms may no longer represent what the designer had in mind. If you change chips after having designed waveforms, you should re-visit each waveform (paying special attention to STATUS and CTL Action Points) to verify their correctness.

Slave Labeling
The large, blue, right rectangle represents the device attached to the FX/FX2 chip. The label of this device can be modified by right-clicking in the main body of the rectangle. The label of the slave block has no impact whatever on the waveform generation. It is provided as a matter of convenience only. The label is saved, along with the block diagram, in GPIF Designer project files (*.GPF).
Clock Settings

Right-click on the Clock display area of the block diagram to bring-up the Clock Properties dialog box.

The Internal / External radio buttons of the dialog control the setting of the IFCLKSRC bit (b7) of the IFCONFIG register.

The Invert Clock checkbox (FX2 only) controls the setting of the IFCLKPOL bit (b4) of the IFCONFIG register.

The IFCLK Output checkbox (FX2 only) controls the setting of the IFCLKOE bit (b5) of the IFCONFIG register.

The 30MHz / 48MHz radio buttons (only available if Internal clock is selected) control the setting of the 3048MHZ bit (b6) of the IFCONFIG register.

When External Clock is selected, the Clock Frequency is only used to calculate the DeltaT displayed on the waveform editor tab pages. This setting has no impact on the GPIF waveform descriptor data that is exported to a GPIF.c file. Rather, it is useful to correctly depict time intervals during waveform editing.

Data Bus Selection
The second black data band, labelled Data [15:8], can be visually enabled and disabled by right-clicking on that band. This setting has no impact on any of the rest of the program or on the waveform descriptor data generated using the Tools | Export function.
ADR Line Configuration

Right-click on the group of ADR lines to bring-up the Config ADR Lines dialog box. The dialog enables individual or group selection of the address lines.
Like the Data Bus control, these settings have no implact on the rest of the program or on the waveform descriptor data generated by the Tools | Export function. They serve only to provide a visual reminder of the actual hardware application for which the waveform descriptors were designed.

RDY Line Configuration

The RDY lines are used in the definition of STATUS Action Points (also known as Decision Points) in the waveform editors. The names of the selected RDY lines are presented in the list of operands for a decision point. So, the proper configuration of the RDY lines is important.
To bring-up the Config RDY Lines dialog, right click on any of the block diagram's RDY lines.

The internal FIFO Flag is always available in the list of operands for a decision point. This dialog only allows you to change the name for this status line that will appear in the operand list. [When defining a waveform decision point, selection of the FIFO Flag operand will generate a value of 6 in the respective TERMA or TERMB fields of the LOGIC FUNCTION register for the state instruction.]
The Internal RDY line is always available in the list of operands for a decision point. This dialog only allows you to change the name for this status line that will appear in the operand list. [When defining a waveform decision point, selection of the Internal RDY operand will generate a value of 7 in the respective TERMA or TERMB fields of the LOGIC FUNCTION register for the state instruction.]
The Init val of Internal RDY radio buttons control the initial value of the Internal RDY status line. [They designate the initial value of the INTRDY bit (b7) of the GPIFREADYCFG register.]
Check the Sync RDY to IFCLK box if the RDY signals are synchronized to the internal clock signal. [Checking this box causes the SAS bit (b6) of GPIFREADYCFG to be set to 1.]
The transaction counter (TC) can be substituted for RDY line #5. Check the Subst TC for RDY 5 checkbox to implement the substitution. When this box is checked, RDY 5 becomes permanently available in the list of decision point operands. When the Subst TC for RDY 5 box is checked, the program places a default label of TCXpire for line #5. This label can be modified, even though RDY line #5 cannot be de-selected. [Checking this box sets the TCXRDY5 bit (b5) of the GPIFREADYCFG register to 1.]
The External Inputs can all be individually selected and labelled. Only the labels for selected lines are presented in the list of operands for a decision point. [When defining a waveform decision point, selection of the External Input RDY lines as an operand will generate a value between 0 and 5 in the respective TERMA or TERMB fields of the LOGIC FUNCTION register for the state instruction.]

CTL Line Configuration

To configure the CTL lines, right click on any of the block diagram's CTL lines.

The Lines Can Be Tri-Stated? radio buttons significantly impact the options available for CTL lines in both the block diagram and the waveform editors. If the lines can be tri-stated, a maximum of 4 CTL lines are available (3 for the 56-pin FX2). Also, tri-stateable lines cannot be configured for Open-drain output. [These Tri-Stated? radio buttons control the value of the TRICTL bit (b7) of the GPIFCTLCFG register.]
Once the Lines Can Be Tri-Stated? selection has been made, the CTL lines to be used should be selected and labelled. Only selected lines will be displayed and actionable in the waveform editors.
CTL Action Points placed on the waveforms have 2 or 3 available actions, depending on whether or not the lines have been configured as tri-stateable here.
If the lines cannot be tri-stated, select the output (CMOS vs Open-drain) for each line. [Bits 0-5 of GPIFCTLCFG register are set to 1, for the respective CTL lines, if Open-drain is selected. Selecting CMOS sets the respective bits to 0.]