commit 1254878a31e5a281b0e895c6f6c98446ea3165fc Author: Abu Abacus Date: Sat Jan 3 19:05:48 2026 +0100 Initial check in diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..8395b31 --- /dev/null +++ b/.gitignore @@ -0,0 +1,8 @@ +lst +obj + +bin +debug +release + + diff --git a/doc/AN65209 Getting Started.pdf b/doc/AN65209 Getting Started.pdf new file mode 100644 index 0000000..8b30de3 Binary files /dev/null and b/doc/AN65209 Getting Started.pdf differ diff --git a/doc/AN65209 Getting Started.zip b/doc/AN65209 Getting Started.zip new file mode 100644 index 0000000..49fcd5b Binary files /dev/null and b/doc/AN65209 Getting Started.zip differ diff --git a/doc/EZ-USB TRM.pdf b/doc/EZ-USB TRM.pdf new file mode 100644 index 0000000..a8ef9d3 Binary files /dev/null and b/doc/EZ-USB TRM.pdf differ diff --git a/doc/GPIF/AN57322 - GPIF-SRAM.pdf b/doc/GPIF/AN57322 - GPIF-SRAM.pdf new file mode 100644 index 0000000..72745b9 Binary files /dev/null and b/doc/GPIF/AN57322 - GPIF-SRAM.pdf differ diff --git a/doc/GPIF/AN57322 - GPIF-SRAM.zip b/doc/GPIF/AN57322 - GPIF-SRAM.zip new file mode 100644 index 0000000..f485c53 Binary files /dev/null and b/doc/GPIF/AN57322 - GPIF-SRAM.zip differ diff --git a/doc/GPIF/AN66806 - GPIF.pdf b/doc/GPIF/AN66806 - GPIF.pdf new file mode 100644 index 0000000..9daa08d Binary files /dev/null and b/doc/GPIF/AN66806 - GPIF.pdf differ diff --git a/doc/GPIF/AN66806 - GPIF.zip b/doc/GPIF/AN66806 - GPIF.zip new file mode 100644 index 0000000..984671b Binary files /dev/null and b/doc/GPIF/AN66806 - GPIF.zip differ diff --git a/doc/GPIF/GPIF Designer.exe b/doc/GPIF/GPIF Designer.exe new file mode 100644 index 0000000..101abb5 Binary files /dev/null and b/doc/GPIF/GPIF Designer.exe differ diff --git a/doc/GPIF/GPIF Designer/Designer.exe b/doc/GPIF/GPIF Designer/Designer.exe new file mode 100644 index 0000000..240cab8 Binary files /dev/null and b/doc/GPIF/GPIF Designer/Designer.exe differ diff --git a/doc/GPIF/GPIF Designer/PDFs/FX2_GPIF_Primer.pdf b/doc/GPIF/GPIF Designer/PDFs/FX2_GPIF_Primer.pdf new file mode 100644 index 0000000..4d5300e Binary files /dev/null and b/doc/GPIF/GPIF Designer/PDFs/FX2_GPIF_Primer.pdf differ diff --git a/doc/GPIF/GPIF Designer/PlugIns/GPIFExportPlugIn.dll b/doc/GPIF/GPIF Designer/PlugIns/GPIFExportPlugIn.dll new file mode 100644 index 0000000..ca7da2b Binary files /dev/null and b/doc/GPIF/GPIF Designer/PlugIns/GPIFExportPlugIn.dll differ diff --git a/doc/GPIF/GPIF Designer/PlugIns/GPIFImportPlugInFX.dll b/doc/GPIF/GPIF Designer/PlugIns/GPIFImportPlugInFX.dll new file mode 100644 index 0000000..075e168 Binary files /dev/null and b/doc/GPIF/GPIF Designer/PlugIns/GPIFImportPlugInFX.dll differ diff --git a/doc/GPIF/GPIF Designer/PlugIns/GPIFImportPlugInFX2.dll b/doc/GPIF/GPIF Designer/PlugIns/GPIFImportPlugInFX2.dll new file mode 100644 index 0000000..6786b40 Binary files /dev/null and b/doc/GPIF/GPIF Designer/PlugIns/GPIFImportPlugInFX2.dll differ diff --git a/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416 HPI.Opt b/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416 HPI.Opt new file mode 100644 index 0000000..3745de3 --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416 HPI.Opt @@ -0,0 +1,49 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.a*; *.src) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (Target 1), 0x0000 // Tools: 'MCS-51' +GRPOPT 1,(Source Group 1),1,0,0 + +OPTFFF 1,1,1,0,0,327,327,0,<.\fw.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,44,0,0,0,44,0,0,0,70,3,0,0,242,1,0,0 } +OPTFFF 1,2,2,218103808,0,3,8,0,<.\dscr.a51> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,22,0,0,0,22,0,0,0,44,3,0,0,216,1,0,0 } +OPTFFF 1,3,1,419430400,0,353,369,0,<.\FX2_to_TI5416_HPI.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,0,0,0,0,0,0,0,0,22,3,0,0,194,1,0,0 } +OPTFFF 1,4,1,0,0,1,1,0,<.\int0.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,88,0,0,0,88,0,0,0,114,3,0,0,12,2,0,0 } +OPTFFF 1,5,3,0,0,0,0,0, +OPTFFF 1,6,4,0,0,0,0,0, +OPTFFF 1,7,1,989855746,0,216,232,0,<.\gpif.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,110,0,0,0,110,0,0,0,105,3,0,0,162,1,0,0 } + + +TARGOPT 1, (Target 1) + CLK51=48000000 + OPTTT 1,1,1,0 + OPTHX 0,65535,0,0,0 + OPTLX 120,65,8,<.\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTDL (S8051.DLL)()(DP51.DLL)(-pFX2)(S8051.DLL)()(TP51.DLL)(-pFX2) + OPTDBG 49150,0,()()()()()()()()()() ()()()() + OPTKEY 0,(MON51)(-S1 -B38400 -O31) + OPTWA 0,1,(Tcount) + OPTWA 1,1,(EP6BCH) + OPTWA 2,1,(EP6BCL) + OPTWA 3,1,(GPIFTRIG) + OPTWA 4,1,(GPIFTCB1) + OPTWA 5,1,(GPIFTCB0) + OPTWA 6,1,(EP6FIFOBCH) + OPTWA 7,1,(EP6FIFOBCL) + OPTDF 0x84 + OPTLE <> + OPTLC <> +EndOpt + diff --git a/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416 HPI.Uv2 b/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416 HPI.Uv2 new file mode 100644 index 0000000..c57383c --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416 HPI.Uv2 @@ -0,0 +1,109 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (Target 1), 0x0000 // Tools: 'MCS-51' + +Group (Source Group 1) + +File 1,1,<.\fw.c> +File 1,2,<.\dscr.a51> +File 1,1,<.\FX2_to_TI5416_HPI.c> +File 1,1,<.\int0.c> +File 1,3, +File 1,4, +File 1,1,<.\gpif.c> + + +Options 1,0,0 // Target 'Target 1' + Device (EZ-USB FX2 (CY7C68XXX)) + Vendor (Cypress Semiconductor) + Cpu (IRAM(0 - 0xFF) XRAM(0 - 0x3FF) CLOCK(48000000) MODDP2) + Rgf (REG52.H) + Mem () + C () + A () + RL () + OH () + UseEnv=1 + EnvBin (C:\Keil\C51\BIN\) + EnvInc (c:\CYPRESS\USB\Target\Inc\;C:\Keil\C51\INC\) + EnvLib (C:\Keil\C51\LIB\) + EnvReg () + OrgReg () + TgStat=0 + OutDir (.\) + OutName (FX2_to_TI5416_HPI) + GenApp=1 + GenLib=0 + GenHex=1 + Debug=1 + Browse=0 + LstDir (.\) + HexSel=0 + MG32K=0 + RunUsr 0 1 + RunUsr 1 0 <> + SVCSID <> + MODEL5=0 + RTOS5=0 + ROMSZ5=2 + DHOLD5=0 + XHOLD5=0 + T51FL=304 + CBANKS5=0 + XBANKS5=0 + RCB51 { 0,0,0,0,0,255,255,0,0 } + RXB51 { 0,0,0,0,0,0,0,0,0 } + OCM51 { 0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCR51 { 0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IRO51 { 0,0,0,0,0,0,0,0,0 } + IRA51 { 0,0,0,0,0,0,1,0,0 } + XRA51 { 0,0,0,0,0,0,4,0,0 } + C51FL=21597456 + C51VA=0 + C51MSC () + C51DEF () + C51UDF () + INCC5 () + AX51FL=4 + AX51MSC () + AX51SET () + AX51RST () + INCA5 () + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + BankNo=65535 + LX51FL=288 + LX51OVL () + LX51MSC () + LX51DWN (16) + LX51LFI () + LX51ASN () + LX51RES () + LX51CCL () + LX51UCL () + LX51CSC () + LX51UCS () + LX51COB (0x80-0x0FFF) + LX51XDB (0x1000) + LX51PDB () + LX51BIB () + LX51DAB () + LX51IDB () + LX51PRC () + LX51STK () + LX51COS () + LX51XDS () + LX51BIS () + LX51DAS () + LX51IDS () + OPTDL (S8051.DLL)()(DP51.DLL)(-pFX2)(S8051.DLL)()(TP51.DLL)(-pFX2) + OPTDBG 49150,0,()()()()()()()()()() ()()()() +EndOpt + diff --git a/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416_HPI.c b/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416_HPI.c new file mode 100644 index 0000000..d3fb7b4 --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416_HPI.c @@ -0,0 +1,643 @@ +#pragma NOIV // Do not generate interrupt vectors +//----------------------------------------------------------------------------- +// File: FX2_to_extsyncFIFO.c +// Contents: Hooks required to implement FX2 GPIF interface to a TI +// 5416 DSP via it's HPI (Host Port Interface) +// +// Copyright (c) 2002 Cypress Semiconductor, Inc. All rights reserved +//----------------------------------------------------------------------------- +#include "fx2.h" +#include "fx2regs.h" +#include "fx2sdly.h" // SYNCDELAY macro, see Section 15.14 of FX2 Tech. + // Ref. Manual for usage details. + +#define HPI_RDY GPIFREADYSTAT & bmBIT0 // RDY0 +#define LED_ALL (bmBIT0 | bmBIT1 | bmBIT2 | bmBIT3) +#define bmEP0BSY 0x01 +#define bmEP1OUTBSY 0x02 +#define bmEP1INBSY 0x04 + +#define bmHPIC 0x00 // HCNTL[1:0] = 00 +#define bmHPID_AUTO 0x04 // HCNTL[1:0] = 01 +#define bmHPIA 0x08 // HCNTL[1:0] = 10 +#define bmHPID_MANUAL 0x0C // HCNTL[1:0] = 11 + +#define GPIFTRIGRD 4 + +#define GPIF_EP2 0 +#define GPIF_EP4 1 +#define GPIF_EP6 2 +#define GPIF_EP8 3 + +extern BOOL GotSUD; // Received setup data flag +extern BOOL Sleep; +extern BOOL Rwuen; +extern BOOL Selfpwr; + +BYTE Configuration; // Current configuration +BYTE AlternateSetting; // Alternate settings +static WORD xdata LED_Count = 0; +static BYTE xdata LED_Status = 0; +BOOL in_enable = FALSE; // flag to enable IN transfers +BOOL hpi_int = FALSE; // HPI interrupt flag +static WORD xdata Tcount = 0; // transaction count +BOOL enum_high_speed = FALSE; // flag to let firmware know FX2 enumerated at high speed +static WORD xFIFOBC_IN = 0x0000; // variable that contains EP6FIFOBCH/L value + +//----------------------------------------------------------------------------- +// Task Dispatcher hooks +// The following hooks are called by the task dispatcher. +//----------------------------------------------------------------------------- +void LED_Off (BYTE LED_Mask); +void LED_On (BYTE LED_Mask); +void GpifInit (); + +void GPIF_SingleByteWrite (BYTE gdata) +{ + while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit + { + ; + } + + XGPIFSGLDATLX = gdata; // trigger GPIF Single Byte Write transaction +} + + +void TD_Init(void) // Called once at startup +{ + // set the CPU clock to 48MHz + CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1); + SYNCDELAY; + + EP1OUTCFG = 0xA0; // always OUT, valid, bulk + EP1INCFG = 0xA0; // always IN, valid, bulk + SYNCDELAY; + EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered + SYNCDELAY; + EP4CFG = 0x00; // EP4 not valid + SYNCDELAY; + EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered + SYNCDELAY; + EP8CFG = 0x00; // EP8 not valid + SYNCDELAY; + + FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host + SYNCDELAY; + FIFORESET = 0x02; // reset EP2 FIFO + SYNCDELAY; + FIFORESET = 0x06; // reset EP6 FIFO + SYNCDELAY; + FIFORESET = 0x00; // clear NAKALL bit to resume normal operation + SYNCDELAY; + + EP2FIFOCFG = 0x00; // allow core to see zero to one transition of auto out bit + SYNCDELAY; + EP2FIFOCFG = 0x10; // auto out mode, disable PKTEND zero length send, byte ops + SYNCDELAY; + EP6FIFOCFG = 0x08; // auto in mode, disable PKTEND zero length send, byte ops + SYNCDELAY; + EP1OUTBC = 0x00; // arm EP1OUT by writing any value to EP1OUTBC register + + GpifInit (); // initialize GPIF registers + + PORTACFG = bmBIT0; // PA0 takes on INT0/ alternate function + OEA |= 0x0C; // initialize PA3 and PA2 port i/o pins as outputs + + EX0 = 1; // Enable INT0/ interrupt + IT0 = 1; // Detect INT0/ on falling edge +} + +void TD_Poll(void) +{ + + if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE + { + if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there's a packet in the peripheral domain for EP2 + { + IOA = bmHPID_AUTO; // select HPID register with address auto-increment + while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer + + SYNCDELAY; + GPIFTCB1 = EP2FIFOBCH; // setup transaction count with number of bytes in the EP2 FIFO + SYNCDELAY; + GPIFTCB0 = EP2FIFOBCL; + SYNCDELAY; + GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO + SYNCDELAY; + + while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit + { + ; + } + SYNCDELAY; + + } + } + + if(in_enable) // if IN transfers are enabled, + { + if(Tcount) // if Tcount is not zero + { + if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE + { + if( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full + { + IOA = bmHPID_AUTO; // select HPID register with address auto-increment + while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer + + SYNCDELAY; + GPIFTCB1 = MSB(Tcount); // setup transaction count with Tcount value + SYNCDELAY; + GPIFTCB0 = LSB(Tcount); + SYNCDELAY; + + GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6IN + SYNCDELAY; + + while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit + { + ; + } + + SYNCDELAY; + + xFIFOBC_IN = ( ( EP6FIFOBCH << 8 ) + EP6FIFOBCL ); // get EP6FIFOBCH/L value + + if( xFIFOBC_IN < 0x0200 ) // if pkt is short, + { + INPKTEND = 0x06; // force a commit to the host + } + Tcount = 0; // set Tcount to zero to cease reading from DSP HPI RAM + } + } + } + } + + if(!(EP01STAT & bmEP1OUTBSY)) + { + // handle OUTs to EP1OUT + } + + if(!(EP01STAT & bmEP1INBSY)) + { + // handle INs to EP1IN + } + + if (hpi_int) + { + hpi_int = FALSE; // clear HPI interrupt flag + EX0 = 1; // enable INT0 interrupt again + LED_On (bmBIT1); // turn on LED1 to alert user HPI interrupt occurred + } + + // blink LED0 to indicate firmware is running + + if (++LED_Count == 10000) + { + if (LED_Status) + { + LED_Off (bmBIT0); + LED_Status = 0; + } + else + { + LED_On (bmBIT0); + LED_Status = 1; + } + LED_Count = 0; + } + +} + +BOOL TD_Suspend(void) // Called before the device goes into suspend mode +{ + return(TRUE); +} + +BOOL TD_Resume(void) // Called after the device resumes +{ + return(TRUE); +} + +//----------------------------------------------------------------------------- +// Device Request hooks +// The following hooks are called by the end point 0 device request parser. +//----------------------------------------------------------------------------- + +BOOL DR_GetDescriptor(void) +{ + return(TRUE); +} + +BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received +{ + + if( EZUSB_HIGHSPEED( ) ) + { // FX2 enumerated at high speed + SYNCDELAY; + EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes + SYNCDELAY; + EP6AUTOINLENL = 0x00; + SYNCDELAY; + enum_high_speed = TRUE; + } + else + { // FX2 enumerated at full speed + SYNCDELAY; + EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes + SYNCDELAY; + EP6AUTOINLENL = 0x40; + SYNCDELAY; + enum_high_speed = FALSE; + } + + Configuration = SETUPDAT[2]; + return(TRUE); // Handled by user code +} + +BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received +{ + EP0BUF[0] = Configuration; + EP0BCH = 0; + EP0BCL = 1; + return(TRUE); // Handled by user code +} + +BOOL DR_SetInterface(void) // Called when a Set Interface command is received +{ + AlternateSetting = SETUPDAT[2]; + return(TRUE); // Handled by user code +} + +BOOL DR_GetInterface(void) // Called when a Set Interface command is received +{ + EP0BUF[0] = AlternateSetting; + EP0BCH = 0; + EP0BCL = 1; + return(TRUE); // Handled by user code +} + +BOOL DR_GetStatus(void) +{ + return(TRUE); +} + +BOOL DR_ClearFeature(void) +{ + return(TRUE); +} + +BOOL DR_SetFeature(void) +{ + return(TRUE); +} + +#define VX_B2 0xB2 // turn off LED1 +#define VX_B3 0xB3 // enable IN transfers +#define VX_B4 0xB4 // disable IN transfers +#define VX_B5 0xB5 // set Tcount value +#define VX_B6 0xB6 // write to HPIC register +#define VX_B7 0xB7 // write to HPIA register +#define VX_B8 0xB8 // reset EP6 FIFO +#define VX_B9 0xB9 // read GPIFTRIG register +#define VX_BA 0xBA // read GPIFTC registers + +BOOL DR_VendorCmnd(void) +{ + + switch (SETUPDAT[1]) + { + case VX_B2: // turn off LED1 + { + LED_Off (bmBIT1); + + *EP0BUF = VX_B2; + EP0BCH = 0; + EP0BCL = 1; // Arm endpoint with # bytes to transfer + EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request + break; + } + case VX_B3: // enable IN transfers + { + in_enable = TRUE; + + *EP0BUF = VX_B3; + EP0BCH = 0; + EP0BCL = 1; + EP0CS |= bmHSNAK; + break; + } + case VX_B4: // disable IN transfers + { + in_enable = FALSE; + + *EP0BUF = VX_B4; + EP0BCH = 0; + EP0BCL = 1; + EP0CS |= bmHSNAK; + break; + } + case VX_B5: // set Tcount value + { + EP0BCL = 0; + while(EP01STAT & bmEP0BSY); // wait until EP0 is available to be accessed by CPU + Tcount = (EP0BUF[0] << 8) + EP0BUF[1]; // load transaction count with EP0 values + + break; + } + case VX_B6: // write to HPIC register + { + EP0BCL = 0; // re-arm EP0 + while(EP01STAT & bmEP0BSY); // wait until EP0 is available to be accessed by CPU + while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer + IOA = bmHPIC; // select HPIC register + GPIFWFSELECT = 0x1E; // point to waveforms that write first byte of HPI protocol + GPIF_SingleByteWrite(EP0BUF[0]); // write LSB of DSP address + GPIFWFSELECT = 0x4E; // point to waveforms that write second byte of HPI protocol + GPIF_SingleByteWrite(EP0BUF[1]); // write MSB of DSP address + + break; + } + case VX_B7: // write to HPIA register + { + EP0BCL = 0; // re-arm EP0 + while(EP01STAT & bmEP0BSY); // wait until EP0 is available to be accessed by CPU + while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer + IOA = bmHPIA; // select HPIA register + GPIFWFSELECT = 0x1E; // point to waveforms that write first byte of HPI protocol + GPIF_SingleByteWrite(EP0BUF[0]); // write LSB of DSP address + GPIFWFSELECT = 0x4E; // point to waveforms that write second byte of HPI protocol + GPIF_SingleByteWrite(EP0BUF[1]); // write MSB of DSP address + + break; + } + case VX_B8: // reset EP6 FIFO + { + FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host + SYNCDELAY; + FIFORESET = 0x06; // reset EP6 FIFO + SYNCDELAY; + FIFORESET = 0x00; // clear NAKALL bit to resume normal operation + SYNCDELAY; + + *EP0BUF = VX_B8; + EP0BCH = 0; + EP0BCL = 1; + EP0CS |= bmHSNAK; + + break; + } + case VX_B9: // read GPIFTRIG register + { + EP0BUF[0] = VX_B9; + EP0BUF[1] = GPIFTRIG; + EP0BCH = 0; + EP0BCL = 2; + EP0CS |= bmHSNAK; + break; + } + case VX_BA: // read GPIFTC registers + { + EP0BUF[0] = VX_BA; + EP0BUF[1] = GPIFTCB1; + EP0BUF[2] = GPIFTCB0; + EP0BCH = 0; + EP0BCL = 3; + EP0CS |= bmHSNAK; + break; + } + default: + return(TRUE); + } + + return(FALSE); +} + +//----------------------------------------------------------------------------- +// USB Interrupt Handlers +// The following functions are called by the USB interrupt jump table. +//----------------------------------------------------------------------------- + +// Setup Data Available Interrupt Handler +void ISR_Sudav(void) interrupt 0 +{ + GotSUD = TRUE; // Set flag + EZUSB_IRQ_CLEAR(); + USBIRQ = bmSUDAV; // Clear SUDAV IRQ +} + +// Setup Token Interrupt Handler +void ISR_Sutok(void) interrupt 0 +{ + EZUSB_IRQ_CLEAR(); + USBIRQ = bmSUTOK; // Clear SUTOK IRQ +} + +void ISR_Sof(void) interrupt 0 +{ + EZUSB_IRQ_CLEAR(); + USBIRQ = bmSOF; // Clear SOF IRQ +} + +void ISR_Ures(void) interrupt 0 +{ + // whenever we get a USB reset, we should revert to full speed mode + pConfigDscr = pFullSpeedConfigDscr; + ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR; + pOtherConfigDscr = pHighSpeedConfigDscr; + ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR; + + EZUSB_IRQ_CLEAR(); + USBIRQ = bmURES; // Clear URES IRQ +} + +void ISR_Susp(void) interrupt 0 +{ + Sleep = TRUE; + EZUSB_IRQ_CLEAR(); + USBIRQ = bmSUSP; +} + +void ISR_Highspeed(void) interrupt 0 +{ + if (EZUSB_HIGHSPEED()) + { + pConfigDscr = pHighSpeedConfigDscr; + ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR; + pOtherConfigDscr = pFullSpeedConfigDscr; + ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR; + } + + EZUSB_IRQ_CLEAR(); + USBIRQ = bmHSGRANT; +} +void ISR_Ep0ack(void) interrupt 0 +{ +} +void ISR_Stub(void) interrupt 0 +{ +} +void ISR_Ep0in(void) interrupt 0 +{ +} +void ISR_Ep0out(void) interrupt 0 +{ +} +void ISR_Ep1in(void) interrupt 0 +{ +} +void ISR_Ep1out(void) interrupt 0 +{ +} +void ISR_Ep2inout(void) interrupt 0 +{ +} +void ISR_Ep4inout(void) interrupt 0 +{ +} +void ISR_Ep6inout(void) interrupt 0 +{ +} +void ISR_Ep8inout(void) interrupt 0 +{ +} +void ISR_Ibn(void) interrupt 0 +{ +} +void ISR_Ep0pingnak(void) interrupt 0 +{ +} +void ISR_Ep1pingnak(void) interrupt 0 +{ +} +void ISR_Ep2pingnak(void) interrupt 0 +{ +} +void ISR_Ep4pingnak(void) interrupt 0 +{ +} +void ISR_Ep6pingnak(void) interrupt 0 +{ +} +void ISR_Ep8pingnak(void) interrupt 0 +{ +} +void ISR_Errorlimit(void) interrupt 0 +{ +} +void ISR_Ep2piderror(void) interrupt 0 +{ +} +void ISR_Ep4piderror(void) interrupt 0 +{ +} +void ISR_Ep6piderror(void) interrupt 0 +{ +} +void ISR_Ep8piderror(void) interrupt 0 +{ +} +void ISR_Ep2pflag(void) interrupt 0 +{ +} +void ISR_Ep4pflag(void) interrupt 0 +{ +} +void ISR_Ep6pflag(void) interrupt 0 +{ +} +void ISR_Ep8pflag(void) interrupt 0 +{ +} +void ISR_Ep2eflag(void) interrupt 0 +{ +} +void ISR_Ep4eflag(void) interrupt 0 +{ +} +void ISR_Ep6eflag(void) interrupt 0 +{ +} +void ISR_Ep8eflag(void) interrupt 0 +{ +} +void ISR_Ep2fflag(void) interrupt 0 +{ +} +void ISR_Ep4fflag(void) interrupt 0 +{ +} +void ISR_Ep6fflag(void) interrupt 0 +{ +} +void ISR_Ep8fflag(void) interrupt 0 +{ +} +void ISR_GpifComplete(void) interrupt 0 +{ +} +void ISR_GpifWaveform(void) interrupt 0 +{ +} + +// ...debug LEDs: accessed via movx reads only ( through CPLD ) +// it may be worth noting here that the default monitor loads at 0xC000 +xdata volatile const BYTE LED0_ON _at_ 0x8000; +xdata volatile const BYTE LED0_OFF _at_ 0x8100; +xdata volatile const BYTE LED1_ON _at_ 0x9000; +xdata volatile const BYTE LED1_OFF _at_ 0x9100; +xdata volatile const BYTE LED2_ON _at_ 0xA000; +xdata volatile const BYTE LED2_OFF _at_ 0xA100; +xdata volatile const BYTE LED3_ON _at_ 0xB000; +xdata volatile const BYTE LED3_OFF _at_ 0xB100; +// use this global variable when (de)asserting debug LEDs... +BYTE xdata ledX_rdvar = 0x00; +BYTE xdata LED_State = 0; +void LED_Off (BYTE LED_Mask) +{ + if (LED_Mask & bmBIT0) + { + ledX_rdvar = LED0_OFF; + LED_State &= ~bmBIT0; + } + if (LED_Mask & bmBIT1) + { + ledX_rdvar = LED1_OFF; + LED_State &= ~bmBIT1; + } + if (LED_Mask & bmBIT2) + { + ledX_rdvar = LED2_OFF; + LED_State &= ~bmBIT2; + } + if (LED_Mask & bmBIT3) + { + ledX_rdvar = LED3_OFF; + LED_State &= ~bmBIT3; + } +} + +void LED_On (BYTE LED_Mask) +{ + if (LED_Mask & bmBIT0) + { + ledX_rdvar = LED0_ON; + LED_State |= bmBIT0; + } + if (LED_Mask & bmBIT1) + { + ledX_rdvar = LED1_ON; + LED_State |= bmBIT1; + } + if (LED_Mask & bmBIT2) + { + ledX_rdvar = LED2_ON; + LED_State |= bmBIT2; + } + if (LED_Mask & bmBIT3) + { + ledX_rdvar = LED3_ON; + LED_State |= bmBIT3; + } +} + diff --git a/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416_HPI.gpf b/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416_HPI.gpf new file mode 100644 index 0000000..428c57d Binary files /dev/null and b/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416_HPI.gpf differ diff --git a/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416_HPI.hex b/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416_HPI.hex new file mode 100644 index 0000000..8101347 --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/FX2_to_TI5416_HPI.hex @@ -0,0 +1,300 @@ +:0A0EB7000001020203030404050514 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Designer/dsp/app_note.htm new file mode 100644 index 0000000..1ab2db4 --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/app_note.htm @@ -0,0 +1,21 @@ + + +You need a browser that supports frame to veiw this page. + + + + + + + + + + + +<body bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> + +<p>You need a browser that supports frame to veiw this page.</p> +</body> + + + \ No newline at end of file diff --git a/doc/GPIF/GPIF Designer/dsp/app_note/Caption.htm b/doc/GPIF/GPIF Designer/dsp/app_note/Caption.htm new file mode 100644 index 0000000..d7d2fc5 --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/app_note/Caption.htm @@ -0,0 +1,24 @@ + + + +Index + + + + + + + + + +
+

 

+ 		+

DSP + DESIGN EXAMPLE

+ 		+

 

+
+
+ + diff --git a/doc/GPIF/GPIF Designer/dsp/app_note/DSPXactions.htm b/doc/GPIF/GPIF Designer/dsp/app_note/DSPXactions.htm new file mode 100644 index 0000000..8b0fd82 --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/app_note/DSPXactions.htm @@ -0,0 +1,1060 @@ + + + + + GPIF + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +

Implementing GPIF Transactions +

+ +

+ +
+ +

+

Creating + GPIF Waveform + Descriptors using GPIF Designer
 

+
+ +

+ +

+

In order to design + the GPIF waveform descriptors for this example, it is first important + to understand a little bit about how the TI DSP’s HPI protocol works. + Each HPI transfer is a two-byte sequence. The meaning of the first + byte and second byte depends on how the BOB bit is set in the DSP’s + HPIC register. In our example, the BOB bit is set to 1, which means + that the first byte of the HPI transfer is going to be the LSB and + the second byte of the transfer is going to be the MSB (as organized + in the DSP memory).

+

The example uses GPIF + single write transactions for writing to the HPIC and HPIA registers, + GPIF FIFO Write transactions for writing data into the HPI RAM, + and GPIF FIFO Read transactions for reading data from the HPI RAM. + Writing to the HPIC and HPIA registers is a special case that requires + two separate waveform behaviors to describe the entire HPI transfer. + One waveform behavior describes the timing and control logic for + the first byte of the HPI transfer, and another describes the timing + and control logic for the second byte of the HPI transfer.

+

In all of the GPIF + waveforms, CTL0-2 are manipulated according to the HPI protocol + and the HPI8 Mode Timing Requirements as outlined in the 5416 data + sheet. In the text to follow, we will discuss how CTL0-2 were manipulated + in the GPIF waveforms to describe the HPI protocol. Figure 23 + shows the block diagram for the DSP example.

+


Figure + 23. GPIF Designer Block Diagram View

+

Figure 24, + below, shows waveform 0, which characterizes the behavior of the + waveform called SnglWr1. SnglWr1 describes the HPI protocol required + to write the first byte of an HPI transfer.

+


Figure + 24. SnglWr1 waveform in GPIF Designer

+

Since SnglWr1 describes + an HPI write operation, HR/W (CTL0) is held LOW throughout the entire + transfer (S0-S2). HBIL (CTL2) is dropped LOW in S0 to signify that + the first byte is being transferred. This is done before HDS1 (CTL1) + is asserted in S1, in order to satisfy the set-up time requirement + for HBIL before HDS1 can be made LOW. Since S0 is active for 20.83 + ns (Wait 1 at 48-MHz IFCLK), this satisfies the set-up time requirement + of 6 ns for HBIL. Since there is also a hold time requirement for + HBIL, to simplify matters, HBIL is actually held LOW throughout + the active portion of the entire waveform.

+

By looking at the + HPI8 Timing Requirements in the 5416 data sheet, it becomes apparent + that any of the strobe widths or set-up and hold times are well + under 20.83 ns. Therefore, one can assume that a state need only + last at maximum 20.83 ns (Wait 1). In S1, data is also placed on + the bus (Activate Data). In S2, HDS1 is deasserted, thus ending + this portion of the HPI transfer. S2 also unconditionally branches + to the IDLE state to terminate the waveform.

+

The waveform that + describes the second portion of the HPI transfer is very similar + to SnglWr1, and is shown in Figure 25.

+


Figure + 25. SnglWr2 waveform in GPIF Designer

+

Again, since SnglWr2 + also describes an HPI write operation, HR/W is held LOW throughout + the entire active portion of the waveform (S0–S2). The main difference + between SnglWr2 and SnglWr1 is the state of HBIL; HBIL is HIGH throughout + S0–S2. This signifies to the HPI that the second byte of the HPI + transfer is being transmitted. S2 unconditionally branches to the + IDLE state to terminate the waveform.

+

To recap, the SnglWr1 + and SnglWr2 waveforms are used for GPIF single write accesses, which + allow us to write to the DSP’s HPIC/HPIA registers. The GPIF engine + allows you to select which of these waveforms are triggered by a + GPIF single write access, via the GPIFWFSELECT register. Consecutive + GPIF single write accesses using the waveforms SnglWr1 and SnglWr2 + are made to describe the entire HPI transfer protocol. The details + of this are described in the firmware programming section (4.2.5).

+

To create the GPIF + FIFO read and write accesses that handle writing and reading to + and from the HPI data RAM, the attributes of the SnglWr1 and SnglWr2 + waveforms can be combined to form each of the GPIF FIFO read and + write waveforms. Figure 26 shows the GPIF FIFO write waveform.

+


Figure + 26. FIFOWr waveform in GPIF Designer

+

Waveform 3 (FIFOWr) + describes an entire HPI write transfer. S0 drives both HR/W and + HBIL LOW for 20.83 ns, then S1 asserts HDS1 and drives the data + bus to present the first byte in the EP2 FIFO, effectively writing + out the first byte of the HPI transfer to the HPI RAM. S2 then increments + the FIFO pointer using Next FIFO data, deasserts HDS1, and drives + HBIL HIGH to tell the HPI the second byte of the transfer is coming. + S3 asserts HDS1 again and drives the data bus to present the second + byte in the EP2 FIFO, effectively writing out the second byte of + the HPI transfer to the HPI RAM.

+

The waveform then + traverses to S5, a decision point state that examines the GPIF TC + to determine whether or not to branch to the IDLE state. If the + GPIF TC has not yet expired, the waveform will then branch back + to S0 to actuate another HPI transfer. Otherwise, the waveform branches + to the IDLE state and terminates. The FIFO read waveform is quite + similar in nature and is shown in Figure 27.

+


Figure + 27. FIFORd waveform in GPIF Designer

+

Waveform 2 (FIFORd) + describes an entire HPI read transfer. HR/W is driven HIGH throughout + the waveform to tell the HPI that this is a read operation. In S0, + HBIL is driven LOW for 20.83 ns to satisfy the set-up time requirement + for HBIL, then S1 asserts HDS1, which tells the HPI to present the + first byte of the HPI read transfer onto the data bus. The data + is not presented until 10ns later, therefore it is correct to only + sample the databus in S2 and not in S1. By sampling the databus + in S2, the first byte is read into the FX2’s EP6 FIFO. For a GPIF + FIFO read transaction, an Activate Data also advances the FIFO pointer, + so a Next FIFO data is not necessary.

+

S2 also drives HBIL + HIGH to tell the HPI the second byte of the transfer is expected. + S3 asserts HDS1 again and S4 samples the data bus to read the second + byte into the EP6 FIFO.

+

The waveform then + traverses to S5, a decision point state that examines the GPIF TC + to determine whether or not to branch to the IDLE state. If the + GPIF TC has not yet expired, the waveform will then branch back + to S0 to actuate another HPI read transfer. Otherwise, the waveform + branches to the IDLE state and terminates.

+

Now that you understand + how the GPIF waveforms are programmed and set up for the DSP example, + the firmware programming can be discussed.
 

+
+

Firmware

+
+

+ After the GPIF waveforms were implemented using + GPIF Designer, the next step was to integrate the USB portion of the overlying + firmware with the GPIF Designer output to perform write and read operations to and from the HPI. To do this a firmware frameworks + project was copied and the code that performed the HPI operations was added to the TD_Poll() function within + FX2_to_TI5416_HPI.c (note that periph.c was renamed to something more meaningful here). Endpoint and GPIF register initialization + is performed in the TD_Init() function, which is also within FX2_to_TI5416_HPI.c.
+

When the user opens up the Keil uVision2 + project for the DSP example, Figure 17 shows the list of files that should be seen in the Project Window:

+ +

    +
+Figure 17
+

    +

    The + contents of these files is as follows:
    +

    +
+ +
+
    +

    fw.c
    Firmware + frameworks which handles USB requests and calls the task dispatcher + TD_Poll(). 

    +
+ +
+
    +

    Ezusb.lib
    Collection + of functions that handle suspend, resume, I2C operations, etc. 

    +
+ +
+
    +

    USBJmpTb.OBJ
    Interrupt + vector jump table for USB (INT2) and GPIF/Slave FIFO (INT4) + interrupt sources. 

    +
+ +
+
    +

    dscr.a51
    Device + descriptor tables for the DSP example which report EP2OUT and + EP6IN as available endpoints for the FX2 device. EP1IN and EP1OUT + are also reported although they are not used in this example. + These low bandwidth endpoints may be used for general purpose + should the need arise in an application. 

    +
+ +
+
    +

    gpif.c
    File + that contains the GPIF waveform descriptor tables that implement + the DSP GPIF transaction waveform behavior.

    +
+ +
+
    +

    FX2_to_extsyncFIFO.c
    Main + user application code where TD_Poll() and TD_Init() can be found. + The user will mainly be modifying this particular file and will + not need to touch fw.c.

    +
+ +
+
    +

    int0.c
    File + that contains the interrupt service routine for servicing the + INT0/ interrupt. 

    +
+
+ +
    +TD_Init( )  + +
+ +
+
    + +

    +The first task at hand was to setup the endpoints appropriately for this example. The following code switches the CPU clock speed + to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, and EP6 + as a Bulk IN endpoint, also 4x buffered of size 512. This setup utilizes the maximum allotted 4 KB FIFO space. It also sets up the + FIFOs for auto mode, byte wide operation, and goes through a FIFO reset and arming sequence to ensure that they are ready + for data operations. EP1IN and EP1OUT are also setup in case the application needs them, although they are not used by this + example.
    +     +

+
+
+
    +// set the CPU clock to 48MHz
    + CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
    + SYNCDELAY;
    +
    + EP1OUTCFG = 0xA0; // always OUT, valid, bulk
    + SYNCDELAY;
    + EP1INCFG = 0xA0; // always IN, valid, bulk
    + SYNCDELAY;
    + EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
    + SYNCDELAY;
    + EP4CFG = 0x00; // EP4 not valid
    + SYNCDELAY;
    +
    + EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered
    + SYNCDELAY;
    + EP8CFG = 0x00; // EP8 not valid
    + SYNCDELAY;
    +
    + FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
    + SYNCDELAY;
    + FIFORESET = 0x02; // reset EP2 FIFO
    + SYNCDELAY;
    + FIFORESET = 0x06; // reset EP6 FIFO
    + SYNCDELAY;
    + FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
    + SYNCDELAY;
    +
    + EP2FIFOCFG = 0x00; // allow core to see zero to one transition of auto out bit
    + SYNCDELAY;
    + EP2FIFOCFG = 0x10; // auto out mode, disable PKTEND zero length send, byte ops
    + SYNCDELAY;
    + EP6FIFOCFG = 0x08; // auto in mode, disable PKTEND zero length send, byte ops
    + SYNCDELAY;
    + EP1OUTBC = 0x00; // arm EP1OUT by writing any value to EP1OUTBC register
    + SYNCDELAY;
    +
    + GpifInit (); // initialize GPIF registers
    +
    + PORTACFG = bmBIT0; // initialize PA3 and PA2 port i/o pins as outputs,
    + OEA |= 0x0C; // PA0 takes on INT0/ alternate function
    +
    + EX0 = 1; // Enable INT0/ interrupt
    + IT0 = 1; // Detect INT0/ on falling edge

     +
+ +
+ +
+ +
    +IFCONFIG Register
    + +     +
+ +
+
    + +

    +TD_Init then calls the function GPIFInit() which resides in gpif.c. GPIFInit() is where the loading of the GPIF waveform descriptor + table into on-chip memory takes place and other GPIF registers get setup. An important register, IFCONFIG, also gets setup here + to define how the physical interface operates. Table 4 goes through the reasoning behind the setup of the IFCONFIG register for + this example.
    +
    + The last thing TD_Init does is it setups up PA3 and PA2 as outputs and enables the INT0/ functionality.
    +     +

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

Bit + #

+ 		+

Bit + Label

+ 		+

Contents + / Description

+
+

7

+ 		+

IFCLKSRC

+

Set + to 1 to run the GPIF using the internal clock source

+ +
+

6

+ 		+

3048MHz

+ 		+

Set to 1 to run the + internal clock source for the GPIF at 48MHz.

+
+

5

+ 		+

IFCLKOE

+ 		+

Set to 1 to turn on + the IFCLK output to drive the WCLK and RCLK inputs of + the external FIFO.

+
+

4

+ 		+

IFCLPOL

+ 		+

Set to 0.

+
+

3

+ 		+

ASYNC

+ 		+

Set to 0 to operate + the GPIF at the highest rate (sync mode).

+
+

2

+ 		+

GSTATE

+ 		+

Set to 1 to turn on + the debug outputs of the state machine. PE[2:0] displays + the states the GPIF engine cycles through during each + transaction (Note: PE[2:0] are only available on the + 100- and 128-pin packages).

+
+

1

+ 		+

IFCFG1

+ 		+

Set to 1 to put the + FX2 part into GPIF mode (internal master).

+
+

0

+ 		+

IFCFG0

+ 		+

Set to 0 to put + the FX2 part into GPIF mode (internal master).

+
+

Table 4. IFCONFIG register bit settings for FIFO example
+
+

+ +
+
    + +

    + The next thing TD_Init() does is it resets the external FIFO by pulsing PA2. This ensures that the external FIFO is at a + ground-zero state before commencing data operations. The following code does the trick:
    + +     +

+ +
+ +

+

+
    +// reset the external FIFO
    +
    + OEA |= 0x04; // turn on PA2 as output pin
    + IOA |= 0x04; // pull PA2 high initially
    + IOA &= 0xFB; // bring PA2 low
    + EZUSB_Delay (1); // keep PA2 low for ~1ms, more than enough time
    + IOA |= 0x04; // bring PA2 high
    +     +
+ +
+ +
+
    + +

    +A vendor command was also setup in the DR_VendorCmnd() function so that the user could reset the external FIFO at any time by + performing a vendor request of 0xB2 from the EZ-USB Control Panel.  +

+
+ +
    +

    Writing to the HPIC and HPIA registers
    +     +

+
+
    + +

    +The firmware implements a 0xB6 IN vendor command and a 0xB7 IN vendor command to write to the HPIC and HPIA registers, + respectively. The following code writes to the HPIC register: +

      +

      case VX_B6: // write to HPIC register
      + {
      +
      +     EP0BCL = 0; // re-arm EP0
      +     while(EP01STAT & bmEP0BSY); // wait until EP0 is available to be accessed by CPU
      +     while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer
      +     IOA = bmHPIC; // select HPIC register
      +     GPIFWFSELECT = 0xE4; // point to waveforms that write first byte of HPI protocol
      +     GPIF_SingleByteWrite(EP0BUF[0]); // write LSB of DSP address
      +     GPIFWFSELECT = 0xA4; // point to waveforms that write second byte of HPI protocol
      +     GPIF_SingleByteWrite(EP0BUF[1]); // write MSB of DSP address
      +
      +     break;
      + }

      +
    +

    The first thing the code does is it re-arms the EP0 buffer to accept the next packet from the host. It then waits until the EP0 buffer + is available for the CPU to access. Before addressing the HPIC register, the code checks to see if the HPI is ready to accept + another transfer. The HPIC register is then addressed by writing a 0 to both PA3 and PA2.
    +
    The technique of changing the waveform index in the GPIFWFSELECT register to point to different waveforms is useful for + handling protocols such as the HPI, where more than one waveform behavior is required to describe a complete read/write cycle. + The GPIFWFSELECT register is first configured to point to the SnglWr1 waveform which writes the first byte of the HPI protocol. + This is now the waveform that gets triggered when a GPIF single write access occurs. The first byte in EP0BUF is then written + out to the HPI. The GPIFWFSELECT register is then configured to point to the SnglWr2 waveform which writes the second byte + of the HPI protocol. This is now the waveform that gets triggered when a GPIF single write access occurs. The second byte in + EP0BUF is then written out to the HPI. Because the HPI protocol calls out that both first and second bytes in the HPI transfer + should be of equal value when writing to the HPIC register, the host should send down two bytes of equal value when performing + the vendor IN request of 0xB6.

    +


    The following code writes to the HPIA register:

    +
    + case VX_B7: // write to HPIA register
    + {
    +
    +     EP0BCL = 0; // re-arm EP0
    +     while(EP01STAT & bmEP0BSY); // wait until EP0 is available to be accessed by CPU
    +     while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer
    +     IOA = bmHPIA; // select HPIA register
    +     GPIFWFSELECT = 0xE4; // point to waveforms that write first byte of HPI protocol
    +     GPIF_SingleByteWrite(EP0BUF[0]); // write LSB of DSP address
    +     GPIFWFSELECT = 0xA4; // point to waveforms that write second byte of HPI protocol
    +     GPIF_SingleByteWrite(EP0BUF[1]); // write MSB of DSP address
    +
    +     break;
    + }
     +
    + +

    +The first thing the code does is it re-arms the EP0 buffer to accept the next packet from the host. It then waits until the EP0 buffer + is available for the CPU to access. Before addressing the HPIA register, the code checks to see if the HPI is ready to accept + another transfer. The HPIA register is then addressed by writing a 1 to PA3 and a 0 to PA2.

    The GPIFWFSELECT register is then configured to point to the SnglWr1 waveform which writes the first byte of the HPI protocol. + This is now the waveform that gets triggered when a GPIF single write access occurs. The first byte in EP0BUF is then written + out to the HPI. The GPIFWFSELECT register is then configured to point to the SnglWr2 waveform which writes the second byte + of the HPI protocol. This is now the waveform that gets triggered when a GPIF single write access occurs. The second byte in + EP0BUF is then written out to the HPI. When the host performs the vendor IN request of 0xB7, the first byte contains the LSB of + the DSP address, and the second byte contains the MSB of the DSP address.
    +       +

+
+ +

+ +

    +Performing Data Writes and Reads to and from the HPI +
+ +
+
    + +

    +The code in TD_Poll() handles USB OUT transfers (Data Writes to the HPI) and USB IN transfers (Data Reads from the HPI).
    +
    + Code that handles USB OUT Transfers     +

      + +

      +if ( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
      + {
      +     if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there's a packet in the peripheral domain for EP2
      +     {
      +         IOA = bmHPID_AUTO; // select HPID register with address auto-increment
      +         while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer
      +
      +         SYNCDELAY;
      +         GPIFTCB1 = EP2FIFOBCH; // setup transaction count with number of bytes in the EP2 FIFO
      +         SYNCDELAY;
      +         GPIFTCB0 = EP2FIFOBCL;
      +         SYNCDELAY;
      +         GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
      +         SYNCDELAY;
      +
      +         while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
      +         {
      +            ;
      +         }
      +
      +         SYNCDELAY;
      +     }
      + }       +

    + +

    +The first thing the OUT handling code does is it checks to see if the GPIF is IDLE. If so, it checks to see if there is at least a packet + in the peripheral domain for EP2. Since EP2 is placed into auto mode, the firmware does not need to check if the host sent a + USB packet. The USB packets are automatically committed to be used by the GPIF engine. Therefore, the firmware's job is to + check if at least one packet has been committed to the peripheral domain.
    +
    + The TC value is then simply setup with the number of bytes in the EP2 FIFO. This allows the user to handle packet sizes less + than 512 but greater than zero. The TC value is a 32-bit register field, but for this application only the lower 16-bit fields are used.
    +
    + A write to the GPIFTRIG register with the appropriate bits triggers the transaction from EP2OUT. The code then waits for the + transaction to complete before exiting out of the if nest.

    Code that handles USB IN transfers     +

      + +

      +if(in_enable) // if IN transfers are enabled,
      + {
      +     if(Tcount) // if Tcount is not zero
      +     {
      +         if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
      +         {
      +             if( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full
      +             {
      +                 IOA = bmHPID_AUTO; // select HPID register with address auto-increment
      +                 while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer
      +
      +                 SYNCDELAY;
      +                 GPIFTCB1 = MSB(Tcount); // setup transaction count with Tcount value
      +                 SYNCDELAY;
      +                 GPIFTCB0 = LSB(Tcount);
      +                 SYNCDELAY;
      +                 GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6IN
      +                 SYNCDELAY;
      +
      +                 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
      +                 {
      +                    ;
      +                 }
      +
      +                 SYNCDELAY;
      +                 xFIFOBC_IN = ( ( EP6FIFOBCH << 8 ) + EP6FIFOBCL ); // get EP6FIFOBCH/L value
      +
      +                 if( xFIFOBC_IN < 0x0200 ) // if pkt is short,
      +                 {
      +                      INPKTEND = 0x06; // force a commit to the host
      +                 }
      +                 Tcount = 0; // set Tcount to zero to cease reading from DSP HPI RAM
      +             }
      +         }
      +     }
      + }       +

    + +

    +If the in_enable flag is not set via vendor IN command 0xB3, the code will just sit there and not process the INs. If the in_enable + flag is set, and then if Tcount is not zero (read along for a further explanation of the Tcount variable), the code will fall through + and check if the GPIF interface is IDLE. It then determines if EP6 is not full, implying that it has room for at least one more data + packet.
    +
    + If EP6 has room for at least one more data packet, the TC value is setup with a user defined value of Tcount. The value of Tcount + is setup prior to the IN transfer and can be done so by executing the vendor OUT command 0xB5. For example, if the user wanted + to read 4KB worth of information from the HPI, the user would send a value of 0x1000 using the vendor OUT command 0xB5. + This requires that the user should have a priori knowledge of how much data is going to be read.
    +
    + A write to the GPIFTRIG register with the appropriate bits triggers the transaction to fill the EP6 FIFO. The code then waits for + the transaction to complete. Since EP6 is placed into auto mode, there is no need to explicitly write a byte count value to indicate + how many bytes to send to the host. FX2 uses the EP6AUTOINLENH/L register values set at enumeration time in the + DR_SetConfiguration() function for the auto commit size.
    +
    + However, to handle packets sizes less than 512 (the last packet of the transfer will typically be short), the code checks to see if + it needs to write to the INPKTEND register with a 0x06 to commit the short packet to the host. The Tcount variable is then set to + zero to prevent from entering the loop again. Now we see the relevance of the upper if statement that checks for Tcount. If the + statement was not present, the code would continously fill EP6IN as the host requests IN after IN. This complicates matters on + the host side becasue when the next transfer is started, stray buffers from the previous transfer would be retrieved by the host. + By checking if Tcount is greater than zero, the user would be forced to set the Tcount variable to the desired value to start another + transfer.
    +       +

+
+ + +
    +

    Handling INT0 +

+
+ +
    + +

    +The HINT/ output is connected to the INT0/ interrupt on the FX2. This allows the 5416 to perform software handshaking with the + FX2 when necessary. The INT0/ interrupt is handled via the following ISR:
     +

      + +

      +void int0_isr (void) // interrupt 0
      + {
      +     hpi_int = TRUE; // HPI interrupted the FX2
      +     EX0 = 0; // disable INT0/ interrupt, let foreground re-enable it
      + }
      +       +

    + +

    +The ISR sets a global flag hpi_int which is monitored by TD_Poll(). The code in TD_Poll then clears the hpi_int flag and turns on + LED1 on the FX2 development board:
    +     +

      + +

      +if (hpi_int)
      + {
      +     hpi_int = FALSE; // clear HPI interrupt flag
      +     EX0 = 1; // enable INT0 interrupt again
      +     LED_On (bmBIT1); / turn on LED1 to alert user HPI interrupt occurred
      + }
      +       +

    + +

    +A vendor IN command of 0xB2 is provided so that the user can turn off LED1.
    +
          +

+
+ +

Running the DSP + example
 

+ + +

+Now that the user has a good idea how this DSP example works, we can now attempt to read and write to the HPI and later on bootload the DSP code.

Step 1: Download the firmware using the EZ-USB Control Panel
 +

    +

    a) + Unzip the "FX2_to_TI5416_HPI GPIF FIFO Transactions Auto Mode.zip" package in the C:\Cypress\USB\Examples\FX2 directory.

    +

    b) + Plug in the 5416 DSK board and launch the Code Composer Studio for the 5416.

    +

    c) + After the user plugs-in the FX2 board, launch the EZ-USB Control Panel and ensure that the selected target is FX2.

    +

    d) + Then, press the Download button and select the FX2_to_TI5416_HPI.hex file. The FX2 board renumerates as a Cypress EZ-USB Sample Device and LED0 should come up flashing.

    +

    e) + Perform a Get Pipes and Get Dev to verify one more time that the firmware is up and running. The user should then see the following screen shown below:

    +

+ +


 

+
+ +

+Step 2: Perform a write to the HPI
 +

    +

    a) + Launch Code Composer Studio and pull up the Memory window at 0x7000. This will allow the user to monitor if the writes occurred correctly.

    +

    b) + Perform a vendor OUT command of 0xB6 to write to the HPIC register using data values 0x01 0x01. This sets the BOB to + 1 in the HPIC register so that the first byte of future HPI transfers is the LSB and the second byte is the MSB (as organized in DSP memory)

    +

    c) + Perform a vendor OUT command of 0xB7 to write to the HPIA register with the address of 0x7000. Notice the ordering of the data in the hex bytes field since the BOB bit has been set to 1.

    +

    d) + Perform another vendor OUT command of 0xB6 to write to the HPIC register using data values 0x11 0x11. This keeps the + BOB bit set at 1 and sets the XPHIA bit. Setting the XPHIA bit does two things: 1) it allows the address to auto-increment for + consecutive data accesses to HPI and 2) the next write to the HPIA register contains the extended address value.

    +

    e) + Perform another vendor OUT command of 0xB7 to write the extended address value into the HPIA register. The value is 0x00 0x00 since the address 0x7000 lies within the first page of DSP memory.

    +

    f) + Select Endpoint 2 OUT as the Pipe, press the FileTrans .. buttion and select the 512_count.hex file. Click on Open and + this action will send out 512 bytes of ramp data to the HPI.

    +
+

    + +

    +
    Since the auto-increment mode is used to write data to the HPI, the first data value will appear at 0x7001 since the HPI pre-increments the address + prior to the data write. If the user wanted the first data value to appear at 0x7000, the address to write to the HPIA register would have been 0x6FFF.
    +
    + The user could have also used the Bulk Trans button to send a specific data pattern to the HPI.
    +
    + The Memory window of Code Composer Studio indicates the HPI write was successful.
    +

+ + + +

 
 

+ +

+Step 3: Perform a Read from the HPI +

    +

    To read from a specific address in the DSP, the user should perform steps a. through e. as listed in Step 2. For HPI auto-increment + reads, the DSP post-increments the address for a data read, so the user can exactly specify the address to read from. In this + instance, we will read back the data values previously written in step 2. We will read 768 bytes to illustrate that the FX2 firmware + can handle short packets (since 768 is not an even divisor of 512).

    +

    a) + Perform a 0xB5 vendor OUT command to set the Tcount variable to 768 (0x0300). This sets up the GPIF to read 768 bytes from the HPI.

    +

    b) + Pend an IN request for 768 bytes on Endpoint 6 IN.

    +

    c) + Perform a 0xB3 vendor IN command to set the in_enable flag to TRUE. 768 bytes worth of data should now be displayed + on the EZ-USB Control Panel window. Note that the data values are the same as the ones previously written by the HPI + write, thus proving that the read was a success.

    +
+ +

+

 

+
+ + +

+Step 4: Bootloading the DSP code
 +

    +

    + A host processor can download the DSP code via the HPI and bootload it by writing the entry point of the program to location + 0x7E and 0x7F in DSP data memory. This is a common method used to bootload a TI DSP. To force the 5416 to use the HPI as + the bootload method, the HINT/ and INT2/ pins are tied together. The host processor just needs to then download the code, write + the entry point, and the DSP program starts running. For simplicity sake, this example chose to use the LED code supplied in the + 5416 DSK software. Once the bootload is complete, the user LED0 on the DSK board starts flashing.
    +
    + The bootloading techniques used in this example are very similar to those explained in the TI appnote SPRA382. Code Composer + Studio generates a .out executable file that follows the Common Object File Format (COFF). This .out file cannot be simply + downloaded to the DSP. The program and data sections need to be extracted by running a COFF Hex Extraction Utility on the + .out file. This utility is available with the SPRA382 appnote. After typing in the command coff_both -out led.out, the utility creates + a hex listing that is called led.out.c.
    +
    + A PC application created in MS VC++ 6.0 called HPIMr (short for HPI Manager) reads in this hex listing, determines the start + address of each section, and writes each section of code/data to the FX2's Endpoint 2 OUT. Prior to writing each block of + code/data, the sequence of 0xB6 and 0xB7 vendor OUT commands are performed to write to the HPIC/HPIA registers (similar + to Step 2). The source code for the HPIMr utility is provided if the user is interested in seeing how this is done. This utility can + also serve as another host application example.
    +
    + These are the steps the user should follow to download the LED example:

    +

    a) + Plug in the 5416 DSK board, plug in the FX2 development board.

    +

    b) + Download the FX2_to_TI5416_HPI.hex firmware.

    +

    c) + Run the HPIMr.exe utility. The user should see the following screen if an FX2 development board is plugged in.

    +
      +

      +

    +

     

    +

    d) + Next, click on the Send Program to HPI button and select the led.out.c file. Click on Open.

    + +
      +


      +
      +       +

    +

    The user should should now see the user LED0 flashing on the 5416 DSK board.

    + +
      +


              +

    +
+
+

Logic + Analyzer Traces

These are the traces the user should + see on the logic analyzer as the DSP example runs. +  The traces were captured using an HP1660C logic analyzer.

 

+

Writing to HPIC: + Zoomed out view

This trace shows what the user should see when a 0xB6 vendor OUT command is performed to write to the HPIC register + (HCNTL=00). The first byte of the HPI transfer is followed by IDLE time, where the FX2 firmware is switching to the GPIF single + write waveform that writes the second byte of the HPI transfer. A similar waveform can be observed when a 0xB7 vendor OUT + command is performed to write to the HPIA register.
+

+

 

+

Writing to HPIC: Close-up view of 1st byte of HPI transfer


Here we see a close-up view of the 1st byte of a HPI write to the HPIC register. A write operation is signified by HR/W/ being + driven low. HBIL is also driven low to signify that this is the 1st byte of the HPI transfer. The timing shown here adheres to the + HPI8 Mode Timing Requirements in the 5416 datasheet. A similar waveform can be observed when a 0xB7 vendor OUT + command is performed to write to the HPIA register.
+

 

 

Writing to HPIC: Close-up view of 2nd byte of HPI transfer


Here we see a close-up view of the 2nd byte of a HPI write to the HPIC register. A write operation is signified by HR/W/ being + driven low. HBIL is now driven high to signify that this is the 2nd byte of the HPI transfer. The timing shown here adheres to the + HPI8 Mode Timing Requirements in the 5416 datasheet. A similar waveform can be observed when a 0xB7 vendor OUT + command is performed to write to the HPIA register.
+

 

 

FIFO Write to HPI: Zoomed out view
+

This is a snapshot of the activity that goes on when the FX2 performs a burst write to the HPI using GPIF FIFO Write transactions. + A similar waveform can be observed when the FX2 performs a burst read from the HPI using GPIF FIFO Read transactions.

 

 

FIFO Write to HPI: Close-up view


Here we see a close-up view of a write to the HPI using GPIF FIFO Write transactions. S0-S5 marks the duration of a complete + HPI write access. Since it is a write, the HR/W/ signal is driven low for the duration of the transfer. In S0-S1, the HBIL signal is + driven low to transfer the first byte, and in S2-S3 the HBIL signal is driven high to transfer the second byte. The timing here + conforms to the HPI8 Mode Timing Requirements in the 5416 datasheet.
+
+ Notice that the HRDY/ signal goes low after the second byte is transferred. The next HPI write does not start until the HRDY/ is + high again (indicating that the HPI is ready for the next write). S4 and S5 allow enough time for the HRDY/ signal to become high + again. Thus it was not necessary to check for HRDY/ in the GPIF waveform logic before starting the next HPI write sequence. + S5 is the decision point state that uses the GPIF transaction count expiration flag (RDY5) to determine whether or not the data + burst should continue.
+

 

 

FIFO Read from HPI: Close-up view
+

Here we see a close-up view of a read from the HPI using GPIF FIFO Read transactions. S0-S5 marks the duration of a complete + HPI read access. Since it is a read, the HR/W/ signal is driven high for the duration of the transfer. In S0-S1, the HBIL signal is + driven low to transfer the first byte, and in S2-S3 the HBIL signal is driven high to transfer the second byte. The timing here + conforms to the HPI8 Mode Timing Requirements in the 5416 datasheet.
+
+ Notice that the HRDY/ signal goes low after the second byte is transferred. The next HPI read does not start until the HRDY/ is + high again (indicating that the HPI is ready for the next read). S4 and S5 allow enough time for the HRDY/ signal to become high + again. Thus, it was not necessary to check for HRDY/ in the GPIF waveform logic before starting the next HPI read sequence. + S5 is the decision point state that uses the GPIF transaction count expiration flag (RDY5) to determine whether or not the data + burst should continue.
+

 

 

Downloading DSP code
 +
This is a snapshot of the activity that goes on when the FX2 downloads the DSP code to the 5416 DSK board.
+

 
 +

 

+
+ +

+Summary
 +

This design example of an FX2 GPIF interface to a TI 5416 DSP's HPI has given the user another concrete example of how the + FX2 GPIF can be used in a practical application. This DSP example builds upon the external FIFO example, and extends the + user's understanding of how to create GPIF waveform descriptors and program the GPIF to perform reads and writes over the + physical interface. Because the HPI protocol is significantly more complex than that of an external FIFO's, the user can appreciate + what it takes to create a full featured GPIF application, and apply the techniques presented here to solve applications that have + slave devices with more sophisticated protocols.
+

+
+

 

+
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+

Interfacing to a TI 5416 DSP via the Host Port Interface (HPI)
 +
+

+ Background on the TI 5416 DSP and Overview  +
+ +

+ The Texas Instruments TI 5416 fixed-point DSP finds its home in many mid range DSP applications. It is supported by the TI 5416 DSK, which proved very + attractive as the choice for this example because it exposes the HPI on one of the three expansion headers of the DSK board. The HPI allows a host processor + access to the internal RAM of the 5416, thereby enabling the transfer of data between the host processor and the 5416.
+
+ By interfacing the FX2 to the 5416's HPI, this allows developers of embedded audio and imaging applications to easily add a high + speed USB port. The FX2 can also bootload the 5416 DSP code via the HPI. In this example, users will be shown how to interface + the FX2 to the 5416 HPI using the GPIF to accomplish two things: 1) read and write to the internal RAM block of the 5416, and + 2) bootload the 5416 by downloading the DSP code from the PC. For detailed information about how the HPI block of the 5416 + works, please refer to the TI documentation mentioned in the references section at the end of this document. Note that the + information presented here may also be applicable to other TI DSPs that expose the HPI port.
+
+ +

+ Hardware + Connections +
+ +

+ This section discusses the definition of the GPIF interconnect which is shown below in Figure 13.
+ +

+ +
+
+ Figure 13. GPIF Interconnect to TI 5416 HPI
+
+ +
+
    +

    PA3, PA2 ----> HCNTL[1:0]
    Port + pins PA3 and PA2 are used to provide address lines to select + either the HPIC, HPIA, or HPID registers of the HPI. The FX2 + reads and writes data by accessing these registers.      +

    +
+
+
    +

    FD[7:0] <----> HD[7:0]
    The + lower portion of the GPIF data bus (FD[7:0]) is connected to + the HPI data bus (HD[7:0]). The FX2 uses this connection for + exchange of information between itself and the HPI. 

    +
+
+
    +

    CTL0 ----> HRNW
    CTL0 + is connected to the HRNW signal of the HPI. If HRNW is a 1, + this indicates a read access to the HPI. If HRNW is a 0, this + indicates a write access to the HPI. 

    +
+
+
    +

    CTL1 ----> HDS1
    CTL1 + is connected to the HDS1/ strobe of the HPI. The falling edge + of HDS1/ marks the beginning of the HPI access, and samples + the value of HRNW, HCNTL[1:0], and HBIL. The rising edge of + HDS1/ marks the end of the HPI access. 

    +
+
+
    +

    CTL2 ----> HBIL
    CTL2 + is connected to the HBIL signal of the HPI. A complete HPI access + consists of a two byte transfer. If HBIL is 0, this indicates + to the HPI that the first byte is being transferred. To indicate + to the HPI that the second byte is being transferred, HBIL must + be 1.

    +
+
+
    +

    RDY0 <---- HRDY
    RDY0 + is connected to the HRDY/ signal of the HPI. HRDY/ is low when + the HPI is completing the internal portion of a complete HPI + access. Another access to the HPI must not be performed until + the internal portion of the transfer is complete. This signal + is monitored by the GPIF.

    +
+
+
    +

    INT0 <---- HINT, INT2
    The + INT0/ interrupt signal on the FX2 is conected the HINT/ output + of the HPI. When the DSP is reset, the HINT/ will be asserted. + The DSP can also use this as a general purpose interrupt to + the FX2. The HINT/ signal is also tied to the 5416&rsquo;s + INT2/ pin to allow the FX2 to be able to bootload the DSP code.

    +
+
+
    +

    GND <----> GND
    Ground

    +
+
+
    +

    HCS, HPI_16
    HPI_16 + is tied to ground to make the HPI operate in 8-bit mode (HPI-8). + The HPI can operate in 16-bit mode (HPI-16) if the 5416&rsquo;s + external memory interface is not used (EMIF). For most DSP applications, + the EMIF will already be used for memory expansion. Using the + HPI in 8-bit mode also simplifies the GPIF interface. HCS/ is + tied to ground to allow continuous access to the HPI.

    +
+
+
    +

    HDS2, HAS, HPI_EN
    HPI_EN + is tied to VCC to enable the HPI port. HAS/ and HDS2/ are tied + to VCC since they are not necessary for this interface (attributed + in part to the flexibility of the GPIF interface).

    +
+
+ +

+The assignment of CTL and RDY lines was optimized for the FX2 56-pin package. The connection between the TI 5416 + DSK board and the FX2 development board was accomplished through the use of a ribbon cable set. The TI 5416 DSK board + exposes headers that require breakout panels (available from www.dspglobal.com) for prototyping purposes. The ribbon cables + connect between a breakout panel installed on the DSK board's P3 and the FX2 prototype board mounted onto the FX2 development + board. Figure 14 shows a snap of the actual hardware setup.
+

+

Figure 14. Shot of Actual Hardware Setup

 

+ +
+ Application-specific Data Flow
+ + +
+ +

+ Now that the GPIF interconnect has been presented, it's important to understand the overall data flow for this design example. + EP2OUT (4x buffered) is the source endpoint used for data writes to the HPI and EP6IN (4x buffered) is the sink endpoint used + for data reads from the HPI. EP0, the FX2's control endpoint, is used for writes to the HPIC and HPIA registers.
+
+ Before a data read or write can commence to and from a specific address in the DSP, the HPIA needs to be setup with the + appropriate source or destination address. The HPIC also needs to be setup to set the BOB bit to 1, which allows the first byte + of transfer to be the LSB and the second byte of the transfer to be the MSB (as organized in the DSP memory). Since the 5416 + supports an extended address scheme, the XPHIA bit in the HPIC register needs to be set if FX2 wants to access the upper + seven bits of the HPIA register. The XPHIA bit also needs to be set if proper auto-increment of the address is to occur when + consecutive data read and write accesses are made.
+
+ Figure 15 and Figure 16 show the data flow models for this example. GPIF single transactions are used to write out the data from EP0 to the + HPIC and HPIA registers. GPIF FIFO transactions are used for data reads and writes using EP6IN and EP2OUT in auto mode, respectively.
 +

    +
      +


      Figure 15. Data Flow Model in the OUT direction 

      +
    +
+ +
+
    +
      +


       
      Figure 16. Data Flow Model in the IN direction 

      + +
    +
+

 

+
+

 

+ +
+

 

+ +
+ + + diff --git a/doc/GPIF/GPIF Designer/dsp/app_note/mainmenu.htm b/doc/GPIF/GPIF Designer/dsp/app_note/mainmenu.htm new file mode 100644 index 0000000..a51e287 --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/app_note/mainmenu.htm @@ -0,0 +1,33 @@ + + + +Contents + + + +

Overview
+    Hardware Connections
   App-specific +Data Flow

GPIF +Transactions
    Waveform Descriptors
    Firmware
       FW +Files
        TD_Init() +function
       IFCONFIG +Register
       Writing +HPIC and HPIA
       Read +/ Write the HPI
       Handling +INT0
   Running the example
+       Step +1: Download FW
       Step +2: Write to the HPI
       Step +3: Read from HPI
       Step +4: Load DSP code
   Logic +Analyzer Traces
       Write +HPIC
       Write +HPIC: 1st Byte
       Write +HPIC: 2nd Byte
       FIFO +Write HPI
       FIFOWr HPI: +Close-up
       FIFORd HPI: +Close-up
       Download +DSP Code

+ + + diff --git a/doc/GPIF/GPIF Designer/dsp/datastruct.c.txt b/doc/GPIF/GPIF Designer/dsp/datastruct.c.txt new file mode 100644 index 0000000..bbf3b95 --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/datastruct.c.txt @@ -0,0 +1,30 @@ +const char xdata WaveData[128] = +{ +// Wave 0 +/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x38, 0x01, 0x07, +/* Opcode*/ 0x00, 0x00, 0x02, 0x00, 0x02, 0x01, 0x00, 0x00, +/* Output*/ 0xFB, 0xF9, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF, +/* LFun */ 0x00, 0x12, 0x12, 0x12, 0x00, 0x2D, 0x12, 0x3F, +// Wave 1 +/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x38, 0x01, 0x07, +/* Opcode*/ 0x00, 0x02, 0x04, 0x02, 0x04, 0x01, 0x00, 0x00, +/* Output*/ 0xFA, 0xF8, 0xFE, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, +/* LFun */ 0x00, 0x12, 0x12, 0x12, 0x00, 0x2D, 0x12, 0x3F, +// Wave 2 +/* LenBr */ 0x01, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Output*/ 0xFE, 0xFC, 0xFE, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, +/* LFun */ 0x00, 0x12, 0x12, 0x12, 0x00, 0x2D, 0x12, 0x3F, +// Wave 3 +/* LenBr */ 0x01, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Output*/ 0xFA, 0xF8, 0xFA, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, +/* LFun */ 0x00, 0x12, 0x12, 0x12, 0x00, 0x2D, 0x12, 0x3F +}; +// END DO NOT EDIT + +// DO NOT EDIT ... +const char xdata InitData[7] = +{ +/* Regs */ 0xC0,0x80,0x00,0xFF,0x06,0xE4,0x11 +}; diff --git a/doc/GPIF/GPIF Designer/dsp/dscr.a51 b/doc/GPIF/GPIF Designer/dsp/dscr.a51 new file mode 100644 index 0000000..db0e395 --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/dscr.a51 @@ -0,0 +1,265 @@ +;;----------------------------------------------------------------------------- +;; File: dscr.a51 +;; Contents: This file contains descriptor data tables. +;; +;; Copyright (c) 2002 Cypress Semiconductor, Inc. All rights reserved +;;----------------------------------------------------------------------------- + +DSCR_DEVICE equ 1 ;; Descriptor type: Device +DSCR_CONFIG equ 2 ;; Descriptor type: Configuration +DSCR_STRING equ 3 ;; Descriptor type: String +DSCR_INTRFC equ 4 ;; Descriptor type: Interface +DSCR_ENDPNT equ 5 ;; Descriptor type: Endpoint +DSCR_DEVQUAL equ 6 ;; Descriptor type: Device Qualifier + +DSCR_DEVICE_LEN equ 18 +DSCR_CONFIG_LEN equ 9 +DSCR_INTRFC_LEN equ 9 +DSCR_ENDPNT_LEN equ 7 +DSCR_DEVQUAL_LEN equ 10 + +ET_CONTROL equ 0 ;; Endpoint type: Control +ET_ISO equ 1 ;; Endpoint type: Isochronous +ET_BULK equ 2 ;; Endpoint type: Bulk +ET_INT equ 3 ;; Endpoint type: Interrupt + +public DeviceDscr, DeviceQualDscr, HighSpeedConfigDscr, FullSpeedConfigDscr, StringDscr, UserDscr + +DSCR SEGMENT CODE PAGE + +;;----------------------------------------------------------------------------- +;; Global Variables +;;----------------------------------------------------------------------------- + rseg DSCR ;; locate the descriptor table in on-part memory. + +DeviceDscr: + db DSCR_DEVICE_LEN ;; Descriptor length + db DSCR_DEVICE ;; Decriptor type + dw 0002H ;; Specification Version (BCD) + db 00H ;; Device class + db 00H ;; Device sub-class + db 00H ;; Device sub-sub-class + db 64 ;; Maximum packet size + dw 4705H ;; Vendor ID + dw 0210H ;; Product ID (Sample Device) + dw 0000H ;; Product version ID + db 1 ;; Manufacturer string index + db 2 ;; Product string index + db 0 ;; Serial number string index + db 1 ;; Number of configurations + +DeviceQualDscr: + db DSCR_DEVQUAL_LEN ;; Descriptor length + db DSCR_DEVQUAL ;; Decriptor type + dw 0002H ;; Specification Version (BCD) + db 00H ;; Device class + db 00H ;; Device sub-class + db 00H ;; Device sub-sub-class + db 64 ;; Maximum packet size + db 1 ;; Number of configurations + db 0 ;; Reserved + +HighSpeedConfigDscr: + db DSCR_CONFIG_LEN ;; Descriptor length + db DSCR_CONFIG ;; Descriptor type + db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) mod 256 ;; Total Length (LSB) + db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) / 256 ;; Total Length (MSB) + db 1 ;; Number of interfaces + db 1 ;; Configuration number + db 0 ;; Configuration string + db 10000000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu) + db 50 ;; Power requirement (div 2 ma) + +;; Interface Descriptor + db DSCR_INTRFC_LEN ;; Descriptor length + db DSCR_INTRFC ;; Descriptor type + db 0 ;; Zero-based index of this interface + db 0 ;; Alternate setting + db 4 ;; Number of end points + db 0ffH ;; Interface class + db 00H ;; Interface sub class + db 00H ;; Interface sub sub class + db 0 ;; Interface descriptor string index + +;; Endpoint Descriptor + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 01H ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 00H ;; Maximum packet size (LSB) + db 02H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + +;; Endpoint Descriptor + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 81H ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 00H ;; Maximum packet size (LSB) + db 02H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + +;; Endpoint Descriptor + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 02H ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 00H ;; Maximum packet size (LSB) + db 02H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + + +;; Endpoint Descriptor + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 86H ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 00H ;; Maximum packet size (LSB) + db 02H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + +HighSpeedConfigDscrEnd: + +FullSpeedConfigDscr: + db DSCR_CONFIG_LEN ;; Descriptor length + db DSCR_CONFIG ;; Descriptor type + db (FullSpeedConfigDscrEnd-FullSpeedConfigDscr) mod 256 ;; Total Length (LSB) + db (FullSpeedConfigDscrEnd-FullSpeedConfigDscr) / 256 ;; Total Length (MSB) + db 1 ;; Number of interfaces + db 1 ;; Configuration number + db 0 ;; Configuration string + db 10000000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu) + db 50 ;; Power requirement (div 2 ma) + +;; Interface Descriptor + db DSCR_INTRFC_LEN ;; Descriptor length + db DSCR_INTRFC ;; Descriptor type + db 0 ;; Zero-based index of this interface + db 0 ;; Alternate setting + db 4 ;; Number of end points + db 0ffH ;; Interface class + db 00H ;; Interface sub class + db 00H ;; Interface sub sub class + db 0 ;; Interface descriptor string index + +;; Endpoint Descriptor + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 01H ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 40H ;; Maximum packet size (LSB) + db 00H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + +;; Endpoint Descriptor + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 81H ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 40H ;; Maximum packet size (LSB) + db 00H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + +;; Endpoint Descriptor + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 02H ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 40H ;; Maximun packet size (LSB) + db 00H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + +;; Endpoint Descriptor + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 86H ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 40H ;; Maximum packet size (LSB) + db 00H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + +FullSpeedConfigDscrEnd: + +StringDscr: + +StringDscr0: + db StringDscr0End-StringDscr0 ;; String descriptor length + db DSCR_STRING + db 09H,04H +StringDscr0End: + +StringDscr1: + db StringDscr1End-StringDscr1 ;; String descriptor length + db DSCR_STRING + db 'C',00 + db 'y',00 + db 'p',00 + db 'r',00 + db 'e',00 + db 's',00 + db 's',00 +StringDscr1End: + +StringDscr2: + db StringDscr2End-StringDscr2 ;; Descriptor length + db DSCR_STRING + db 'E',00 + db 'Z',00 + db '-',00 + db 'U',00 + db 'S',00 + db 'B',00 + db ' ',00 + db 'F',00 + db 'X',00 + db '2',00 + db ' ',00 + db 'G',00 + db 'P',00 + db 'I',00 + db 'F',00 + db ' ',00 + db 't',00 + db 'o',00 + db ' ',00 + db 'T',00 + db 'I',00 + db ' ',00 + db '5',00 + db '4',00 + db '1',00 + db '6',00 + db ' ',00 + db 'H',00 + db 'P',00 + db 'I',00 + db ' ',00 + db 'u',00 + db 's',00 + db 'i',00 + db 'n',00 + db 'g',00 + db ' ',00 + db 'F',00 + db 'I',00 + db 'F',00 + db 'O',00 + db ' ',00 + db 'T',00 + db 'r',00 + db 'a',00 + db 'n',00 + db 's',00 + db 'a',00 + db 'c',00 + db 't',00 + db 'i',00 + db 'o',00 + db 'n',00 + db 's',00 +StringDscr2End: + +UserDscr: + dw 0000H + end + diff --git a/doc/GPIF/GPIF Designer/dsp/fw.c b/doc/GPIF/GPIF Designer/dsp/fw.c new file mode 100644 index 0000000..df5bd72 --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/fw.c @@ -0,0 +1,366 @@ +//----------------------------------------------------------------------------- +// File: fw.c +// Contents: Firmware frameworks task dispatcher and device request parser +// source. +// +// indent 3. NO TABS! +// +// $Revision: 17 $ +// $Date: 11/15/01 5:45p $ +// +// Copyright (c) 2002 Cypress Semiconductor, Inc. All rights reserved +//----------------------------------------------------------------------------- +#include "fx2.h" +#include "fx2regs.h" + +//----------------------------------------------------------------------------- +// Constants +//----------------------------------------------------------------------------- +#define DELAY_COUNT 0x9248*8L // Delay for 8 sec at 24Mhz, 4 sec at 48 +#define _IFREQ 48000 // IFCLK constant for Synchronization Delay +#define _CFREQ 48000 // CLKOUT constant for Synchronization Delay + +//----------------------------------------------------------------------------- +// Random Macros +//----------------------------------------------------------------------------- +#define min(a,b) (((a)<(b))?(a):(b)) +#define max(a,b) (((a)>(b))?(a):(b)) + + // Registers which require a synchronization delay, see section 15.14 + // FIFORESET FIFOPINPOLAR + // INPKTEND OUTPKTEND + // EPxBCH:L REVCTL + // GPIFTCB3 GPIFTCB2 + // GPIFTCB1 GPIFTCB0 + // EPxFIFOPFH:L EPxAUTOINLENH:L + // EPxFIFOCFG EPxGPIFFLGSEL + // PINFLAGSxx EPxFIFOIRQ + // EPxFIFOIE GPIFIRQ + // GPIFIE GPIFADRH:L + // UDMACRCH:L EPxGPIFTRIG + // GPIFTRIG + + // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well... + // ...these have been replaced by GPIFTC[B3:B0] registers + +#include "fx2sdly.h" // Define _IFREQ and _CFREQ above this #include + +//----------------------------------------------------------------------------- +// Global Variables +//----------------------------------------------------------------------------- +volatile BOOL GotSUD; +BOOL Rwuen; +BOOL Selfpwr; +volatile BOOL Sleep; // Sleep mode enable flag + +WORD pDeviceDscr; // Pointer to Device Descriptor; Descriptors may be moved +WORD pDeviceQualDscr; +WORD pHighSpeedConfigDscr; +WORD pFullSpeedConfigDscr; +WORD pConfigDscr; +WORD pOtherConfigDscr; +WORD pStringDscr; + +//----------------------------------------------------------------------------- +// Prototypes +//----------------------------------------------------------------------------- +void SetupCommand(void); +void TD_Init(void); +void TD_Poll(void); +BOOL TD_Suspend(void); +BOOL TD_Resume(void); + +BOOL DR_GetDescriptor(void); +BOOL DR_SetConfiguration(void); +BOOL DR_GetConfiguration(void); +BOOL DR_SetInterface(void); +BOOL DR_GetInterface(void); +BOOL DR_GetStatus(void); +BOOL DR_ClearFeature(void); +BOOL DR_SetFeature(void); +BOOL DR_VendorCmnd(void); + +// this table is used by the epcs macro +const char code EPCS_Offset_Lookup_Table[] = +{ + 0, // EP1OUT + 1, // EP1IN + 2, // EP2OUT + 2, // EP2IN + 3, // EP4OUT + 3, // EP4IN + 4, // EP6OUT + 4, // EP6IN + 5, // EP8OUT + 5, // EP8IN +}; + +// macro for generating the address of an endpoint's control and status register (EPnCS) +#define epcs(EP) (EPCS_Offset_Lookup_Table[(EP & 0x7E) | (EP > 128)] + 0xE6A1) + +//----------------------------------------------------------------------------- +// Code +//----------------------------------------------------------------------------- + +// Task dispatcher +void main(void) +{ + DWORD i; + WORD offset; + DWORD DevDescrLen; + DWORD j=0; + WORD IntDescrAddr; + WORD ExtDescrAddr; + + // Initialize Global States + Sleep = FALSE; // Disable sleep mode + Rwuen = FALSE; // Disable remote wakeup + Selfpwr = FALSE; // Disable self powered + GotSUD = FALSE; // Clear "Got setup data" flag + + // Initialize user device + TD_Init(); + + // The following section of code is used to relocate the descriptor table. + // Since the SUDPTRH and SUDPTRL are assigned the address of the descriptor + // table, the descriptor table must be located in on-part memory. + // The 4K demo tools locate all code sections in external memory. + // The descriptor table is relocated by the frameworks ONLY if it is found + // to be located in external memory. + pDeviceDscr = (WORD)&DeviceDscr; + pDeviceQualDscr = (WORD)&DeviceQualDscr; + pHighSpeedConfigDscr = (WORD)&HighSpeedConfigDscr; + pFullSpeedConfigDscr = (WORD)&FullSpeedConfigDscr; + pStringDscr = (WORD)&StringDscr; + + if (EZUSB_HIGHSPEED()) + { + pConfigDscr = pHighSpeedConfigDscr; + pOtherConfigDscr = pFullSpeedConfigDscr; + } + else + { + pConfigDscr = pFullSpeedConfigDscr; + pOtherConfigDscr = pHighSpeedConfigDscr; + } + + if ((WORD)&DeviceDscr & 0xe000) + { + IntDescrAddr = INTERNAL_DSCR_ADDR; + ExtDescrAddr = (WORD)&DeviceDscr; + DevDescrLen = (WORD)&UserDscr - (WORD)&DeviceDscr + 2; + for (i = 0; i < DevDescrLen; i++) + *((BYTE xdata *)IntDescrAddr+i) = 0xCD; + for (i = 0; i < DevDescrLen; i++) + *((BYTE xdata *)IntDescrAddr+i) = *((BYTE xdata *)ExtDescrAddr+i); + pDeviceDscr = IntDescrAddr; + offset = (WORD)&DeviceDscr - INTERNAL_DSCR_ADDR; + pDeviceQualDscr -= offset; + pConfigDscr -= offset; + pOtherConfigDscr -= offset; + pHighSpeedConfigDscr -= offset; + pFullSpeedConfigDscr -= offset; + pStringDscr -= offset; + } + + EZUSB_IRQ_ENABLE(); // Enable USB interrupt (INT2) + EZUSB_ENABLE_RSMIRQ(); // Wake-up interrupt + + INTSETUP |= (bmAV2EN | bmAV4EN); // Enable INT 2 & 4 autovectoring + + USBIE |= bmSUDAV | bmSUTOK | bmSUSP | bmURES | bmHSGRANT; // Enable selected interrupts + EA = 1; // Enable 8051 interrupts + +#ifndef NO_RENUM + // Renumerate if necessary. Do this by checking the renum bit. If it + // is already set, there is no need to renumerate. The renum bit will + // already be set if this firmware was loaded from an eeprom. + if(!(USBCS & bmRENUM)) + { + EZUSB_Discon(TRUE); // renumerate + } +#endif + + // unconditionally re-connect. If we loaded from eeprom we are + // disconnected and need to connect. If we just renumerated this + // is not necessary but doesn't hurt anything + USBCS &=~bmDISCON; + + CKCON = (CKCON&(~bmSTRETCH)) | FW_STRETCH_VALUE; // Set stretch to 0 (after renumeration) + + // clear the Sleep flag. + Sleep = FALSE; + + // Task Dispatcher + while(TRUE) // Main Loop + { + if(GotSUD) // Wait for SUDAV + { + SetupCommand(); // Implement setup command + GotSUD = FALSE; // Clear SUDAV flag + } + + // Poll User Device + // NOTE: Idle mode stops the processor clock. There are only two + // ways out of idle mode, the WAKEUP pin, and detection of the USB + // resume state on the USB bus. The timers will stop and the + // processor will not wake up on any other interrupts. + if (Sleep) + { + if(TD_Suspend()) + { + Sleep = FALSE; // Clear the "go to sleep" flag. Do it here to prevent any race condition between wakeup and the next sleep. + do + { + EZUSB_Susp(); // Place processor in idle mode. + } + while(!Rwuen && EZUSB_EXTWAKEUP()); + // Must continue to go back into suspend if the host has disabled remote wakeup + // *and* the wakeup was caused by the external wakeup pin. + + // 8051 activity will resume here due to USB bus or Wakeup# pin activity. + EZUSB_Resume(); // If source is the Wakeup# pin, signal the host to Resume. + TD_Resume(); + } + } + TD_Poll(); + } +} + +// Device request parser +void SetupCommand(void) +{ + void *dscr_ptr; + + switch(SETUPDAT[1]) + { + case SC_GET_DESCRIPTOR: // *** Get Descriptor + if(DR_GetDescriptor()) + switch(SETUPDAT[3]) + { + case GD_DEVICE: // Device + SUDPTRH = MSB(pDeviceDscr); + SUDPTRL = LSB(pDeviceDscr); + break; + case GD_DEVICE_QUALIFIER: // Device Qualifier + SUDPTRH = MSB(pDeviceQualDscr); + SUDPTRL = LSB(pDeviceQualDscr); + break; + case GD_CONFIGURATION: // Configuration + SUDPTRH = MSB(pConfigDscr); + SUDPTRL = LSB(pConfigDscr); + break; + case GD_OTHER_SPEED_CONFIGURATION: // Other Speed Configuration + SUDPTRH = MSB(pOtherConfigDscr); + SUDPTRL = LSB(pOtherConfigDscr); + break; + case GD_STRING: // String + if(dscr_ptr = (void *)EZUSB_GetStringDscr(SETUPDAT[2])) + { + SUDPTRH = MSB(dscr_ptr); + SUDPTRL = LSB(dscr_ptr); + } + else + EZUSB_STALL_EP0(); // Stall End Point 0 + break; + default: // Invalid request + EZUSB_STALL_EP0(); // Stall End Point 0 + } + break; + case SC_GET_INTERFACE: // *** Get Interface + DR_GetInterface(); + break; + case SC_SET_INTERFACE: // *** Set Interface + DR_SetInterface(); + break; + case SC_SET_CONFIGURATION: // *** Set Configuration + DR_SetConfiguration(); + break; + case SC_GET_CONFIGURATION: // *** Get Configuration + DR_GetConfiguration(); + break; + case SC_GET_STATUS: // *** Get Status + if(DR_GetStatus()) + switch(SETUPDAT[0]) + { + case GS_DEVICE: // Device + EP0BUF[0] = ((BYTE)Rwuen << 1) | (BYTE)Selfpwr; + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + break; + case GS_INTERFACE: // Interface + EP0BUF[0] = 0; + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + break; + case GS_ENDPOINT: // End Point + EP0BUF[0] = *(BYTE xdata *) epcs(SETUPDAT[4]) & bmEPSTALL; + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + break; + default: // Invalid Command + EZUSB_STALL_EP0(); // Stall End Point 0 + } + break; + case SC_CLEAR_FEATURE: // *** Clear Feature + if(DR_ClearFeature()) + switch(SETUPDAT[0]) + { + case FT_DEVICE: // Device + if(SETUPDAT[2] == 1) + Rwuen = FALSE; // Disable Remote Wakeup + else + EZUSB_STALL_EP0(); // Stall End Point 0 + break; + case FT_ENDPOINT: // End Point + if(SETUPDAT[2] == 0) + { + *(BYTE xdata *) epcs(SETUPDAT[4]) &= ~bmEPSTALL; + EZUSB_RESET_DATA_TOGGLE( SETUPDAT[4] ); + } + else + EZUSB_STALL_EP0(); // Stall End Point 0 + break; + } + break; + case SC_SET_FEATURE: // *** Set Feature + if(DR_SetFeature()) + switch(SETUPDAT[0]) + { + case FT_DEVICE: // Device + if(SETUPDAT[2] == 1) + Rwuen = TRUE; // Enable Remote Wakeup + else if(SETUPDAT[2] == 2) + // Set Feature Test Mode. The core handles this request. However, it is + // necessary for the firmware to complete the handshake phase of the + // control transfer before the chip will enter test mode. It is also + // necessary for FX2 to be physically disconnected (D+ and D-) + // from the host before it will enter test mode. + break; + else + EZUSB_STALL_EP0(); // Stall End Point 0 + break; + case FT_ENDPOINT: // End Point + *(BYTE xdata *) epcs(SETUPDAT[4]) |= bmEPSTALL; + break; + } + break; + default: // *** Invalid Command + if(DR_VendorCmnd()) + EZUSB_STALL_EP0(); // Stall End Point 0 + } + + // Acknowledge handshake phase of device request + EP0CS |= bmHSNAK; +} + +// Wake-up interrupt handler +void resume_isr(void) interrupt WKUP_VECT +{ + EZUSB_CLEAR_RSMIRQ(); +} + + diff --git a/doc/GPIF/GPIF Designer/dsp/gpif.c b/doc/GPIF/GPIF Designer/dsp/gpif.c new file mode 100644 index 0000000..eb7ee1d --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/gpif.c @@ -0,0 +1,292 @@ +// This program configures the General Programmable Interface (GPIF) for FX2. +// Please do not modify sections of text which are marked as "DO NOT EDIT ...". +// +// DO NOT EDIT ... +// GPIF Initialization +// Interface Timing Sync +// Internal Ready Init IntRdy=1 +// CTL Out Tristate-able Binary +// SingleWrite WF Select 1 +// SingleRead WF Select 0 +// FifoWrite WF Select 3 +// FifoRead WF Select 2 +// Data Bus Idle Drive Tristate +// END DO NOT EDIT + +// DO NOT EDIT ... +// GPIF Wave Names +// Wave 0 = SnglWr1 +// Wave 1 = SnglWr2 +// Wave 2 = FIFORd +// Wave 3 = FIFOWr + +// GPIF Ctrl Outputs Level +// CTL 0 = HR/W* CMOS +// CTL 1 = HDS1* CMOS +// CTL 2 = HBIL CMOS +// CTL 3 = CTL3 CMOS +// CTL 4 = CTL4 CMOS +// CTL 5 = CTL5 CMOS + +// GPIF Rdy Inputs +// RDY0 = HRDY* +// RDY1 = HDS1* +// RDY2 = HBIL +// RDY3 = RDY3 +// RDY4 = RDY4 +// RDY5 = TCXpire +// FIFOFlag = FIFOFlag +// IntReady = IntReady +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 0: SnglWr1 +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data Activate NO Data NO Data NO Data NO Data NO Data +// NextData SameData SameData NextData SameData SameData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1 +// Term A HRDY* +// LFunc AND +// Term B HRDY* +// Branch1 ThenIdle +// Branch0 ElseIdle +// Re-Exec No +// Sngl/CRC Default Default Default Default Default Default Default +// HR/W* 0 0 0 0 0 0 0 1 +// HDS1* 1 0 1 1 1 1 1 1 +// HBIL 0 0 0 0 0 0 0 1 +// CTL3 0 0 0 0 0 0 0 0 +// CTL4 0 0 0 0 0 0 0 0 +// CTL5 0 0 0 0 0 0 0 0 +// +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 1: SnglWr2 +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data Activate NO Data NO Data NO Data NO Data NO Data +// NextData SameData SameData NextData SameData SameData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1 +// Term A HRDY* +// LFunc AND +// Term B HRDY* +// Branch1 ThenIdle +// Branch0 ElseIdle +// Re-Exec No +// Sngl/CRC Default Default Default Default Default Default Default +// HR/W* 0 0 0 0 0 0 0 1 +// HDS1* 1 0 1 1 1 1 1 1 +// HBIL 1 1 1 1 1 1 1 1 +// CTL3 0 0 0 0 0 0 0 0 +// CTL4 0 0 0 0 0 0 0 0 +// CTL5 0 0 0 0 0 0 0 0 +// +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 2: FIFORd +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data NO Data Activate NO Data Activate NO Data NO Data +// NextData SameData SameData SameData SameData SameData NextData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 IF Wait 1 +// Term A TCXpire +// LFunc AND +// Term B TCXpire +// Branch1 ThenIdle +// Branch0 Else 0 +// Re-Exec No +// Sngl/CRC Default Default Default Default Default Default Default +// HR/W* 1 1 1 1 1 1 1 1 +// HDS1* 1 0 1 0 1 1 1 1 +// HBIL 0 0 1 1 1 1 1 1 +// CTL3 0 0 0 0 0 0 0 0 +// CTL4 0 0 0 0 0 0 0 0 +// CTL5 0 0 0 0 0 0 0 0 +// +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 3: FIFOWr +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data Activate NO Data Activate NO Data NO Data NO Data +// NextData SameData SameData NextData SameData NextData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 IF Wait 1 +// Term A TCXpire +// LFunc AND +// Term B TCXpire +// Branch1 ThenIdle +// Branch0 Else 0 +// Re-Exec No +// Sngl/CRC Default Default Default Default Default Default Default +// HR/W* 0 0 0 0 0 1 1 1 +// HDS1* 1 0 1 0 1 1 1 1 +// HBIL 0 0 1 1 1 1 1 1 +// CTL3 0 0 0 0 0 0 0 0 +// CTL4 0 0 0 0 0 0 0 0 +// CTL5 0 0 0 0 0 0 0 0 +// +// END DO NOT EDIT + +// GPIF Program Code + +// DO NOT EDIT ... +#include "fx2.h" +#include "fx2regs.h" +#include "fx2sdly.h" // SYNCDELAY macro +// END DO NOT EDIT + +// DO NOT EDIT ... +const char xdata WaveData[128] = +{ +// Wave 0 +/* LenBr */ 0x01, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Output*/ 0x02, 0x00, 0x02, 0x02, 0x02, 0x02, 0x02, 0x07, +/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, +// Wave 1 +/* LenBr */ 0x01, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Output*/ 0x06, 0x04, 0x06, 0x06, 0x06, 0x06, 0x06, 0x07, +/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, +// Wave 2 +/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x38, 0x01, 0x07, +/* Opcode*/ 0x00, 0x00, 0x02, 0x00, 0x02, 0x05, 0x00, 0x00, +/* Output*/ 0x03, 0x01, 0x07, 0x05, 0x07, 0x07, 0x07, 0x07, +/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x2D, 0x00, 0x3F, +// Wave 3 +/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x38, 0x01, 0x07, +/* Opcode*/ 0x00, 0x02, 0x04, 0x02, 0x04, 0x01, 0x00, 0x00, +/* Output*/ 0x02, 0x00, 0x06, 0x04, 0x06, 0x07, 0x07, 0x07, +/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x2D, 0x00, 0x3F, +}; +// END DO NOT EDIT + +// DO NOT EDIT ... +const char xdata FlowStates[36] = +{ +/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/* Wave 2 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/* Wave 3 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +}; +// END DO NOT EDIT + +// DO NOT EDIT ... +const char xdata InitData[7] = +{ +/* Regs */ 0xE0,0x00,0x00,0x07,0xCE,0x4E,0x00 +}; +// END DO NOT EDIT + +// TO DO: You may add additional code below. + +void GpifInit( void ) +{ + BYTE i; + + // Registers which require a synchronization delay, see section 15.14 + // FIFORESET FIFOPINPOLAR + // INPKTEND OUTPKTEND + // EPxBCH:L REVCTL + // GPIFTCB3 GPIFTCB2 + // GPIFTCB1 GPIFTCB0 + // EPxFIFOPFH:L EPxAUTOINLENH:L + // EPxFIFOCFG EPxGPIFFLGSEL + // PINFLAGSxx EPxFIFOIRQ + // EPxFIFOIE GPIFIRQ + // GPIFIE GPIFADRH:L + // UDMACRCH:L EPxGPIFTRIG + // GPIFTRIG + + // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well... + // ...these have been replaced by GPIFTC[B3:B0] registers + + // 8051 doesn't have access to waveform memories 'til + // the part is in GPIF mode. + + IFCONFIG = 0xCE; + // IFCLKSRC=1 , FIFOs executes on internal clk source + // xMHz=1 , 48MHz internal clk rate + // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz + // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk + // ASYNC=1 , master samples asynchronous + // GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF + // IFCFG[1:0]=10, FX2 in GPIF master mode + + GPIFABORT = 0xFF; // abort any waveforms pending + + GPIFREADYCFG = InitData[ 0 ]; + GPIFCTLCFG = InitData[ 1 ]; + GPIFIDLECS = InitData[ 2 ]; + GPIFIDLECTL = InitData[ 3 ]; + GPIFWFSELECT = InitData[ 5 ]; + GPIFREADYSTAT = InitData[ 6 ]; + + // use dual autopointer feature... + AUTOPTRSETUP = 0x07; // inc both pointers, + // ...warning: this introduces pdata hole(s) + // ...at E67B (XAUTODAT1) and E67C (XAUTODAT2) + + // source + AUTOPTRH1 = MSB( &WaveData ); + AUTOPTRL1 = LSB( &WaveData ); + + // destination + AUTOPTRH2 = 0xE4; + AUTOPTRL2 = 0x00; + + // transfer + for ( i = 0x00; i < 128; i++ ) + { + EXTAUTODAT2 = EXTAUTODAT1; + } + +// Configure GPIF Address pins, output initial value, + PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0] + OEC = 0xFF; // and as outputs + PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8] + OEE |= 0x80; // and as output + +// ...OR... tri-state GPIFADR[8:0] pins +// PORTCCFG = 0x00; // [7:0] as port I/O +// OEC = 0x00; // and as inputs +// PORTECFG &= 0x7F; // [8] as port I/O +// OEE &= 0x7F; // and as input + +// GPIF address pins update when GPIFADRH/L written + SYNCDELAY; // + GPIFADRH = 0x00; // bits[7:1] always 0 + SYNCDELAY; // + GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000 + +// Configure GPIF FlowStates registers for Wave 0 of WaveData + FLOWSTATE = FlowStates[ 0 ]; + FLOWLOGIC = FlowStates[ 1 ]; + FLOWEQ0CTL = FlowStates[ 2 ]; + FLOWEQ1CTL = FlowStates[ 3 ]; + FLOWHOLDOFF = FlowStates[ 4 ]; + FLOWSTB = FlowStates[ 5 ]; + FLOWSTBEDGE = FlowStates[ 6 ]; + FLOWSTBHPERIOD = FlowStates[ 7 ]; +} + diff --git a/doc/GPIF/GPIF Designer/dsp/int0.c b/doc/GPIF/GPIF Designer/dsp/int0.c new file mode 100644 index 0000000..9ad6d63 --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/int0.c @@ -0,0 +1,10 @@ +#include "fx2.h" +#include "fx2regs.h" + +extern BOOL hpi_int; + +void int0_isr (void) interrupt 0 +{ + hpi_int = TRUE; // HPI interrupted the FX2 + EX0 = 0; // disable INT0/ interrupt, let foreground re-enable it +} \ No newline at end of file diff --git a/doc/GPIF/GPIF Designer/dsp/readme.txt b/doc/GPIF/GPIF Designer/dsp/readme.txt new file mode 100644 index 0000000..93136e5 --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/readme.txt @@ -0,0 +1,6 @@ +readme.txt for FX2_to_TI5416 GPIF FIFO Transactions Auto mode +------------------------------------------------------------- + +see GPIF Primer section on design examples for operating instructions +and details + diff --git a/doc/GPIF/GPIF Designer/dsp/tmp.c b/doc/GPIF/GPIF Designer/dsp/tmp.c new file mode 100644 index 0000000..989792f --- /dev/null +++ b/doc/GPIF/GPIF Designer/dsp/tmp.c @@ -0,0 +1,292 @@ +// This program configures the General Programmable Interface (GPIF) for FX2. +// Please do not modify sections of text which are marked as "DO NOT EDIT ...". +// +// DO NOT EDIT ... +// GPIF Initialization +// Interface Timing Async +// Internal Ready Init IntRdy=1 +// CTL Out Tristate-able Tristate +// SingleWrite WF Select 3 +// SingleRead WF Select 2 +// FifoWrite WF Select 1 +// FifoRead WF Select 0 +// Data Bus Idle Drive Tristate +// END DO NOT EDIT + +// DO NOT EDIT ... +// GPIF Wave Names +// Wave 0 = FIFORd +// Wave 1 = FIFOWr +// Wave 2 = SnglWr2 +// Wave 3 = SnglWr1 + +// GPIF Ctrl Outputs Level +// CTL 0 = HR/W* CMOS +// CTL 1 = HDS1* CMOS +// CTL 2 = HBIL CMOS +// CTL 3 = unused CMOS +// CTL 4 = unused CMOS +// CTL 5 = unused CMOS + +// GPIF Rdy Inputs +// RDY0 = HRDY* +// RDY1 = unused +// RDY2 = unused +// RDY3 = unused +// RDY4 = unused +// RDY5 = TCXpire +// FIFOFlag = FIFOFlag +// IntReady = IntReady +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 0: FIFORd +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data NO Data Activate NO Data Activate NO Data NO Data +// NextData SameData SameData SameData SameData SameData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 IF Wait 3 +// Term A TCXpire +// LFunc AND +// Term B TCXpire +// Branch1 ThenIdle +// Branch0 Else 0 +// Re-Exec No +// Sngl/CRC Default Default Default Default Default Default Default +// HR/W* 1 1 1 1 1 1 1 1 +// HDS1* 1 0 1 0 0 0 1 1 +// HBIL 0 0 1 1 1 1 1 1 +// unused 1 1 1 1 1 1 1 1 +// unused +// unused +// +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 1: FIFOWr +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data Activate NO Data Activate NO Data NO Data NO Data +// NextData SameData SameData NextData SameData SameData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 IF Wait 1 +// Term A TCXpire +// LFunc AND +// Term B TCXpire +// Branch1 ThenIdle +// Branch0 Else 0 +// Re-Exec No +// Sngl/CRC Default Default Default Default Default Default Default +// HR/W* 0 0 0 0 0 1 1 1 +// HDS1* 1 0 1 0 1 1 1 1 +// HBIL 0 0 1 1 1 1 1 1 +// unused 1 1 1 1 1 1 1 1 +// unused +// unused +// +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 2: SnglWr2 +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data Activate NO Data NO Data NO Data NO Data NO Data +// NextData SameData SameData SameData SameData SameData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1 +// Term A unused +// LFunc AND +// Term B unused +// Branch1 ThenIdle +// Branch0 ElseIdle +// Re-Exec No +// Sngl/CRC Default Default Default Default Default Default Default +// HR/W* 0 0 0 0 0 0 0 1 +// HDS1* 1 0 1 0 1 1 1 1 +// HBIL 1 1 1 1 1 1 1 1 +// unused 1 1 1 1 1 1 1 1 +// unused +// unused +// +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 3: SnglWr1 +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data Activate NO Data NO Data NO Data NO Data NO Data +// NextData SameData SameData SameData SameData SameData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1 +// Term A unused +// LFunc AND +// Term B unused +// Branch1 ThenIdle +// Branch0 ElseIdle +// Re-Exec No +// Sngl/CRC Default Default Default Default Default Default Default +// HR/W* 0 0 0 0 0 0 0 1 +// HDS1* 1 0 1 0 1 1 1 1 +// HBIL 0 0 0 1 1 1 1 1 +// unused 1 1 1 1 1 1 1 1 +// unused +// unused +// +// END DO NOT EDIT + +// GPIF Program Code + +// DO NOT EDIT ... +#include "fx2.h" +#include "fx2regs.h" +#include "fx2sdly.h" // SYNCDELAY macro +// END DO NOT EDIT + +// DO NOT EDIT ... +const char xdata WaveData[128] = +{ +// Wave 0 +/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x38, 0x03, 0x07, +/* Opcode*/ 0x00, 0x00, 0x02, 0x00, 0x02, 0x01, 0x00, 0x00, +/* Output*/ 0xFB, 0xF9, 0xFF, 0xFD, 0xFD, 0xFD, 0xFF, 0xFF, +/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x2D, 0x00, 0x3F, +// Wave 1 +/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x38, 0x01, 0x07, +/* Opcode*/ 0x00, 0x02, 0x04, 0x02, 0x00, 0x01, 0x00, 0x00, +/* Output*/ 0xFA, 0xF8, 0xFE, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF, +/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x2D, 0x00, 0x3F, +// Wave 2 +/* LenBr */ 0x01, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Output*/ 0xFE, 0xFC, 0xFE, 0xFC, 0xFE, 0xFE, 0xFE, 0xFF, +/* LFun */ 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x3F, +// Wave 3 +/* LenBr */ 0x01, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Output*/ 0xFA, 0xF8, 0xFA, 0xFC, 0xFE, 0xFE, 0xFE, 0xFF, +/* LFun */ 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x3F, +}; +// END DO NOT EDIT + +// DO NOT EDIT ... +const char xdata FlowStates[36] = +{ +/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/* Wave 2 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/* Wave 3 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +}; +// END DO NOT EDIT + +// DO NOT EDIT ... +const char xdata InitData[7] = +{ +/* Regs */ 0xA0,0x80,0x00,0xFF,0xEA,0xE4,0x00 +}; +// END DO NOT EDIT + +// TO DO: You may add additional code below. + +void GpifInit( void ) +{ + BYTE i; + + // Registers which require a synchronization delay, see section 15.14 + // FIFORESET FIFOPINPOLAR + // INPKTEND OUTPKTEND + // EPxBCH:L REVCTL + // GPIFTCB3 GPIFTCB2 + // GPIFTCB1 GPIFTCB0 + // EPxFIFOPFH:L EPxAUTOINLENH:L + // EPxFIFOCFG EPxGPIFFLGSEL + // PINFLAGSxx EPxFIFOIRQ + // EPxFIFOIE GPIFIRQ + // GPIFIE GPIFADRH:L + // UDMACRCH:L EPxGPIFTRIG + // GPIFTRIG + + // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well... + // ...these have been replaced by GPIFTC[B3:B0] registers + + // 8051 doesn't have access to waveform memories 'til + // the part is in GPIF mode. + + IFCONFIG = 0xEA; + // IFCLKSRC=1 , FIFOs executes on internal clk source + // xMHz=1 , 48MHz internal clk rate + // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz + // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk + // ASYNC=1 , master samples asynchronous + // GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF + // IFCFG[1:0]=10, FX2 in GPIF master mode + + GPIFABORT = 0xFF; // abort any waveforms pending + + GPIFREADYCFG = InitData[ 0 ]; + GPIFCTLCFG = InitData[ 1 ]; + GPIFIDLECS = InitData[ 2 ]; + GPIFIDLECTL = InitData[ 3 ]; + GPIFWFSELECT = InitData[ 5 ]; + GPIFREADYSTAT = InitData[ 6 ]; + + // use dual autopointer feature... + AUTOPTRSETUP = 0x07; // inc both pointers, + // ...warning: this introduces pdata hole(s) + // ...at E67B (XAUTODAT1) and E67C (XAUTODAT2) + + // source + AUTOPT1RH = MSB( &WaveData ); + AUTOPT1RL = LSB( &WaveData ); + + // destination + AUTOPTRH2 = 0xE4; + AUTOPTRL2 = 0x00; + + // transfer + for ( i = 0x00; i < 128; i++ ) + { + EXTAUTODAT2 = EXTAUTODAT1; + } + +// Configure GPIF Address pins, output initial value, + PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0] + OEC = 0xFF; // and as outputs + PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8] + OEE |= 0x80; // and as output + +// ...OR... tri-state GPIFADR[8:0] pins +// PORTCCFG = 0x00; // [7:0] as port I/O +// OEC = 0x00; // and as inputs +// PORTECFG &= 0x7F; // [8] as port I/O +// OEE &= 0x7F; // and as input + +// GPIF address pins update when GPIFADRH/L written + SYNCDELAY; // + GPIFADRH = 0x00; // bits[7:1] always 0 + SYNCDELAY; // + GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000 + +// Configure GPIF FlowStates registers for Wave 0 of WaveData + FLOWSTATE = FlowStates[ 0 ]; + FLOWLOGIC = FlowStates[ 1 ]; + FLOWEQ0CTL = FlowStates[ 2 ]; + FLOWEQ1CTL = FlowStates[ 3 ]; + FLOWHOLDOFF = FlowStates[ 4 ]; + FLOWSTB = FlowStates[ 5 ]; + FLOWSTBEDGE = FlowStates[ 6 ]; + FLOWSTBHPERIOD = FlowStates[ 7 ]; +} + diff --git a/doc/GPIF/GPIF Designer/fifo/FX2_to_extsyncFIFO.Opt b/doc/GPIF/GPIF Designer/fifo/FX2_to_extsyncFIFO.Opt new file mode 100644 index 0000000..382b896 --- /dev/null +++ b/doc/GPIF/GPIF Designer/fifo/FX2_to_extsyncFIFO.Opt @@ -0,0 +1,40 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + + cExt (*.c) + aExt (*.a*; *.src) + oExt (*.obj) + lExt (*.lib) + tExt (*.txt) + pExt (*.plm) + CppX (*.cpp) + DaveTm { 0,0,0,0,0,0,0,0 } + +Target (Target 1), 0x0000 // Tools: 'MCS-51' +GRPOPT 1,(Source Group 1),1,0,0 + +OPTFFF 1,1,1,385875968,0,339,339,0,<.\fw.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,66,0,0,0,66,0,0,0,61,3,0,0,118,1,0,0 } +OPTFFF 1,2,2,385875968,0,1,5,0,<.\dscr.a51> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,44,0,0,0,44,0,0,0,70,3,0,0,224,1,0,0 } +OPTFFF 1,3,1,553648128,0,42,42,0,<.\FX2_to_extsyncFIFO.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,0,0,0,0,0,0,0,0,22,3,0,0,176,1,0,0 } +OPTFFF 1,4,4,0,0,0,0,0, +OPTFFF 1,5,3,0,0,0,0,0, +OPTFFF 1,6,1,33554434,0,175,175,0,<.\gpif.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,66,0,0,0,66,0,0,0,61,3,0,0,118,1,0,0 } + + +TARGOPT 1, (Target 1) + CLK51=48000000 + OPTTT 1,1,1,0 + OPTHX 0,65535,0,0,0 + OPTLX 120,65,8,<.\> + OPTOX 16 + OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 + OPTXL 1,1,1,1,1,1,1,0,0 + OPTFL 1,0,1 + OPTDL (S8051.DLL)()(DP51.DLL)(-pFX2)(S8051.DLL)()(TP51.DLL)(-pFX2) + OPTDBG 49150,0,()()()()()()()()()() ()()()() + OPTKEY 0,(MON51)(-S1 -B38400 -O31) + OPTDF 0x0 + OPTLE <> + OPTLC <> +EndOpt + diff --git a/doc/GPIF/GPIF Designer/fifo/FX2_to_extsyncFIFO.Uv2 b/doc/GPIF/GPIF Designer/fifo/FX2_to_extsyncFIFO.Uv2 new file mode 100644 index 0000000..c8c105e --- /dev/null +++ b/doc/GPIF/GPIF Designer/fifo/FX2_to_extsyncFIFO.Uv2 @@ -0,0 +1,108 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (Target 1), 0x0000 // Tools: 'MCS-51' + +Group (Source Group 1) + +File 1,1,<.\fw.c> +File 1,2,<.\dscr.a51> +File 1,1,<.\FX2_to_extsyncFIFO.c> +File 1,4, +File 1,3, +File 1,1,<.\gpif.c> + + +Options 1,0,0 // Target 'Target 1' + Device (EZ-USB FX2 (CY7C68XXX)) + Vendor (Cypress Semiconductor) + Cpu (IRAM(0 - 0xFF) XRAM(0 - 0x3FF) CLOCK(48000000) MODDP2) + Rgf (REG52.H) + Mem () + C () + A () + RL () + OH () + UseEnv=1 + EnvBin (C:\Keil\C51\BIN\) + EnvInc (c:\CYPRESS\USB\Target\Inc\;C:\Keil\C51\INC\) + EnvLib (C:\Keil\C51\LIB\) + EnvReg () + OrgReg () + TgStat=0 + OutDir (.\) + OutName (FX2_to_extsyncFIFO) + GenApp=1 + GenLib=0 + GenHex=1 + Debug=1 + Browse=0 + LstDir (.\) + HexSel=0 + MG32K=0 + RunUsr 0 1 + RunUsr 1 0 <> + SVCSID <> + MODEL5=0 + RTOS5=0 + ROMSZ5=2 + DHOLD5=0 + XHOLD5=0 + T51FL=304 + CBANKS5=0 + XBANKS5=0 + RCB51 { 0,0,0,0,0,255,255,0,0 } + RXB51 { 0,0,0,0,0,0,0,0,0 } + OCM51 { 0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCR51 { 0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IRO51 { 0,0,0,0,0,0,0,0,0 } + IRA51 { 0,0,0,0,0,0,1,0,0 } + XRA51 { 0,0,0,0,0,0,4,0,0 } + C51FL=21630224 + C51VA=0 + C51MSC () + C51DEF () + C51UDF () + INCC5 () + AX51FL=4 + AX51MSC () + AX51SET () + AX51RST () + INCA5 () + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + BankNo=65535 + LX51FL=288 + LX51OVL () + LX51MSC () + LX51DWN () + LX51LFI () + LX51ASN () + LX51RES () + LX51CCL () + LX51UCL () + LX51CSC () + LX51UCS () + LX51COB (0x0080-0x0FFF) + LX51XDB (0x1000) + LX51PDB () + LX51BIB () + LX51DAB () + LX51IDB () + LX51PRC () + LX51STK () + LX51COS () + LX51XDS () + LX51BIS () + LX51DAS () + LX51IDS () + OPTDL (S8051.DLL)()(DP51.DLL)(-pFX2)(S8051.DLL)()(TP51.DLL)(-pFX2) + OPTDBG 49150,0,()()()()()()()()()() ()()()() +EndOpt + diff --git a/doc/GPIF/GPIF Designer/fifo/FX2_to_extsyncFIFO.c b/doc/GPIF/GPIF Designer/fifo/FX2_to_extsyncFIFO.c new file mode 100644 index 0000000..8d32fcf --- /dev/null +++ b/doc/GPIF/GPIF Designer/fifo/FX2_to_extsyncFIFO.c @@ -0,0 +1,528 @@ +#pragma NOIV // Do not generate interrupt vectors +//----------------------------------------------------------------------------- +// File: FX2_to_extsyncFIFO.c +// Contents: Hooks required to implement FX2 GPIF to external sync. FIFO +// interface using CY4265-15AC +// +// Copyright (c) 2003 Cypress Semiconductor, Inc. All rights reserved +//----------------------------------------------------------------------------- +#include "fx2.h" +#include "fx2regs.h" +#include "fx2sdly.h" // SYNCDELAY macro, see Section 15.14 of FX2 Tech. + // Ref. Manual for usage details. + +#define EXTFIFONOTFULL GPIFREADYSTAT & bmBIT1 +#define EXTFIFONOTEMPTY GPIFREADYSTAT & bmBIT0 + +#define GPIFTRIGRD 4 + +#define GPIF_EP2 0 +#define GPIF_EP4 1 +#define GPIF_EP6 2 +#define GPIF_EP8 3 + +extern BOOL GotSUD; // Received setup data flag +extern BOOL Sleep; +extern BOOL Rwuen; +extern BOOL Selfpwr; + +BYTE Configuration; // Current configuration +BYTE AlternateSetting; // Alternate settings +BOOL in_enable = FALSE; // flag to enable IN transfers +BOOL enum_high_speed = FALSE; // flag to let firmware know FX2 enumerated at high speed +extern const char xdata FlowStates[36]; + +//----------------------------------------------------------------------------- +// Task Dispatcher hooks +// The following hooks are called by the task dispatcher. +//----------------------------------------------------------------------------- +void Setup_FLOWSTATE_Write ( void ); +void Setup_FLOWSTATE_Read ( void ); +void GpifInit (); + +void TD_Init(void) // Called once at startup +{ + // set the CPU clock to 48MHz + CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1); + SYNCDELAY; + + EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered + SYNCDELAY; + EP4CFG = 0x00; // EP4 not valid + SYNCDELAY; + EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered + SYNCDELAY; + EP8CFG = 0x00; // EP8 not valid + SYNCDELAY; + + + FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host + SYNCDELAY; + FIFORESET = 0x02; // reset EP2 FIFO + SYNCDELAY; + FIFORESET = 0x06; // reset EP6 FIFO + SYNCDELAY; + FIFORESET = 0x00; // clear NAKALL bit to resume normal operation + SYNCDELAY; + + EP2FIFOCFG = 0x01; // allow core to see zero to one transition of auto out bit + SYNCDELAY; + EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word ops + SYNCDELAY; + EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops + SYNCDELAY; + + GpifInit (); // initialize GPIF registers + + SYNCDELAY; + EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses EF flag + SYNCDELAY; + EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses FF flag + SYNCDELAY; + + // global flowstate register initializations + + FLOWLOGIC = FlowStates[19]; // 0011 0110b - LFUNC[1:0] = 00 (A AND B), TERMA/B[2:0]=110 (FIFO Flag) + SYNCDELAY; + FLOWSTB = FlowStates[22]; // 0000 0100b - MSTB[2:0] = 100 (CTL4), not used as strobe + SYNCDELAY; + GPIFHOLDAMOUNT = FlowStates[26]; // hold data for one half clock (10ns) assuming 48MHz IFCLK + SYNCDELAY; + FLOWSTBEDGE = FlowStates[24]; // move data on both edges of clock + SYNCDELAY; + FLOWSTBHPERIOD = FlowStates[25]; // 20.83ns half period + SYNCDELAY; + + // reset the external FIFO + + OEA |= 0x04; // turn on PA2 as output pin + IOA |= 0x04; // pull PA2 high initially + IOA &= 0xFB; // bring PA2 low + EZUSB_Delay (1); // keep PA2 low for ~1ms, more than enough time + IOA |= 0x04; // bring PA2 high +} + +void TD_Poll(void) +{ + if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE + { + if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there's a packet in the peripheral domain for EP2 + { + if ( EXTFIFONOTFULL ) // if the external FIFO is not full + { + if(enum_high_speed) + { + SYNCDELAY; + GPIFTCB1 = 0x01; // setup transaction count (512 bytes/2 for word wide -> 0x0100) + SYNCDELAY; + GPIFTCB0 = 0x00; + SYNCDELAY; + } + else + { + SYNCDELAY; + GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20) + SYNCDELAY; + GPIFTCB0 = 0x20; + SYNCDELAY; + } + Setup_FLOWSTATE_Write(); // setup FLOWSTATE registers for FIFO Write operation + SYNCDELAY; + GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO + SYNCDELAY; + + while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit + { + ; + } + SYNCDELAY; + } + } + } + + if(in_enable) // if IN transfers are enabled + { + if ( GPIFTRIG & 0x80 ) // if GPIF interface IDLE + { + if ( EXTFIFONOTEMPTY ) // if external FIFO is not empty + { + if ( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full + { + if(enum_high_speed) + { + SYNCDELAY; + GPIFTCB1 = 0x01; // setup transaction count (512 bytes/2 for word wide -> 0x0100) + SYNCDELAY; + GPIFTCB0 = 0x00; + SYNCDELAY; + } + else + { + SYNCDELAY; + GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20) + SYNCDELAY; + GPIFTCB0 = 0x20; + SYNCDELAY; + } + + Setup_FLOWSTATE_Read(); // setup FLOWSTATE registers for FIFO Read operation + SYNCDELAY; + GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO + SYNCDELAY; + + while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit + { + ; + } + + SYNCDELAY; + } + } + } + } + +} + +BOOL TD_Suspend(void) // Called before the device goes into suspend mode +{ + return(TRUE); +} + +BOOL TD_Resume(void) // Called after the device resumes +{ + return(TRUE); +} + +//----------------------------------------------------------------------------- +// Device Request hooks +// The following hooks are called by the end point 0 device request parser. +//----------------------------------------------------------------------------- + +BOOL DR_GetDescriptor(void) +{ + return(TRUE); +} + +BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received +{ + if( EZUSB_HIGHSPEED( ) ) + { // FX2 enumerated at high speed + SYNCDELAY; // + EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes + SYNCDELAY; // + EP6AUTOINLENL = 0x00; + SYNCDELAY; + enum_high_speed = TRUE; + } + else + { // FX2 enumerated at full speed + SYNCDELAY; + EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes + SYNCDELAY; + EP6AUTOINLENL = 0x40; + SYNCDELAY; + enum_high_speed = FALSE; + } + + Configuration = SETUPDAT[2]; + return(TRUE); // Handled by user code +} + +BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received +{ + EP0BUF[0] = Configuration; + EP0BCH = 0; + EP0BCL = 1; + return(TRUE); // Handled by user code +} + +BOOL DR_SetInterface(void) // Called when a Set Interface command is received +{ + AlternateSetting = SETUPDAT[2]; + return(TRUE); // Handled by user code +} + +BOOL DR_GetInterface(void) // Called when a Set Interface command is received +{ + EP0BUF[0] = AlternateSetting; + EP0BCH = 0; + EP0BCL = 1; + return(TRUE); // Handled by user code +} + +BOOL DR_GetStatus(void) +{ + return(TRUE); +} + +BOOL DR_ClearFeature(void) +{ + return(TRUE); +} + +BOOL DR_SetFeature(void) +{ + return(TRUE); +} + +#define VX_B2 0xB2 // reset the external FIFO +#define VX_B3 0xB3 // enable IN transfers +#define VX_B4 0xB4 // disable IN transfers +#define VX_B5 0xB5 // read GPIFREADYSTAT register +#define VX_B6 0xB6 // read GPIFTRIG register + +BOOL DR_VendorCmnd(void) +{ + switch (SETUPDAT[1]) + { + case VX_B2: + { + // reset the external FIFO + + OEA |= 0x04; // turn on PA2 as output pin + IOA |= 0x04; // pull PA2 high initially + IOA &= 0xFB; // bring PA2 low + EZUSB_Delay (1); // keep PA2 low for ~1ms, more than enough time + IOA |= 0x04; // bring PA2 high + + *EP0BUF = VX_B2; + EP0BCH = 0; + EP0BCL = 1; // Arm endpoint with # bytes to transfer + EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request + break; + } + case VX_B3: // enable IN transfers + { + in_enable = TRUE; + + *EP0BUF = VX_B3; + EP0BCH = 0; + EP0BCL = 1; + EP0CS |= bmHSNAK; + break; + } + case VX_B4: // disable IN transfers + { + in_enable = FALSE; + + *EP0BUF = VX_B4; + EP0BCH = 0; + EP0BCL = 1; + EP0CS |= bmHSNAK; + break; + } + case VX_B5: // read GPIFREADYSTAT register + { + EP0BUF[0] = VX_B5; + SYNCDELAY; + EP0BUF[1] = GPIFREADYSTAT; + SYNCDELAY; + EP0BCH = 0; + EP0BCL = 2; + EP0CS |= bmHSNAK; + break; + } + case VX_B6: // read GPIFTRIG register + { + EP0BUF[0] = VX_B6; + SYNCDELAY; + EP0BUF[1] = GPIFTRIG; + SYNCDELAY; + EP0BCH = 0; + EP0BCL = 2; + EP0CS |= bmHSNAK; + break; + } + default: + return(TRUE); + } + + return(FALSE); +} + +//----------------------------------------------------------------------------- +// USB Interrupt Handlers +// The following functions are called by the USB interrupt jump table. +//----------------------------------------------------------------------------- + +// Setup Data Available Interrupt Handler +void ISR_Sudav(void) interrupt 0 +{ + GotSUD = TRUE; // Set flag + EZUSB_IRQ_CLEAR(); + USBIRQ = bmSUDAV; // Clear SUDAV IRQ +} + +// Setup Token Interrupt Handler +void ISR_Sutok(void) interrupt 0 +{ + EZUSB_IRQ_CLEAR(); + USBIRQ = bmSUTOK; // Clear SUTOK IRQ +} + +void ISR_Sof(void) interrupt 0 +{ + EZUSB_IRQ_CLEAR(); + USBIRQ = bmSOF; // Clear SOF IRQ +} + +void ISR_Ures(void) interrupt 0 +{ + // whenever we get a USB reset, we should revert to full speed mode + pConfigDscr = pFullSpeedConfigDscr; + ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR; + pOtherConfigDscr = pHighSpeedConfigDscr; + ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR; + + EZUSB_IRQ_CLEAR(); + USBIRQ = bmURES; // Clear URES IRQ +} + +void ISR_Susp(void) interrupt 0 +{ + Sleep = TRUE; + EZUSB_IRQ_CLEAR(); + USBIRQ = bmSUSP; +} + +void ISR_Highspeed(void) interrupt 0 +{ + if (EZUSB_HIGHSPEED()) + { + pConfigDscr = pHighSpeedConfigDscr; + ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR; + pOtherConfigDscr = pFullSpeedConfigDscr; + ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR; + } + + EZUSB_IRQ_CLEAR(); + USBIRQ = bmHSGRANT; +} +void ISR_Ep0ack(void) interrupt 0 +{ +} +void ISR_Stub(void) interrupt 0 +{ +} +void ISR_Ep0in(void) interrupt 0 +{ +} +void ISR_Ep0out(void) interrupt 0 +{ +} +void ISR_Ep1in(void) interrupt 0 +{ +} +void ISR_Ep1out(void) interrupt 0 +{ +} +void ISR_Ep2inout(void) interrupt 0 +{ +} +void ISR_Ep4inout(void) interrupt 0 +{ +} +void ISR_Ep6inout(void) interrupt 0 +{ +} +void ISR_Ep8inout(void) interrupt 0 +{ +} +void ISR_Ibn(void) interrupt 0 +{ +} +void ISR_Ep0pingnak(void) interrupt 0 +{ +} +void ISR_Ep1pingnak(void) interrupt 0 +{ +} +void ISR_Ep2pingnak(void) interrupt 0 +{ +} +void ISR_Ep4pingnak(void) interrupt 0 +{ +} +void ISR_Ep6pingnak(void) interrupt 0 +{ +} +void ISR_Ep8pingnak(void) interrupt 0 +{ +} +void ISR_Errorlimit(void) interrupt 0 +{ +} +void ISR_Ep2piderror(void) interrupt 0 +{ +} +void ISR_Ep4piderror(void) interrupt 0 +{ +} +void ISR_Ep6piderror(void) interrupt 0 +{ +} +void ISR_Ep8piderror(void) interrupt 0 +{ +} +void ISR_Ep2pflag(void) interrupt 0 +{ +} +void ISR_Ep4pflag(void) interrupt 0 +{ +} +void ISR_Ep6pflag(void) interrupt 0 +{ +} +void ISR_Ep8pflag(void) interrupt 0 +{ +} +void ISR_Ep2eflag(void) interrupt 0 +{ +} +void ISR_Ep4eflag(void) interrupt 0 +{ +} +void ISR_Ep6eflag(void) interrupt 0 +{ +} +void ISR_Ep8eflag(void) interrupt 0 +{ +} +void ISR_Ep2fflag(void) interrupt 0 +{ +} +void ISR_Ep4fflag(void) interrupt 0 +{ +} +void ISR_Ep6fflag(void) interrupt 0 +{ +} +void ISR_Ep8fflag(void) interrupt 0 +{ +} +void ISR_GpifComplete(void) interrupt 0 +{ +} +void ISR_GpifWaveform(void) interrupt 0 +{ +} + +void Setup_FLOWSTATE_Read ( void ) +{ + FLOWSTATE = FlowStates[18]; // 1000 0011b - FSE=1, FS[2:0]=003 + SYNCDELAY; + FLOWEQ0CTL = FlowStates[20]; // CTL1/CTL2 = 0 when flow condition equals zero (data flows) + SYNCDELAY; + FLOWEQ1CTL = FlowStates[21]; // CTL1/CTL2 = 1 when flow condition equals one (data does not flow) + SYNCDELAY; +} + +void Setup_FLOWSTATE_Write ( void ) +{ + FLOWSTATE = FlowStates[27]; // 1000 0001b - FSE=1, FS[2:0]=001 + SYNCDELAY; + FLOWEQ0CTL = FlowStates[29]; // CTL0 = 0 when flow condition equals zero (data flows) + SYNCDELAY; + FLOWEQ1CTL = FlowStates[30]; // CTL0 = 1 when flow condition equals one (data does not flow) + SYNCDELAY; +} diff --git a/doc/GPIF/GPIF Designer/fifo/FX2_to_extsyncFIFO.gpf b/doc/GPIF/GPIF Designer/fifo/FX2_to_extsyncFIFO.gpf new file mode 100644 index 0000000..a2cd989 Binary files /dev/null and b/doc/GPIF/GPIF Designer/fifo/FX2_to_extsyncFIFO.gpf differ diff --git a/doc/GPIF/GPIF Designer/fifo/FX2_to_extsyncFIFO.hex b/doc/GPIF/GPIF Designer/fifo/FX2_to_extsyncFIFO.hex new file mode 100644 index 0000000..9e870c7 --- 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Designer/fifo/app_note.htm b/doc/GPIF/GPIF Designer/fifo/app_note.htm new file mode 100644 index 0000000..1ab2db4 --- /dev/null +++ b/doc/GPIF/GPIF Designer/fifo/app_note.htm @@ -0,0 +1,21 @@ + + +You need a browser that supports frame to veiw this page. + + + + + + + + + + + +<body bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> + +<p>You need a browser that supports frame to veiw this page.</p> +</body> + + + \ No newline at end of file diff --git a/doc/GPIF/GPIF Designer/fifo/app_note/Caption.htm b/doc/GPIF/GPIF Designer/fifo/app_note/Caption.htm new file mode 100644 index 0000000..4d42455 --- /dev/null +++ b/doc/GPIF/GPIF Designer/fifo/app_note/Caption.htm @@ -0,0 +1,24 @@ + + + +Index + + + + + + + + + +
+

 

+ 		+

FIFO + DESIGN EXAMPLE

+ 		+

 

+
+
+ + diff --git a/doc/GPIF/GPIF Designer/fifo/app_note/FifoXactions.htm b/doc/GPIF/GPIF Designer/fifo/app_note/FifoXactions.htm new file mode 100644 index 0000000..d211c1c --- /dev/null +++ b/doc/GPIF/GPIF Designer/fifo/app_note/FifoXactions.htm @@ -0,0 +1,602 @@ + + + + + GPIF + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +

Implementing FIFO + (multiple) Transactions +

+ +

+ A fully working external FIFO example using GPIF Single transactions has already been discussed, but the bandwidth achieved is miniscule. + This is because there is a lot of firmware overhead involved in launching GPIF Single transactions. With GPIF FIFO transactions, the GPIF engine + directly handles bursts of data, so a higher bandwidth over the physical interface is achievable.
+
Introducing + the Flow State Feature of the GPIF

In order to efficiently + handle bursts of data and meet burst access timing to the external + FIFO, the flow state feature of the GPIF was utilized for the FIFO + transaction example. The flow state feature makes its debut in the + FX2 GPIF and is a mechanism that allows the GPIF to efficiently + throttle data on and off the bus by using an independent set of + RDYn logic (flow logic) that is separate from the decision point + RDYn logic. Since the flow state feature is an advanced mode of + the GPIF, not every application will need to use the flow state. + However, handling bursts of data to and from an external FIFO shows + the simplest application of the flow state. One very advanced application + of the flow state is in the generation of UDMA waveforms for the + FX2 mass storage reference design firmware. +

In any GPIF waveform, there can + only be one flow state, but it can be any of the available non-idle + states (S0–S6). The flow state behavior is controlled by a set of + registers that are specific to the flow state feature (see the FX2 + Technical Reference Manual for flow state register details). One + can think of the flow state as being “orthogonal” to one of the + GPIF waveform’s states, but it is still the regular decision point + logic that is responsible for determining when the flow state should + be exited and the normal GPIF waveform behavior continues.

+

Another property of the flow state + is that it can be programmed to perform a different set of CTLx + logic than what is described in the GPIF waveform descriptors themselves. + This brings the level of autonomy to another notch. The idea behind + the GPIF FIFO Read and Write descriptor programming is to have the + read and write control lines assert for the duration of the transaction, + thereby allowing data to be moved on every edge of IFCLK. Therefore, + a 16-bit interface running at 48 MHz would yield an effective burst + data rate of 96 MB/s over the GPIF interface.

+

The main difference between this + FIFO transaction version and the single transaction version is that + waveforms 2 and 3 are used (FIFORd and FIFOWr waveforms, respectively) + instead of waveforms 0 and 1. RDY5 is used as the GPIF transaction + count (GPIF TC) internal expiration flag (TCXpire). The GPIF TC + is what is used in the waveform’s decision point logic to determine + when to exit out of the flow state and terminate the waveform.

+


Figure + 16.  Block Diagram for FIFO Transactions  +

+

Figure + 16 shows the set-up of the block diagram and the naming conventions + of the CTLx and RDYn signals (same as the single transaction example). + Figure 17 below shows waveform 3, which characterizes the behavior + of the FIFO Write waveform.

+


Figure + 17. FIFO Write waveform in GPIF Designer

+

In this FIFO Write waveform (waveform + 3) we see that S0 is a period of inactivity, followed by S1 which + is designated as the flow state. The decision point logic in S1 + looks at the GPIF TC to determine when to terminate the waveform + by branching to the IDLE state. As previously mentioned, the flow + logic in S1 then takes over to throttle data on and off the bus + and manipulate the CTLx lines. The flow state registers are set + up by selecting the various flow state parameters, accessed by right + clicking on the S1 state trace.

+

In order to set up the flow state + for both FIFO reads and writes, a set of global GPIF and flow state + registers are first initialized. The values are taken from a FlowStates[36] + array in gpif.c, generated by GPIF Designer.

+
    +

    (Note: The FlowStates array, + in GPIF.c, could be re-declared as FlowStates[4][9], for simplicity. +  The first 9 elements contain the FlowState register values + for waveform 0.  The next 9 elements contain the FlowState + register values for waveform 1, etc.  Therefore, FlowStates[19] + is the same element as FlowStates[2][1].)

    +

    EP2GPIFFLGSEL = 0x01; // + For EP2OUT, GPIF uses EF flag
    SYNCDELAY;
    EP6GPIFFLGSEL + = 0x02;     // + For EP6IN, GPIF uses FF flag
    SYNCDELAY;

    // + global flowstate register initializations
    FLOWLOGIC = FlowStates[19];     + // 0011 0110b - LFUNC[1:0] = 00 (A AND B), TERMA/B[2:0]=110 + (FIFO Flag)
    SYNCDELAY;
    FLOWSTB + = FlowStates[22];     // + 0000 0100b - MSTB[2:0] = 100 (CTL4), not used as strobe
    SYNCDELAY;
    GPIFHOLDAMOUNT + = FlowStates[26];     // + hold data for one half clock (10ns) assuming 48MHz IFCLK
    SYNCDELAY;
    FLOWSTBEDGE + = FlowStates[24];     // + move data on both edges of clock
    SYNCDELAY;
    FLOWSTBHPERIOD + = FlowStates[25];     // + 20.83ns half period
    SYNCDELAY;

    +
+

The set-up is such that when FIFO + Write transactions are launched from EP2OUT, the GPIF uses EP2’s + empty flag (EF) as the FIFO Flag, and when FIFO Read transactions + are launched into EP6IN, the GPIF uses EP6’s full flag (FF) as the + FIFO Flag.

+

Subsequently, the flow logic is + set up to use the FIFO Flag to throttle data on and off the bus, + so the flow state mechanism actually uses EP2EF and EP6FF status + to know when to keep writing to the data bus or keep reading from + the data bus, respectively.

+

Although CTL4 (unused) is not used + in the application, we take advantage of the fact that the flow + state can use any of the CTLx lines as a data strobe. At a 48-MHz + IFCLK, CTL4 is toggled at a half period of 20.83 ns. Since the flow + state is also programmed to move data on both edges of the data + strobe, this allows us to nicely align the data values with the + rising edge of IFCLK and achieve a 96-MB/s burst rate over the physical + interface. Note that although CTL4 is not physically exposed on + the 56-pin package, the flow state logic can still be set up to + use it as a data strobe.

+

Let’s also examine the flow state + register set-up that is specific to FIFO Writes:

+
    +

    void Setup_FLOWSTATE_Write + ( void )
    {
    FLOWSTATE = FlowStates[18];     + // 1000 0001b - FSE=1, FS[2:0]=001
    SYNCDELAY;
    FLOWEQ0CTL + = FlowStates[20];     // + CTL0 = 0 when flow condition equals zero (data flows)
    SYNCDELAY;
    FLOWEQ1CTL + = FlowStates[21];     // + CTL0 = 1 when flow condition equals one (data does not flow)
    SYNCDELAY;
    }

    +
+

Here we designate S1 to be the + flow state and define the state of CTL0 when the flow condition + equals zero (data flows) and when the flow condition equals one + (data does not flow). Remember that the state of the flow condition + is determined by the state of EP2EF. So when the EP2 FIFO contains + data (EP2 is not empty) the flow condition equals zero, the flow + state drops CTL0 LOW (WEN# is asserted), and data is placed on FD[15:0].

+

Figure 18 below shows waveform + 2, which characterizes the behavior of the FIFO Read waveform.

+


Figure + 18. FIFO Read waveform in GPIF Designer

+

In this FIFO Read waveform (waveform + 2) S0 is a period of inactivity, then S1 and S2 sets up the “front + porch” of the burst transfer, followed by S3 which is designated + as the flow state. The decision point logic in S3 looks at the GPIF + TC to determine when to terminate the waveform by branching to the + IDLE state. As previously mentioned, the flow logic in S3 then takes + over to throttle data reads from the bus and manipulate the CTLx + lines.

+

Let’s examine the flow state register + set-up that is specific to FIFO Reads:

+
    +

    void Setup_FLOWSTATE_Read ( + void )
    {
    FLOWSTATE = FlowStates[27];     // + 1000 0011b - FSE=1, FS[2:0]=003
    SYNCDELAY;
    FLOWEQ0CTL + = FlowStates[29];     // + CTL1/CTL2 = 0 when flow condition equals zero (data flows)
    SYNCDELAY;
    FLOWEQ1CTL + = FlowStates[30];     // + CTL1/CTL2 = 1 when flow condition equals one (data does not + flow)
    SYNCDELAY;
    }

    +
+

Here we designate S3 to be the + flow state and define the state of CTL1 and CTL2 when the flow condition + equals zero (data flows) and when the flow condition equals one + (data does not flow). Remember that the state of the flow condition + is determined by the state of EP6FF. So when the EP6 FIFO has room + for data (EP6 is not full) the flow condition equals zero, the flow + state drops CTL1 and CTL2 LOW (REN and OE are asserted), and data + is read from FD[15:0].

Since there is a different flow state + register set-up for FIFO read and write operations, the firmware + has to call Setup_FLOWSTATE_Read() before launching a GPIF FIFO + read transaction, and call Setup_FLOWSTATE_Write() before launching + a GPIF FIFO write transaction.

+

Now that you understand how the + GPIF FIFO read and write waveforms were programmed and set up, the + firmware programming for GPIF FIFO transactions can be discussed. 

+ +
+

 

+
+ +

+ +

+

FIFO Transaction + Firmware
 

+
+

+ In moving from GPIF Single transactions to GPIF FIFO transactions, the only major difference really lies in the TD_Poll() code. The basic underlying + architecture of the example remains the same. In this section, the basic principles of launching a FIFO transaction are introduced. Following that + is a discussion of the TD_Poll() code that triggers the GPIF FIFO transactions.
 

+ + +
    +Triggering GPIF FIFO Transactions

    For triggering GPIF FIFO transactions, we reiterate the concept of the GPIF transaction count (TC). Analogous to the Tcount variable in the single + transaction example, the TC is a value the GPIF engine uses to determine how many times to go through a FIFO waveform.

    For example, if the user wished to burst out 512 bytes of data from the EP2OUT endpoint, the TC value would be set to 512 (for byte wide operation) or 256 + (for word wide operation). The GPIF engine then decrements the TC value on every push or pop of the FIFO. When the TC value reaches zero, the waveform is + complete (a waveform completion is signified by the GPIFDONE being set in the GPIFIDLECS register). A decision point state can use the TC value as an + internal flag to determine whether or not to branch to the IDLE state. GPIFREADYCFG.5 must be set to allow the GPIF engine to use the RDY5 signal as an + internal TC expiration flag.
    +
    + The act of triggering a GPIF FIFO transaction is actually very simple. Writing to the R/W bit in the GPIFTRIG register sets the direction of the + transaction. If R/W=1, a FIFO Read transaction gets triggered when accessing the GPIFTRIG register. If R/W=0, a FIFO Write transaction get triggered + instead.

    For example, to trigger a GPIF FIFO Read transaction to EP6IN use the following line of code:

     +

    GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO Read transaction to EP6IN

    To trigger a GPIF FIFO Write transaction from EP2OUT use the following line of code:
     +

    GPIFTRIG = GPIF_EP2; // launch GPIF FIFO Write transaction from EP2OUT

    GPIFTRIGRD, GPIF_EP6, and GPIF_EP2 are bit masks to set the appropriate bits in the GPIFTRIG register. By setting the EP[1:0] bits in the GPIFTRIG + register to valid options of 0,1,2, or 3 (in order of the endpoints 2,4,6, and 8), this specifies which endpoint should be used in the transaction. + Source or sink direction is implied by whether the endpoint is an IN or and OUT endpoint.      +

+ + + + +
+ +
    +TD_Init( )  +
+ +
+
    + +

    +The initialization code in TD_Init( ) remains pretty much the same as the single transaction version. The main differences lie in the setup of the FIFOCFG + registers. To maximize the USB 2.0 bandwidth, the endpoints are placed into auto mode (AUTOOUT/AUTOIN=1). Note that the bits 1 and 0 of the REVCTL + register are not set. Therefore, it is necessary to first set AUTOOUT=0, then set AUTOOUT=1. The FX2 needs to see a 0 to 1 transition of the AUTOOUT + bit to automatically arm the endpoint buffers.  +

+
+
    +

    +// set the CPU clock to 48MHz
    + CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
    + SYNCDELAY;
    +
    + EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
    + SYNCDELAY;
    + EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered
    + SYNCDELAY;
    +
    + FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
    + SYNCDELAY;
    + FIFORESET = 0x02; // reset EP2 FIFO
    + SYNCDELAY;
    + FIFORESET = 0x06; // reset EP6 FIFO
    + SYNCDELAY;
    + FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
    + SYNCDELAY;
    +
    + EP2FIFOCFG = 0x01;
    + SYNCDELAY;
    + EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word ops
    + SYNCDELAY;
    + EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops
    + SYNCDELAY;
    +
    + GpifInit (); // initialize GPIF registers
    +
    + // reset the external FIFO
    + OEA |= 0x04; // turn on PA2 as output pin
    + IOA |= 0x04; // pull PA2 high initially
    + IOA &= 0xFB // bring PA2 low
    + EZUSB_Delay (1); // keep PA2 low for ~1ms, more than enough time
    + IOA |= 0x04; // bring PA2 high
    +

+ +
+ +

+ +

    +TD_Poll()  +
+ +
+
    + +

    +The first thing the OUT handling code does is it checks to see if the GPIF is IDLE. If so, it checks to see if there is at least a packet in the + peripheral domain for EP2. Since EP2 is placed into auto mode, the firmware does not need to check if the host sent a USB packet. The USB packets are + automatically committed to be used by the GPIF engine. Therefore, the firmware's job is to check if at least one packet has been committed to the + peripheral domain.
    +
    + Then, if the external FIFO is not full, the TC value is setup for word wide operation (256). The TC value is a 32-bit register field, but for this + application only the lower 16-bit fields are necessary. Since each GPIF FIFO Write transaction sends 512 bytes to the external FIFO over a 16-bit + interface, the number of transactions is always half the number of bytes actually contained within the endpoint buffer. The appropriate TC value is + setup for either high speed or full speed operation.
    +
    + The appropriate flow state registers are then setup for the FIFO Write transaction, and a write to the GPIFTRIG register with the appropriate bits + triggers the transaction from EP2OUT. The code then waits for the transaction to complete before exiting out of the "if" nest.

    // code that handles USB OUT transfers

    + if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
    + {
    +     if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there's a packet in the peripheral domain for EP2
    +     {
    +         if ( EXTFIFONOTFULL ) // if the external FIFO is not full
    +         {
    +             if(enum_high_speed)
    +             {
    +                 SYNCDELAY;
    +                 GPIFTCB1 = 0x01; // setup transaction count (512 bytes/2 for word wide -> 0x0100)
    +                 SYNCDELAY;
    +                 GPIFTCB0 = 0x00;
    +                 SYNCDELAY;
    +             }
    +             else
    +             {
    +                 SYNCDELAY;
    +                 GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20)
    +                 SYNCDELAY;
    +                 GPIFTCB0 = 0x20;
    +                 SYNCDELAY;
    +             }
    +
    +             Setup_FLOWSTATE_Write(); // setup FLOWSTATE registers for FIFO Write operation
    +             SYNCDELAY;
    +             GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
    +             SYNCDELAY;
    +
    +             while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
    +             {
    +                ;
    +             }
    +             SYNCDELAY;
    +         }
    +     }
    + }

    Just like the single transaction firmware, if the in_enable flag is not set, the code will just sit there and not process the INs.
    +
    + If the in_enable flag is set, the code will fall through and check if the GPIF interface is IDLE. It then goes on to check if the external FIFO is + not empty. If the external FIFO has data, the code then determines if EP6 has room for at least one more data packet.
    +
    + If EP6 has room for at least one more data packet, the TC value is setup for word wide operation (256). The appropriate TC value is setup for either + high speed or full speed operation. The flow state registers are then setup for the FIFO Read transaction, and a write to the GPIFTRIG register with + the appropriate bits triggers the transaction to fill the EP6 FIFO. The code then waits for the transaction to complete. Since EP6 is placed into auto + mode, there is no need to explicitly write a byte count value to indicate how many bytes to send to the host. FX2 uses the EP6AUTOINLENH/L register + values set at enumeration time in the DR_SetConfiguration() function for the auto commit size.

    // code that handles USB IN transfers

    if (in_enable) // if IN transfers are enabled
    + {
    +     if ( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
    +     {
    +         if ( EXTFIFONOTEMPTY ) // if external FIFO is not empty
    +         {
    +             if ( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full
    +             {
    +                 if (enum_high_speed)
    +                 {
    +                     SYNCDELAY;
    +                     GPIFTCB1 = 0x01; // setup transaction count (512 bytes/2 for word wide -> 0x0100)
    +                     SYNCDELAY;
    +                     GPIFTCB0 = 0x00;
    +                     SYNCDELAY;
    +                 }
    +                 else
    +                 {
    +                     SYNCDELAY;
    +                     GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20)
    +                     SYNCDELAY;
    +                     GPIFTCB0 = 0x20;
    +                     SYNCDELAY;
    +                 }
    +
    +                 Setup_FLOWSTATE_Read(); // setup FLOWSTATE registers for FIFO Read operation
    +                 SYNCDELAY;
    +                 GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO
    +                 SYNCDELAY;
    +
    +                 while ( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
    +                 {
    +                     ;
    +                 }
    +
    +                 SYNCDELAY;
    +             }
    +         }
    +     }
    + }

          +

+
+ +

Running the example for GPIF FIFO Transactions

The procedure for running the FIFO transaction example is essentially the same as the Single transaction example. Going through steps 1 through 3 of + section 4.1.6 will allow the user to run the FIFO transaction example as well. For running this version of the example, unzip the "FX2_to_extsyncFIFO GPIF + FIFO Transactions Auto mode.zip" package instead.
+
+ A couple of differences to note are that LED0 will no longer flash when the code is downloaded, and that a few more vendor commands were added for + debug purposes. The LED0 code was taken out of TD_Poll() to optimize the firmware execution for FIFO transactions.
+
Debug Tip:
+ The use of vendor commands is a "cheap" way to add more debug functionality to the code without incurring unnecessary "printf" statements. With the use of + vendor commands, the Keil debugger is not necessary for peeking and poking register values after the fact, which is what most GPIF firmware developers will + end up doing. For example, the vendor command 0xb6 was added to the FIFO transaction firmware to read back the status of the GPIF engine. The vendor + command returns the 0xb6 request with the value of the GPIFTRIG register. If the GPIF engine has completed a FIFO read or write transaction, the GPIFDONE + bit is set, returning a value of 0x80. The screenshot below shows what the user should see in the EZ-USB Control Panel window.
 +

    +


     

    +
+
+ +

Logic + Analyzer Traces

These are the traces the user should + see on the logic analyzer as the FIFO transaction example runs. +  The traces were captured using an HP1660C logic analyzer.

 

+
+ +

FIFO Write: Close-up view of the front porch

This trace shows that the 4 ns data setup time for the external FIFO is satisfied using the X to 0 marker as an indicator. The word + consisting of data values 0x02 and 0x03 is written into the external FIFO on the rising edge of IFCLK (the external FIFO's WCLK). + While WEN/ is held low, consecutive words are written into the external FIFO on every rising edge of IFCLK. Notice that the + GSTATE bus reflects the state of the GPIF engine as it's progressing through the GPIF FIFO Write waveform. S0 is a period of + inactivity for 1 IFCLK cycle (20.83 ns) and S1 is the flow state and is active for the entire duration of the data burst phase.

 +

 

+
+ +

FIFO Write: + Close-up view of the back porch

Here we see the back end of the 512 byte transfer at a zoomed in level. The last word in the packet consists of data values 0xFE + and 0xFF (the end of our ramp test data). Note that a repeated word at the end is not clocked in as the setup time for the WEN/ + line is not met prior to the IFCLK edge.

 

 

+ +

FIFO Write: + Time taken to transfer 512 bytes to the external FIFO

This trace shows how long it takes to write a burst of 512 bytes (256 words) into the external FIFO. At a burst rate of 96MB/s (one + word every IFCLK period), this results in a time of approximately 5.3 microseconds to transfer a payload of 512 bytes. This zoomed + out view allows us to see that indeed the GPIF FIFO Write waveform remains in the flowstate until it is done transferring 512 + bytes, at which point it then transitions to the IDLE state (S7).

 

 

+ +

FIFO Write: + Inter-packet transfer time

In this trace we examine the inter-packet transfer time between consecutive OUTs sent by the host. Notice that the FX2 has + approximately 20 microseconds to spare before it has to burst out the next OUT packet. This means that the host is behind.

 

 

+ +

FIFO Read: + Close-up view of the front porch

This trace shows that the 9.2 ns data setup time for the GPIF is satisfied using the X to 0 marker as an indicator. The word + consisting of data values 0x00 and 0x01 is read from the external FIFO on the rising edge of IFCLK (the external FIFO's RCLK). + While REN/ is held low, consecutive words are read from the external FIFO on every rising edge of IFCLK. Notice that the GSTATE + bus reflects the state of the GPIF engine as it's progressing through the GPIF FIFO Read waveform. S0 is a period of inactivity + for 1 IFCLK cycle (20.83 ns). In S1, the REN/ is asserted since the external FIFO requires that the REN/ be setup tENS before + the OE/ line is asserted. S2 asserts the OE/ line, and S3 is the flow state and is active for the entire duration of the data burst phase.

 

 

+ +

FIFO Read: + Close-up view of the back porch

Here we see the back end of the 512 byte transfer at a zoomed in level. The last word in the packet consists of data values 0xFE + and 0xFF (the end of our ramp test data). Note that a repeated word at the end is not clocked in as the setup time for the REN/ + line is not met prior to the IFCLK edge.

 

 

+ +

FIFO Read: + Time taken to read 512 bytes from the external FIFO

This trace shows how long it takes to read a burst of 512 bytes from the external FIFO. At a burst rate of 96MB/s (one word every + IFCLK period), this results in a time of approximately 5.3 microseconds to transfer a payload of 512 bytes. This zoomed out view + allows us to see that indeed the GPIF FIFO Read waveform remains in the flowstate until it is done transferring 512 bytes, at + which point it then transitions to the IDLE state (S7).

 

 

+ +

FIFO Read: + Inter-packet transfer time

In this trace we examine the inter-packet transfer time between consecutive INs requested by the host. Notice that the FX2 has + approximately 20 microseconds to spare before it has to fulfill the next IN request. This means that the host is behind.

 

 

+ +

Bulk Loopback: + FIFO Reads and Writes

The user will observe the above wavefrom when the bulkloop utility is exercised. This trace shows activity that includes both reads + and writes to the external FIFO. We notice here that the host judiciously schedules INs and OUTs. No favoritism is shown to either + type of transfer.

  +

 

+
+ +

Summary

+

This design example of a 16-bit interface to an external synchronous FIFO has +brought to the forefront many GPIF programming fundamentals, such as determining +GPIF hardware connections, creating GPIF single and FIFO waveform descriptors +using the GPIF Tool, and how to launch GPIF single and FIFO transfers in +firmware. The user should now have a firm grasp of what it takes to create a +full featured GPIF applications solution, and how to go from a simple set of +firmware that utilizes GPIF single transactions, to a more complex and robust +application that uses GPIF FIFO transfers. Also, by now the user should be aware +that the logic analyzer is a GPIF programmer's best friend. Let's extend the +basic toolset the user should already have by presenting a more complex design example using a TI +DSP.

+
+ +  + + + + + + + + + + + + + + + + + + + diff --git a/doc/GPIF/GPIF Designer/fifo/app_note/SingleXactions.htm b/doc/GPIF/GPIF Designer/fifo/app_note/SingleXactions.htm new file mode 100644 index 0000000..808b366 --- /dev/null +++ b/doc/GPIF/GPIF Designer/fifo/app_note/SingleXactions.htm @@ -0,0 +1,846 @@ + + + + + GPIF + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +

Implementing Single Transactions +

+ +

+ As previously mentioned, the simplest GPIF waveforms to produce are the single read and single + write waveforms. Performing this + function first not only enhances the initial user experience with the design, but also allows the design to be in fairly good shape, fairly quickly. Of + course, for high bandwidth applications the natural migration is then to create FIFO read and write transactions. +  But, the implementation of single + transactions is the right place to start. The + first section discusses the single transaction waveforms implemented using GPIF Designer and the next section + covers the firmware that triggers them.
+ +

 
Figure + 12. GPIF Designer Block Diagram

+

+The GPIF Designer makes creating GPIF waveform + descriptors easy. Rather than having to know each bit of the waveform + descriptor opcode bytes in detail to create a waveform, the GPIF + Designer allows you to “draw” each waveform and export the waveform + descriptors to a self-contained file, typically called gpif.c. When + you open GPIF Designer, it will present you with a block diagram + view of the physical interconnect as shown in Figure 12. You can + then use the block diagram view to name the individual + CTLx lines and + RDYn signals. These names propagate into the waveform tabs, allowing + you to personalize each waveform and determine which signals are + being manipulated. You can also use the block diagram to configure + the clock properties of IFCLK, select different package types, and + label the external slave device.

We + can see that the naming conventions are consistent with the hardware + set-up. The single write waveform (waveform 1) is shown below in + Figure 13.
 +

+


 Figure + 13.  Single Write waveform in GPIF Designer

+
+

For the single write + waveform, data is written to the external FIFO in S0 by making CTL0 + a logic LOW (WEN is asserted) and placing data on the bus (Activate + Data) for one IFCLK cycle (Wait 1). At 48 MHz, one IFCLK cycle is + 20.83 ns. With the IFCLK output inverted, this provides enough set-up + and hold time for the data.

+

S1 is a decision-point + state that forces an unconditional branch to the IDLE state, which + terminates the waveform (no activity occurs in the IDLE state). + A decision point state allows you to pick, at most, two terms to + evaluate a logical expression. Based on the results of that evaluation, + you can control the next state the waveform goes to. See the FX2 + Technical Reference Manual for more information on decision point + states. Also in S1, CTL0 is a logic HIGH (WEN is de-asserted), and + the data bus is tri-stated (De-activate Data).

+

Every time a single + write waveform is initiated, the GPIF engine will cycle through + S0, S1, and then IDLE (S7).

The single read waveform (waveform 0) + is very similar to the single write waveform. The single read waveform + is shown in Figure 14.

+

 

+
+


Figure + 14. Single Read waveform in GPIF Designer

+

For the single read + waveform, CTL1 starts off as a logic LOW in S0 (REN asserted) for + one IFCLK cycle. This is to account for a t ENS set-up time for + the external FIFO before OE (CTL2) is asserted. S1 then asserts + OE, and in S2 the data bus is sampled (Activate Data) and an unconditional + branch to the IDLE state is taken to terminate the waveform (no + activity occurs in the IDLE state).

+

Note that the data + bus is sampled in S2 when it would be tempting to sample it in S1. + At the beginning of S1, the data is not yet available from the external + FIFO, therefore the GPIF has to “catch” the data at the beginning + of S2. This is why the data bus is sampled in S2 instead of S1.

+

Every time a single + read waveform is initiated, the GPIF engine will cycle through S0, + S1, S2, and then IDLE (S7). Notice that waveforms 2 and 3 are unused + for the single transaction example, but will be used later for the + FIFO transaction example.

+

 

+
+

Single Transaction + Firmware

+
+

+ After the single transaction waveforms were implemented in the GPIF Designer, the next step was to integrate the USB portion of the + overlying firmware with the GPIF Designer output to perform write and read operations to and from the external FIFO. To do this a firmware frameworks project + was copied and the code that performed the external FIFO operations was added to the TD_Poll() function within FX2_extsyncfifo.c (note that periph.c was + renamed to something more meaningful here). Endpoint and GPIF register initialization is performed in the TD_Init() function, which is also within + FX2_extsyncfifo.c.

When the user opens up the Keil uVision2 project for the FIFO example, the following should be the list of files shown in the Project Window: 

+ +     +
+ +
    +

    The + contents of these files is as follows:
    +

    +
+ +
+
    +

    fw.c
    Firmware + frameworks which handles USB requests and calls the task dispatcher + TD_Poll(). 

    +
+ +
+
    +

    Ezusb.lib
    Collection + of functions that handle suspend, resume, I2C operations, etc. 

    +
+ +
+
    +

    USBJmpTb.OBJ
    Interrupt + vector jump table for USB (INT2) and GPIF/Slave FIFO (INT4) + interrupt sources. 

    +
+ +
+
    +

    dscr.a51
    Device + descriptor tables for the FIFO example which report EP2OUT and + EP6IN as the available endpoints for the FX2 device. 

    +
+ +
+
    +

    FX2_to_extsyncFIFO.c
    Main + user application code where TD_Poll() and TD_Init() can be found. + The user will mainly be modifying this particular file and will + not need to touch fw.c. 

    +
+ +
+
    +

    gpif.c
    File + that contains the GPIF waveform descriptor tables that implement + the Single/FIFO GPIF transaction waveform behavior.
     

    +
+ +
+ +
    +TD_Init( )  + +
+ +
+
    + +

    + The first task at hand was to setup the endpoints appropriately for this example. The following code switches the CPU clock + speed to 48MHz (since at power-on default it is 12MHz), and sets up EP2 as an OUT endpoint, 4x buffered of size 512, and EP6 as an IN endpoint, also + 4x buffered of size 512. This setup utilizes the maximum allotted 4KB FIFO space. It also sets up the FIFOs for manual mode, word wide operation and + goes through a FIFO reset and arming sequence to ensure that they are ready for data operations.
    +     +

+ +
+
+
    +// set the CPU clock to 48MHz
    + CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
    + SYNCDELAY;
    +
    + EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
    + SYNCDELAY;
    + EP4CFG = 0x00; // EP4 not valid
    + SYNCDELAY;
    + EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered
    + SYNCDELAY;
    + EP8CFG = 0x00; // EP8 not valid
    + SYNCDELAY;
    +
    + EP2FIFOCFG = 0x01; // manual mode, disable PKTEND zero length send, word ops
    + SYNCDELAY;
    + EP6FIFOCFG = 0x01; // manual mode, disable PKTEND zero length send, word ops
    + SYNCDELAY;
    +
    + FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
    + SYNCDELAY;
    + FIFORESET = 0x02; // reset EP2 FIFO
    + SYNCDELAY;
    + FIFORESET = 0x06; // reset EP6 FIFO
    + SYNCDELAY;
    + FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
    + SYNCDELAY;
    +
    + // out endpoints do not come up armed
    + // since EP2OUT is quad buffered we must write dummy byte counts four times
    +
    + EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
    + SYNCDELAY;
    + EP2BCL = 0x80;
    + SYNCDELAY;
    + EP2BCL = 0x80;
    + SYNCDELAY;
    + EP2BCL = 0x80;
    + SYNCDELAY;
    +
    + GpifInit (); // initialize GPIF registers
    +
    +
+ +
+ +
+ +
    +IFCONFIG Register
    + +     +
+ +
+
    + +

    + TD_Init then calls the function GPIFInit() that resides in gpif.c. GPIFInit() is where the loading of the GPIF waveform + descriptor table into on-chip memory takes place and other GPIF registers get setup. An important register, IFCONFIG, also gets setup here to define + how the physical interface operates. Table 2 goes through the reasoning behind the setup of the IFCONFIG register for this example. +  Note that all these bit assignments were made, automatically + by GPIF Designer as a consequence of the Block Diagram configuration.

    +     +

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

Bit + #

+ 		+

Bit + Label

+ 		+

Contents + / Description

+
+

7

+ 		+

IFCLKSRC

+

Set + to 1 to run the GPIF using the internal clock source

+ +
+

6

+ 		+

3048MHz

+ 		+

Set to 1 to run the + internal clock source for the GPIF at 48MHz.

+
+

5

+ 		+

IFCLKOE

+ 		+

Set to 1 to turn on + the IFCLK output to drive the WCLK and RCLK inputs of + the external FIFO.

+
+

4

+ 		+

IFCLPOL

+ 		+

Set to 1 to invert + the IFCLK output to the external FIFO. This allows enough + setup time for the external FIFO.

+
+

3

+ 		+

ASYNC

+ 		+

Set to 0 to operate + the GPIF at the highest rate (sync mode).

+
+

2

+ 		+

GSTATE

+ 		+

Set to 1 to turn on + the debug outputs of the state machine. PE[2:0] displays + the states the GPIF engine cycles through during each + transaction (Note: PE[2:0] are only available on the + 100- and 128-pin packages).

+
+

1

+ 		+

IFCFG1

+ 		+

Set to 1 to put the + FX2 part into GPIF mode (internal master).

+
+

0

+ 		+

IFCFG0

+ 		+

Set to 0 to put + the FX2 part into GPIF mode (internal master).

+
+

Table 2. IFCONFIG register bit settings for FIFO example
+
+

+ +
+
    + +

    + The next thing TD_Init() does is it resets the external FIFO by pulsing PA2. This ensures that the external FIFO is at a + ground-zero state before commencing data operations. The following code does the trick:
    + +     +

+ +
+ +

+ 

+
    +// reset the external FIFO
    +
    + OEA |= 0x04; // turn on PA2 as output pin
    + IOA |= 0x04; // pull PA2 high initially
    + IOA &= 0xFB; // bring PA2 low
    + EZUSB_Delay (1); // keep PA2 low for ~1ms, more than enough time
    + IOA |= 0x04; // bring PA2 high
    +     +
+ +
+ +
+
    + +

    +A vendor command was also setup in the DR_VendorCmnd() function so that the user could reset the external FIFO at any time by + performing a vendor request of 0xB2 from the EZ-USB Control Panel.  +

+
+ +
    +

    Triggering GPIF Single Transactions
     +

+
+
    + +

    + In order for the data transfers to occur across the physical interface, the CPU needs to trigger the GPIF waveforms by accessing + the registers XGPIFSGLDATH, XGPIFSGLDATLX, and XGPIFSGLDATLNOX.

    In order to trigger a GPIF Single Word Write transaction, the user writes to the XGPIFSGLDATAH< and XGPIFSGLDATLX in the following manner:

    + XGPIFSGLDATH = <word_value> >> 8;
    + XGPIFSGLDATLX = <word_value> // trigger GPIF

    This effectively setups the MSB and LSB of the word value to be transferred, and the sheer act of writing to the XGPIFSGLDATLX register fires + off the Single Word Write transaction. To make things a little neater to follow in TD_Poll(), the following function was defined which basically + accepts a word value as an input argument and performs the GPIF Single Word Write transaction:
     +

      +

      // reset the external FIFO
      + void GPIF_SingleWordWrite( WORD gdata )
      + {
      +     while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
      +     {
      +       ;
      +     }
      + +     // using registers in XDATA space
      +     XGPIFSGLDATH = gdata;
      +     XGPIFSGLDATLX = gdata >> 8; // trigger GPIF Single Word Write transaction
      + }

      +
    +

    This function also checks to see if the GPIF is in the IDLE state (GPIFTRIG.7 is set if GPIF is IDLE) before it launches the transaction. This is + something that is necessary before launching any GPIF transaction. Note that the access to the single transaction registers is swapped here because + the endpoint buffer is organized as a FIFO. The swapping ensures that the first byte in the endpoint buffer is written out FD[7:0], and the second + byte is written out FD[15:8].
    +
    + In order to trigger a GPIF Single Word Read transaction, the user performs a dummy read from the XGPIFSGLDATX register. The word value just read will + be contained in the registers XGPIFSGLDATH and XGPIFSGLDATLNOX.

    To make things a little neater to follow in TD_Poll(), the following function was defined which basically accepts a word pointer for the + destination variable as an input argument and performs the GPIF Single Word Read transaction:

    +
      +

      void GPIF_SingleWordRead( WORD xdata *gdata )
      + {
      +     static BYTE g_data = 0x00; // dummy variable
      +
      +     while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
      +     {
      +       ;
      +     }
      +
      +     // using register in XDATA space
      +     g_data = XGPIFSGLDATLX; // dummy read to trigger GPIF Single Word Read transaction
      +
      +     while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
      +     {
      +       ;
      +     }
      +
      +     // using register(s) in XDATA space, retrieve word just read from external FIFO
      +     *gdata = ( ( WORD )XGPIFSGLDATLNOX << 8 ) | ( WORD )XGPIFSGLDATH;
      + }

      +
    +

    This function first checks to see if the GPIF is IDLE and then performs a dummy read from XGPIFSGLDATLX to fire off the GPIF Single Word Read + transaction. Then, another check is performed before accessing the registers that contain the word value.
    +  

    + +
+ +
+ +

+ +

    +TD_Poll()
    +     +
+ +
+
    + +

    +The TD_Poll() function is where the main application code resides. The firmware here calls the functions GPIF_SingleWordWrite() and + GPIF_SingleWordRead to send and receive data from EP2OUT and EP6IN, respectively.

    Code that handles USB OUT transfers     +

      +

      if(!(EP2468STAT & bmEP2EMPTY) && (EXTFIFONOTFULL))
      + {
      +     // if host sent data to EP2OUT AND external FIFO is not full
      +
      +     Tcount = (EP2BCH << 8) + EP2BCL; // load transaction count with EP2 byte count
      +     Tcount /= 2; // divide by 2 for word wide transaction
      +     Source = (WORD *)(&EP2FIFOBUF);
      +     for( i = 0x0000; i < Tcount; i++ )
      +     {
      +         // transfer data from EP2OUT buffer to external FIFO
      +         GPIF_SingleWordWrite (*Source);
      +         Source++;
      +     }
      +     EP2BCL = 0x80; // re-arm EP2OUT
      + }

      +
    +

    The first thing the OUT handling code does is it checks to see if the host sent data to EP2OUT, and if the external FIFO is not full by accessing the + GPIFREADYSTAT register (EXTFIFONOTEMPTY is a macro for GPIFREADYSTAT & bmBIT0).

    If both conditions are met, the word variable Tcount is setup appropriately. Since each GPIF Single Word Write transaction sends an entire word to + the external FIFO, the number of transactions is always half the number of bytes actually contained within the endpoint buffer.

    A for loop then calls the GPIF_SingleWordWrite function and indexes through the endpoint buffer values, sending a word out to the external FIFO + at a time. The last step then is to re-arm the endpoint buffer so that the next USB data packet can be accepted    .

    + +

    +Code that handles USB IN transfers  +

      + + +

      if(in_enable) // if IN transfers are enabled
      + {
      +     if(!(EP2468STAT & bmEP6FULL) && (EXTFIFONOTEMPTY))
      +     {
      +     // if EP6IN is not full AND there is data in the external FIFO
      +
      +     Destination = (WORD *)(&EP6FIFOBUF);
      +     for( i = 0x0000; i < Tcount; i++ )
      +     {
      +         // transfer data from external FIFO to EP6IN buffer
      +         GPIF_SingleWordRead (Destination);
      +         Destination++;
      +     }
      +     Tcount *= 2; // multiply by 2 to obtain byte count value
      +     EP6BCH = MSB(Tcount);
      +     SYNCDELAY;
      +     EP6BCL = LSB(Tcount); // arm EP6IN to send data to the host
      +     SYNCDELAY;
      +     }
      + }       +

    +

    Another vendor command (0xB3) is setup to enable the IN transfers to occur. Otherwise, the code will just sit there and not process the INs. The + reason for the in_enable flag is so that the user can test each read and write operation independently. Otherwise, after the OUT handling code, the + IN is processed immediately. This is also useful for debugging purposes with the logic analyzer. It allows the user to capture each read/write + operation relatively easily.

    If the in_enable flag is set, the code will fall through and check if the EP6IN endpoint buffer is not full, and if the external FIFO is not empty + (The CPU can check the status of the RDY signals by accessing the GPIFREADYSTAT register, so EXTFIFONOTEMPTY is a macro for GPIFREADYSTAT & bmBIT1).

    If both conditions are met, a for loop then calls the GPIF_SingleWordRead function and indexes through the endpoint buffer values, receiving a word from + the external FIFO at a time. The last step then is to re-arm the endpoint buffer so that the next USB data packet can be accepted. Since each GPIF + Single Word Read transaction receives an entire word from the external FIFO, the number of transactions is always half the number of bytes actually + contained within the endpoint buffer.

     

    + +
+ +
+ +

Running the example for GPIF Single Transactions
 

+ +

+Now that the user understands how this FIFO example works, the bulk loop back function can be exercised by performing the steps discussed in this section.

Step 1: Download the firmware using the EZ-USB Control Panel +

    +

    a) + Unzip the "FX2_extsyncFIFO GPIF Single Transactions.zip" package in the C:\Cypress\Usb\Examples\FX2 directory.

    +

    b) + After the user plugs-in the FX2 board, launch the EZ-USB Control Panel and ensure that the selected target is FX2.

    +

    c) + Then, press the "Download" button and select the FX2_extsyncFIFO.hex file. The FX2 board renumerates as a Cypress EZ-USB Sample Device and LED0 should come up flashing.

    +

    d) + Perform a "Get Pipes" and "Get Dev" to verify one more time that the firmware is up and running. The user should then see the following screen shown below:

    +
+ + +
    +

+ + +


 

+
+ +

+Step 2: Setup bulk IN transfer and send 512 bytes to the external FIFO
 +

    +

    a) + On the same line as the "BulkTrans" button, select Endpoint 6 IN as the "Pipe" and specify a "Length" of 512 bytes. Then click the + "BulkTrans" button. This will setup a bulk IN transfer of 512 bytes to read that amount from the external FIFO. Select View -> Pending Ops to + see the pending bulk IN transfer.

    +

    b) + On the same line as the "FileTrans.." button, select Endpoint 2 OUT as the "Pipe". Press the "FileTrans.." button and select the 512_count.hex + file. Click on "Open" and this action will send out 512 bytes out to the external FIFO (the data stream is a ramp).

    +

    c) + Even though 512 bytes have been written into the external FIFO the IN transfer is not processed. This is because the in_enable flag in the firmware has not yet been set to TRUE.

    +
+ + +
    +

+ + +

 

+
+ +

+Step 3: Complete IN transfer to read back 512 bytes from the external FIFO
+
+ In order to complete the pending IN transfer and read back 512 bytes from the external FIFO, the in_enable flag must be set to TRUE (remember that + this allows the INs to be processed in the TD_Poll routine). To set the flag, on the same line as the "Vend Req" button, enter a value of 0xb3 in the + "Req" field. Then click the "Vend Req" button. The user should now see the 512 bytes read back from the external FIFO displayed in the window.
 +

    + +

    +
+

 

+
+ +

+The bulk loop back function can also be exercised by running the bulkloop.exe utility supplied with the EZ-USB development kit software. After + downloading the firmware, launch the bulkloop.exe utility found in the C:\Cypress\Usb\Bin sub-directory. The user should setup the parameters + according to the following screen: +

+ +

+Prior to clicking the "Start" button to commence the bulk loop back transfers, the user should perform the 0xb3 vendor request to set the in_enable flag + to TRUE. By clicking the "Start" button, the user should see the "Pass" counter increment as each loop back transfer is exercised. Clicking on the "Stop" + button will end the loop back transfers. The data values are also checked by the bulkloop utility on each pass, so the user should see the "Error" count + increment if any data value does not match. The application will also stop on any error if the "Stop on Error" checkbox is selected.
+
+ + Debug Tip:
+ While running this example and at any time during GPIF development, the user is strongly encouraged to connect a logic analyzer to the relevant signals + on the development kit headers. Monitoring the GPIF bus transactions aids debug sessions tremendously, and is essential for anyone seriously interested + in writing GPIF firmware. The next topic presents the waveforms the user should see on the logic analyzer as the example is run. An HP1660C Logic + Analyzer was used to capture the waveforms.
 +

 

+
+ +

Logic Analyzer Waveforms
 

+ +
    +

    Single Write Waveform
     +

      +

       

      +
    + +
+
    + +

    +The waveform above shows the timing generated by the GPIF engine for the Single Write waveform as defined by the GPIF tool. All the essential signals + are presented here, including GSTATE[2:0], which displays the states the GPIF engine cycles through as it performs the Single Write transaction.

    Debug Tip:
    +
    + Bringing out the GSTATE signals to the logic analyzer headers allows the user to correlate between the waveforms generated by the GPIF tool, and + the actual waveforms generated on the physical interface. This also aids the debugging process because the user can see the immediate effect of + changing the waveform behavior in the GPIF tool    .

    As expected from the GPIF tool output, S0 places the data on the bus (PORTB is FD[7:0] and PORTD is FD[15:8]), and asserts CTL0 (connected to the + external FIFO's WEN/ line). This effectively writes the 16-bit data value into the external FIFO. Note here that enough data setup time to the + rising edge of IFCLK is provided, since the minimum data setup time for the external FIFO is 4 ns (see CY4265 datasheet). S1 is a decision point + state that unconditionally branches to the IDLE state to terminate the transaction. Without the unconditional branch, the GPIF engine would + sequentially move through the remaining states until the IDLE state (S7) is reached.
    +
    + For every word written out in a bulk OUT transfer, the user should see the GPIF engine cycle through S0, S1, and S7. To capture the waveform, the + user should trigger the logic analyzer on the falling edge of CTL0. A sampling rate of 4 ns will give the user the same resolution shown in the + waveform above.
    +       +

+
+ +
    +

    Single Read Waveform

          +

      +

       
       +

    +

    +The waveform above shows the timing generated by the GPIF engine for the Single Read waveform as defined by the GPIF tool. All the essential signals + are presented here, including GSTATE[2:0], which displays the states the GPIF engine cycles through as it performs the Single Read transaction.

    As expected from the GPIF tool output, S0 asserts CTL1 (connected to the external FIFO's REN/ line), S1 asserts CTL2 (connected to the external + FIFO's OE/ line), and S2 samples the data bus (PORTB is FD[7:0] and PORTD is FD[15:8]). This effectively reads the 16-bit data value into the + external FIFO. Note here that enough data setup time to the rising edge of IFCLK is provided, since the minimum data setup time for the external + FIFO is 4 ns (see CY4265 datasheet). S2 is a decision point state that unconditionally branches to the IDLE state to terminate the transaction. + Without the unconditional branch, the GPIF engine would sequentially move through the remaining states until the IDLE state (S7) is reached.
    +
    + For every word read out from the external FIFO in a bulk IN transfer, the user should see the GPIF engine cycle through S0, S1, S2, and S7. To + capture the waveform, the user should trigger the logic analyzer on the falling edge of CTL1. A sampling rate of 4 ns will give the user the same + resolution shown in the waveform above.
    +     +

+ +
+

 

+
+

 

+
+

 

+
+

 

+
+

 

+
+

 

+
+ + + + diff --git a/doc/GPIF/GPIF Designer/fifo/app_note/images/BlkDiag2.gif b/doc/GPIF/GPIF Designer/fifo/app_note/images/BlkDiag2.gif new file mode 100644 index 0000000..2166952 Binary files /dev/null and b/doc/GPIF/GPIF Designer/fifo/app_note/images/BlkDiag2.gif differ diff --git a/doc/GPIF/GPIF Designer/fifo/app_note/images/FifoWr.gif b/doc/GPIF/GPIF Designer/fifo/app_note/images/FifoWr.gif new file mode 100644 index 0000000..568a685 Binary files /dev/null and b/doc/GPIF/GPIF Designer/fifo/app_note/images/FifoWr.gif differ diff --git a/doc/GPIF/GPIF Designer/fifo/app_note/images/SingleBlkDiag.gif b/doc/GPIF/GPIF Designer/fifo/app_note/images/SingleBlkDiag.gif new file mode 100644 index 0000000..07c495e Binary files /dev/null and b/doc/GPIF/GPIF Designer/fifo/app_note/images/SingleBlkDiag.gif differ diff --git a/doc/GPIF/GPIF Designer/fifo/app_note/images/bulkexe.gif b/doc/GPIF/GPIF Designer/fifo/app_note/images/bulkexe.gif new file mode 100644 index 0000000..947c721 Binary files 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+

16-bit Interface to External Synchronous Cypress FIFO CY7C4625-15AC
 +
+

+ Overview  +
+ +

+ The end objective of this example is to be able to perform a bulk loop back function with the external FIFO. The FX2 will write data + out FD[15:0] to the external FIFO and read data back from FD[15:0] (the outputs from the external FIFO Q[15:0] are also connected to FD[15:0]). The bulk + transfers can be exercised by using the EZ-USB Control Panel or bulkloop.exe utility supplied with the EZ-USB development kit software.
+
+ +

+ Hardware + Connections +
+ +

+ This section discusses the definition of the GPIF interconnect which is shown below in Figure 4-1.
+ +

+ +
+
+ Figure 4-1. GPIF Interconnect Diagram
+
+ +
+
    +

    IFCLK ----> WCLK, RCLK +
    IFCLK is connected to the write and read clock inputs (WCLK, + RCLK) of the external FIFO. Data is clocked into the external FIFO + on every rising edge of WCLK while WEN/ is asserted. Likewise, new + data is presented on Q[15:0] on every rising edge of RCLK while + REN/ and OE/ are asserted. The external FIFO can accept an input + clock frequency of up to 66.7Mhz so it can handle the incoming IFCLK + frequency (either 30MHz or 48MHz).     
          +

    + +
+
+
    +

    FD[15:0] <----> D[15:0] + Q[15:0]
    The GPIF data bus (FD[15:0]) is connected to the + external FIFO&rsquo;s input data bus (D[15:0]) to allow for + word wide operations. The output data bus of the external FIFO (Q[15:0]) + is also connected to the GPIF data bus to allow the FX2 to read + back the data contents. In order to ensure that bus contention will + never occur, the OE/ signal must be manipulated appropriately.
     

    + +
+
+
    +

    CTL0 ----> WEN
    CTL0 + is connected to the write enable line (WEN/) of the external FIFO. + While WEN/ is held low, data is written into the external FIFO on + every rising edge of WCLK.
     

    + +
+
+
    +

    CTL1 ----> REN
    CTL1 + is connected to the read enable line (REN/) of the external FIFO. + While REN/ and OE/ are held low, new data is presented on Q[15:0] + on every rising edge of RCLK.
     

    + +
+
+
    +

    CTL2 ----> OE
    CTL2 + is connected to the output enable line (OE/) of the external FIFO. + While REN/ and OE/ are held low, new data is presented on Q[15:0] + on every rising edge of RCLK.
     

    + +
+
+
    +

    RDY0 <---- EF
    RDY0 + is connected to the empty flag (EF/) of the external FIFO. EF/ is + asserted low if the external FIFO is empty. The GPIF can use this + to regulate data transfers when reading from the external FIFO.
     

    + +
+
+
    +

    RDY1 <---- FF
    RDY1 + is connected to the full flag (FF/) of the external FIFO. FF/ is + asserted low if the external FIFO is full. The GPIF can use this + to regulate data transfers when writing to the external FIFO.
     

    + +
+
+
    +

    PA2 ----> RS
    PA2 is + connected to the reset signal of the external FIFO. PA2 is not part + of the GPIF interconnect but is still part of the overall system + design. PA2 is used as an I/O pin to reset the external FIFO to + a known state before GPIF data transfers commence.

    + +

    The GPIF Designer + block diagram for the single transaction portion of the FIFO design example is shown below.

    +

    +
+ + +

 

+
+

The assignment of CTLx and RDYn + lines is optimized for the FX2 56-pin package. The CTLx lines are + used as input strobes into the external FIFO, and the status outputs + from the external FIFO (EF and FF) are used to monitor under run + and over run conditions. The basic rule of thumb is: one should + never read from an empty FIFO or write to a full FIFO.

The external FIFO was mounted onto an FX2 development board by using the prototype board supplied with the development + kit. The external FIFO was placed on a 64-pin TQFP package surface mount adapter (available from Twin Industries at + www.twinhunter.com) and piggybacked on top of the prototype board. Figure 9 shows a snapshot of the actual hardware setup. + For full hardware specifications on the external FIFO, its datasheet can be downloaded from the Cypress website. For a pin-out + list for the prototype board connection to the FX2 development board and a full schematic for the external FIFO prototype board, + see the software contents available with this primer.

+

+

Figure 9. Shot of Actual Hardware Setup

 

+ +
+ Application-specific Data Flow
+ + +
+ +

+ Now that the GPIF interconnect has been presented, it's important to understand the overall data flow for this design example. + Endpoint 2 OUT (EP2OUT) is used as the source endpoint for GPIF writes to the external FIFO, and Endpoint 6 IN (EP6IN) is used as the sink endpoint for + GPIF reads from the external FIFO. Remember that the IN and OUT directions are USB host-centric, therefore EP2OUT contains the data packets sent by the + USB host (in this case the PC) and EP6IN contains the data packets sent to the USB host. Figures 4-2 and 4-3 show the data flow models for this + particular example.
+
+ +

+ +
+
+ Figure 4-2. Data Flow Model in the OUT direction +
+
+
+ Figure 4-3. Data Flow Model in the IN direction + +

 

+ +
+
    +Manual mode versus Auto mode
     +
+ +
+
    + +

    + FX2 endpoints can basically operate in two modes, Manual (AUTOIN/AUTOOUT=0) or Auto (AUTOIN/AUTOOUT=1). In short, manual mode + makes the CPU responsible for committing the USB packet to the peripheral domain and vice versa. In order to maximize the USB 2.0 bandwidth, auto mode + should be used. This allows USB packets to be committed automatically to the peripheral domain and vice versa by removing the CPU from the data path. + This example demonstrates the use of auto mode.

          +

+ +
+
    +Two examples in one
     +
+ +
+
    + +

    + The FIFO example is really two examples in one because two versions of the firmware are discussed. Sections 4.1.4-4.1.6 present + a version that uses GPIF single transactions to read and write to the external FIFO, which then sets the stage for Sections 4.1.7-4.1.9. Sections + 4.1.7-4.1.9 discuss a version that uses GPIF FIFO transactions and the endpoints in auto mode, thus maximizing the USB 2.0 bandwidth. This two-phased + approach is in line with the methodology presented in section 3.3, and by understanding the two approaches, the user should be able to discern what it + takes to move from a simple working example to an example that utilizes the full USB 2.0 bandwidth capabilities of the FX2.

          +

+ +
+

 

+ +
+
    +

     

    +
+ +
+

 

+ +
+

 

+ +
+

 

+ +
+ + + diff --git a/doc/GPIF/GPIF Designer/fifo/app_note/mainmenu.htm b/doc/GPIF/GPIF Designer/fifo/app_note/mainmenu.htm new file mode 100644 index 0000000..7136651 --- /dev/null +++ b/doc/GPIF/GPIF Designer/fifo/app_note/mainmenu.htm @@ -0,0 +1,41 @@ + + + +Contents + + + +

Overview
+    Hardware Connections
   App-specific +Data Flow

Single +Transactions
    Waveform Descriptors
    Firmware
       FW +Files
        TD_Init() +function
       IFCONFIG +Register
       Trigger +Transaction
       TD_Poll() +function
   Running the example
+       Step +1: Download FW
       Step +2: Initiate Bulk IN
       Step +3: Finish Bulk IN
   Logic +Analyzer Traces

FIFO +(multi) Transactions
    Flow +States
    Waveform +Descriptors
    Firmware
        Trigger +Transaction
       TD_Init() +function
       TD_Poll() +function
   Running the +example   
   Logic +Analyzer Traces
       FIFO +WR: Front Porch
       FIFO +WR: Back Porch
       FIFO +WR: 512 Xfer time
        FIFO +WR: Pkt Xfer time        FIFO +RD: Front Porch
       FIFO +RD: Back Porch
       FIFO +RD: 512 Xfer time
       FIFO +RD: Pkt Xfer time
       Bulk +Loopback

+ + + diff --git a/doc/GPIF/GPIF Designer/fifo/dscr.a51 b/doc/GPIF/GPIF Designer/fifo/dscr.a51 new file mode 100644 index 0000000..8c63db2 --- /dev/null +++ b/doc/GPIF/GPIF Designer/fifo/dscr.a51 @@ -0,0 +1,234 @@ +;;----------------------------------------------------------------------------- +;; File: dscr.a51 +;; Contents: This file contains descriptor data tables. +;; +;; Copyright (c) 2003 Cypress Semiconductor, Inc. All rights reserved +;;----------------------------------------------------------------------------- + +DSCR_DEVICE equ 1 ;; Descriptor type: Device +DSCR_CONFIG equ 2 ;; Descriptor type: Configuration +DSCR_STRING equ 3 ;; Descriptor type: String +DSCR_INTRFC equ 4 ;; Descriptor type: Interface +DSCR_ENDPNT equ 5 ;; Descriptor type: Endpoint +DSCR_DEVQUAL equ 6 ;; Descriptor type: Device Qualifier + +DSCR_DEVICE_LEN equ 18 +DSCR_CONFIG_LEN equ 9 +DSCR_INTRFC_LEN equ 9 +DSCR_ENDPNT_LEN equ 7 +DSCR_DEVQUAL_LEN equ 10 + +ET_CONTROL equ 0 ;; Endpoint type: Control +ET_ISO equ 1 ;; Endpoint type: Isochronous +ET_BULK equ 2 ;; Endpoint type: Bulk +ET_INT equ 3 ;; Endpoint type: Interrupt + +public DeviceDscr, DeviceQualDscr, HighSpeedConfigDscr, FullSpeedConfigDscr, StringDscr, UserDscr + +DSCR SEGMENT CODE PAGE + +;;----------------------------------------------------------------------------- +;; Global Variables +;;----------------------------------------------------------------------------- + rseg DSCR ;; locate the descriptor table in on-part memory. + +DeviceDscr: + db DSCR_DEVICE_LEN ;; Descriptor length + db DSCR_DEVICE ;; Decriptor type + dw 0002H ;; Specification Version (BCD) + db 00H ;; Device class + db 00H ;; Device sub-class + db 00H ;; Device sub-sub-class + db 64 ;; Maximum packet size + dw 4705H ;; Vendor ID + dw 0210H ;; Product ID (Sample Device) + dw 0000H ;; Product version ID + db 1 ;; Manufacturer string index + db 2 ;; Product string index + db 0 ;; Serial number string index + db 1 ;; Number of configurations + +DeviceQualDscr: + db DSCR_DEVQUAL_LEN ;; Descriptor length + db DSCR_DEVQUAL ;; Decriptor type + dw 0002H ;; Specification Version (BCD) + db 00H ;; Device class + db 00H ;; Device sub-class + db 00H ;; Device sub-sub-class + db 64 ;; Maximum packet size + db 1 ;; Number of configurations + db 0 ;; Reserved + +HighSpeedConfigDscr: + db DSCR_CONFIG_LEN ;; Descriptor length + db DSCR_CONFIG ;; Descriptor type + db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) mod 256 ;; Total Length (LSB) + db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) / 256 ;; Total Length (MSB) + db 1 ;; Number of interfaces + db 1 ;; Configuration number + db 0 ;; Configuration string + db 10000000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu) + db 50 ;; Power requirement (div 2 ma) + +;; Interface Descriptor + db DSCR_INTRFC_LEN ;; Descriptor length + db DSCR_INTRFC ;; Descriptor type + db 0 ;; Zero-based index of this interface + db 0 ;; Alternate setting + db 2 ;; Number of end points + db 0ffH ;; Interface class + db 00H ;; Interface sub class + db 00H ;; Interface sub sub class + db 0 ;; Interface descriptor string index + +;; Endpoint Descriptor + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 02H ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 00H ;; Maximum packet size (LSB) + db 02H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + + +;; Endpoint Descriptor + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 86H ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 00H ;; Maximum packet size (LSB) + db 02H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + +HighSpeedConfigDscrEnd: + +FullSpeedConfigDscr: + db DSCR_CONFIG_LEN ;; Descriptor length + db DSCR_CONFIG ;; Descriptor type + db (FullSpeedConfigDscrEnd-FullSpeedConfigDscr) mod 256 ;; Total Length (LSB) + db (FullSpeedConfigDscrEnd-FullSpeedConfigDscr) / 256 ;; Total Length (MSB) + db 1 ;; Number of interfaces + db 1 ;; Configuration number + db 0 ;; Configuration string + db 10000000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu) + db 50 ;; Power requirement (div 2 ma) + +;; Interface Descriptor + db DSCR_INTRFC_LEN ;; Descriptor length + db DSCR_INTRFC ;; Descriptor type + db 0 ;; Zero-based index of this interface + db 0 ;; Alternate setting + db 2 ;; Number of end points + db 0ffH ;; Interface class + db 00H ;; Interface sub class + db 00H ;; Interface sub sub class + db 0 ;; Interface descriptor string index + +;; Endpoint Descriptor + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 02H ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 40H ;; Maximum packet size (LSB) + db 00H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + +;; Endpoint Descriptor + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 86H ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 40H ;; Maximum packet size (LSB) + db 00H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + +FullSpeedConfigDscrEnd: + +StringDscr: + +StringDscr0: + db StringDscr0End-StringDscr0 ;; String descriptor length + db DSCR_STRING + db 09H,04H +StringDscr0End: + +StringDscr1: + db StringDscr1End-StringDscr1 ;; String descriptor length + db DSCR_STRING + db 'C',00 + db 'y',00 + db 'p',00 + db 'r',00 + db 'e',00 + db 's',00 + db 's',00 +StringDscr1End: + +StringDscr2: + db StringDscr2End-StringDscr2 ;; Descriptor length + db DSCR_STRING + db 'E',00 + db 'Z',00 + db '-',00 + db 'U',00 + db 'S',00 + db 'B',00 + db ' ',00 + db 'F',00 + db 'X',00 + db '2',00 + db ' ',00 + db 'G',00 + db 'P',00 + db 'I',00 + db 'F',00 + db ' ',00 + db 't',00 + db 'o',00 + db ' ',00 + db 'E',00 + db 'x',00 + db 't',00 + db ' ',00 + db 'F',00 + db 'I',00 + db 'F',00 + db 'O',00 + db ' ',00 + db 'E',00 + db 'x',00 + db 'a',00 + db 'm',00 + db 'p',00 + db 'l',00 + db 'e',00 + db ' ',00 + db 'u',00 + db 's',00 + db 'i',00 + db 'n',00 + db 'g',00 + db ' ',00 + db 'F',00 + db 'I',00 + db 'F',00 + db 'O',00 + db ' ',00 + db 'T',00 + db 'r',00 + db 'a',00 + db 'n',00 + db 's',00 + db 'a',00 + db 'c',00 + db 't',00 + db 'i',00 + db 'o',00 + db 'n',00 + db 's',00 +StringDscr2End: + +UserDscr: + dw 0000H + end + diff --git a/doc/GPIF/GPIF Designer/fifo/fw.c b/doc/GPIF/GPIF Designer/fifo/fw.c new file mode 100644 index 0000000..85b8742 --- /dev/null +++ b/doc/GPIF/GPIF Designer/fifo/fw.c @@ -0,0 +1,366 @@ +//----------------------------------------------------------------------------- +// File: fw.c +// Contents: Firmware frameworks task dispatcher and device request parser +// source. +// +// indent 3. NO TABS! +// +// $Revision: 17 $ +// $Date: 11/15/01 5:45p $ +// +// Copyright (c) 2003 Cypress Semiconductor, Inc. All rights reserved +//----------------------------------------------------------------------------- +#include "fx2.h" +#include "fx2regs.h" + +//----------------------------------------------------------------------------- +// Constants +//----------------------------------------------------------------------------- +#define DELAY_COUNT 0x9248*8L // Delay for 8 sec at 24Mhz, 4 sec at 48 +#define _IFREQ 48000 // IFCLK constant for Synchronization Delay +#define _CFREQ 48000 // CLKOUT constant for Synchronization Delay + +//----------------------------------------------------------------------------- +// Random Macros +//----------------------------------------------------------------------------- +#define min(a,b) (((a)<(b))?(a):(b)) +#define max(a,b) (((a)>(b))?(a):(b)) + + // Registers which require a synchronization delay, see section 15.14 + // FIFORESET FIFOPINPOLAR + // INPKTEND OUTPKTEND + // EPxBCH:L REVCTL + // GPIFTCB3 GPIFTCB2 + // GPIFTCB1 GPIFTCB0 + // EPxFIFOPFH:L EPxAUTOINLENH:L + // EPxFIFOCFG EPxGPIFFLGSEL + // PINFLAGSxx EPxFIFOIRQ + // EPxFIFOIE GPIFIRQ + // GPIFIE GPIFADRH:L + // UDMACRCH:L EPxGPIFTRIG + // GPIFTRIG + + // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well... + // ...these have been replaced by GPIFTC[B3:B0] registers + +#include "fx2sdly.h" // Define _IFREQ and _CFREQ above this #include + +//----------------------------------------------------------------------------- +// Global Variables +//----------------------------------------------------------------------------- +volatile BOOL GotSUD; +BOOL Rwuen; +BOOL Selfpwr; +volatile BOOL Sleep; // Sleep mode enable flag + +WORD pDeviceDscr; // Pointer to Device Descriptor; Descriptors may be moved +WORD pDeviceQualDscr; +WORD pHighSpeedConfigDscr; +WORD pFullSpeedConfigDscr; +WORD pConfigDscr; +WORD pOtherConfigDscr; +WORD pStringDscr; + +//----------------------------------------------------------------------------- +// Prototypes +//----------------------------------------------------------------------------- +void SetupCommand(void); +void TD_Init(void); +void TD_Poll(void); +BOOL TD_Suspend(void); +BOOL TD_Resume(void); + +BOOL DR_GetDescriptor(void); +BOOL DR_SetConfiguration(void); +BOOL DR_GetConfiguration(void); +BOOL DR_SetInterface(void); +BOOL DR_GetInterface(void); +BOOL DR_GetStatus(void); +BOOL DR_ClearFeature(void); +BOOL DR_SetFeature(void); +BOOL DR_VendorCmnd(void); + +// this table is used by the epcs macro +const char code EPCS_Offset_Lookup_Table[] = +{ + 0, // EP1OUT + 1, // EP1IN + 2, // EP2OUT + 2, // EP2IN + 3, // EP4OUT + 3, // EP4IN + 4, // EP6OUT + 4, // EP6IN + 5, // EP8OUT + 5, // EP8IN +}; + +// macro for generating the address of an endpoint's control and status register (EPnCS) +#define epcs(EP) (EPCS_Offset_Lookup_Table[(EP & 0x7E) | (EP > 128)] + 0xE6A1) + +//----------------------------------------------------------------------------- +// Code +//----------------------------------------------------------------------------- + +// Task dispatcher +void main(void) +{ + DWORD i; + WORD offset; + DWORD DevDescrLen; + DWORD j=0; + WORD IntDescrAddr; + WORD ExtDescrAddr; + + // Initialize Global States + Sleep = FALSE; // Disable sleep mode + Rwuen = FALSE; // Disable remote wakeup + Selfpwr = FALSE; // Disable self powered + GotSUD = FALSE; // Clear "Got setup data" flag + + // Initialize user device + TD_Init(); + + // The following section of code is used to relocate the descriptor table. + // Since the SUDPTRH and SUDPTRL are assigned the address of the descriptor + // table, the descriptor table must be located in on-part memory. + // The 4K demo tools locate all code sections in external memory. + // The descriptor table is relocated by the frameworks ONLY if it is found + // to be located in external memory. + pDeviceDscr = (WORD)&DeviceDscr; + pDeviceQualDscr = (WORD)&DeviceQualDscr; + pHighSpeedConfigDscr = (WORD)&HighSpeedConfigDscr; + pFullSpeedConfigDscr = (WORD)&FullSpeedConfigDscr; + pStringDscr = (WORD)&StringDscr; + + if (EZUSB_HIGHSPEED()) + { + pConfigDscr = pHighSpeedConfigDscr; + pOtherConfigDscr = pFullSpeedConfigDscr; + } + else + { + pConfigDscr = pFullSpeedConfigDscr; + pOtherConfigDscr = pHighSpeedConfigDscr; + } + + if ((WORD)&DeviceDscr & 0xe000) + { + IntDescrAddr = INTERNAL_DSCR_ADDR; + ExtDescrAddr = (WORD)&DeviceDscr; + DevDescrLen = (WORD)&UserDscr - (WORD)&DeviceDscr + 2; + for (i = 0; i < DevDescrLen; i++) + *((BYTE xdata *)IntDescrAddr+i) = 0xCD; + for (i = 0; i < DevDescrLen; i++) + *((BYTE xdata *)IntDescrAddr+i) = *((BYTE xdata *)ExtDescrAddr+i); + pDeviceDscr = IntDescrAddr; + offset = (WORD)&DeviceDscr - INTERNAL_DSCR_ADDR; + pDeviceQualDscr -= offset; + pConfigDscr -= offset; + pOtherConfigDscr -= offset; + pHighSpeedConfigDscr -= offset; + pFullSpeedConfigDscr -= offset; + pStringDscr -= offset; + } + + EZUSB_IRQ_ENABLE(); // Enable USB interrupt (INT2) + EZUSB_ENABLE_RSMIRQ(); // Wake-up interrupt + + INTSETUP |= (bmAV2EN | bmAV4EN); // Enable INT 2 & 4 autovectoring + + USBIE |= bmSUDAV | bmSUTOK | bmSUSP | bmURES | bmHSGRANT; // Enable selected interrupts + EA = 1; // Enable 8051 interrupts + +#ifndef NO_RENUM + // Renumerate if necessary. Do this by checking the renum bit. If it + // is already set, there is no need to renumerate. The renum bit will + // already be set if this firmware was loaded from an eeprom. + if(!(USBCS & bmRENUM)) + { + EZUSB_Discon(TRUE); // renumerate + } +#endif + + // unconditionally re-connect. If we loaded from eeprom we are + // disconnected and need to connect. If we just renumerated this + // is not necessary but doesn't hurt anything + USBCS &=~bmDISCON; + + CKCON = (CKCON&(~bmSTRETCH)) | FW_STRETCH_VALUE; // Set stretch to 0 (after renumeration) + + // clear the Sleep flag. + Sleep = FALSE; + + // Task Dispatcher + while(TRUE) // Main Loop + { + if(GotSUD) // Wait for SUDAV + { + SetupCommand(); // Implement setup command + GotSUD = FALSE; // Clear SUDAV flag + } + + // Poll User Device + // NOTE: Idle mode stops the processor clock. There are only two + // ways out of idle mode, the WAKEUP pin, and detection of the USB + // resume state on the USB bus. The timers will stop and the + // processor will not wake up on any other interrupts. + if (Sleep) + { + if(TD_Suspend()) + { + Sleep = FALSE; // Clear the "go to sleep" flag. Do it here to prevent any race condition between wakeup and the next sleep. + do + { + EZUSB_Susp(); // Place processor in idle mode. + } + while(!Rwuen && EZUSB_EXTWAKEUP()); + // Must continue to go back into suspend if the host has disabled remote wakeup + // *and* the wakeup was caused by the external wakeup pin. + + // 8051 activity will resume here due to USB bus or Wakeup# pin activity. + EZUSB_Resume(); // If source is the Wakeup# pin, signal the host to Resume. + TD_Resume(); + } + } + TD_Poll(); + } +} + +// Device request parser +void SetupCommand(void) +{ + void *dscr_ptr; + + switch(SETUPDAT[1]) + { + case SC_GET_DESCRIPTOR: // *** Get Descriptor + if(DR_GetDescriptor()) + switch(SETUPDAT[3]) + { + case GD_DEVICE: // Device + SUDPTRH = MSB(pDeviceDscr); + SUDPTRL = LSB(pDeviceDscr); + break; + case GD_DEVICE_QUALIFIER: // Device Qualifier + SUDPTRH = MSB(pDeviceQualDscr); + SUDPTRL = LSB(pDeviceQualDscr); + break; + case GD_CONFIGURATION: // Configuration + SUDPTRH = MSB(pConfigDscr); + SUDPTRL = LSB(pConfigDscr); + break; + case GD_OTHER_SPEED_CONFIGURATION: // Other Speed Configuration + SUDPTRH = MSB(pOtherConfigDscr); + SUDPTRL = LSB(pOtherConfigDscr); + break; + case GD_STRING: // String + if(dscr_ptr = (void *)EZUSB_GetStringDscr(SETUPDAT[2])) + { + SUDPTRH = MSB(dscr_ptr); + SUDPTRL = LSB(dscr_ptr); + } + else + EZUSB_STALL_EP0(); // Stall End Point 0 + break; + default: // Invalid request + EZUSB_STALL_EP0(); // Stall End Point 0 + } + break; + case SC_GET_INTERFACE: // *** Get Interface + DR_GetInterface(); + break; + case SC_SET_INTERFACE: // *** Set Interface + DR_SetInterface(); + break; + case SC_SET_CONFIGURATION: // *** Set Configuration + DR_SetConfiguration(); + break; + case SC_GET_CONFIGURATION: // *** Get Configuration + DR_GetConfiguration(); + break; + case SC_GET_STATUS: // *** Get Status + if(DR_GetStatus()) + switch(SETUPDAT[0]) + { + case GS_DEVICE: // Device + EP0BUF[0] = ((BYTE)Rwuen << 1) | (BYTE)Selfpwr; + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + break; + case GS_INTERFACE: // Interface + EP0BUF[0] = 0; + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + break; + case GS_ENDPOINT: // End Point + EP0BUF[0] = *(BYTE xdata *) epcs(SETUPDAT[4]) & bmEPSTALL; + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + break; + default: // Invalid Command + EZUSB_STALL_EP0(); // Stall End Point 0 + } + break; + case SC_CLEAR_FEATURE: // *** Clear Feature + if(DR_ClearFeature()) + switch(SETUPDAT[0]) + { + case FT_DEVICE: // Device + if(SETUPDAT[2] == 1) + Rwuen = FALSE; // Disable Remote Wakeup + else + EZUSB_STALL_EP0(); // Stall End Point 0 + break; + case FT_ENDPOINT: // End Point + if(SETUPDAT[2] == 0) + { + *(BYTE xdata *) epcs(SETUPDAT[4]) &= ~bmEPSTALL; + EZUSB_RESET_DATA_TOGGLE( SETUPDAT[4] ); + } + else + EZUSB_STALL_EP0(); // Stall End Point 0 + break; + } + break; + case SC_SET_FEATURE: // *** Set Feature + if(DR_SetFeature()) + switch(SETUPDAT[0]) + { + case FT_DEVICE: // Device + if(SETUPDAT[2] == 1) + Rwuen = TRUE; // Enable Remote Wakeup + else if(SETUPDAT[2] == 2) + // Set Feature Test Mode. The core handles this request. However, it is + // necessary for the firmware to complete the handshake phase of the + // control transfer before the chip will enter test mode. It is also + // necessary for FX2 to be physically disconnected (D+ and D-) + // from the host before it will enter test mode. + break; + else + EZUSB_STALL_EP0(); // Stall End Point 0 + break; + case FT_ENDPOINT: // End Point + *(BYTE xdata *) epcs(SETUPDAT[4]) |= bmEPSTALL; + break; + } + break; + default: // *** Invalid Command + if(DR_VendorCmnd()) + EZUSB_STALL_EP0(); // Stall End Point 0 + } + + // Acknowledge handshake phase of device request + EP0CS |= bmHSNAK; +} + +// Wake-up interrupt handler +void resume_isr(void) interrupt WKUP_VECT +{ + EZUSB_CLEAR_RSMIRQ(); +} + + diff --git a/doc/GPIF/GPIF Designer/fifo/gpif.c b/doc/GPIF/GPIF Designer/fifo/gpif.c new file mode 100644 index 0000000..13c5ff4 --- /dev/null +++ b/doc/GPIF/GPIF Designer/fifo/gpif.c @@ -0,0 +1,292 @@ +// This program configures the General Programmable Interface (GPIF) for FX2. +// Please do not modify sections of text which are marked as "DO NOT EDIT ...". +// +// DO NOT EDIT ... +// GPIF Initialization +// Interface Timing Sync +// Internal Ready Init IntRdy=1 +// CTL Out Tristate-able Binary +// SingleWrite WF Select 1 +// SingleRead WF Select 0 +// FifoWrite WF Select 3 +// FifoRead WF Select 2 +// Data Bus Idle Drive Tristate +// END DO NOT EDIT + +// DO NOT EDIT ... +// GPIF Wave Names +// Wave 0 = unused +// Wave 1 = unused +// Wave 2 = FIFORd +// Wave 3 = FIFOWr + +// GPIF Ctrl Outputs Level +// CTL 0 = WEN# CMOS +// CTL 1 = REN# CMOS +// CTL 2 = OE# CMOS +// CTL 3 = unused CMOS +// CTL 4 = unused CMOS +// CTL 5 = unused CMOS + +// GPIF Rdy Inputs +// RDY0 = EF# +// RDY1 = FF# +// RDY2 = unused +// RDY3 = unused +// RDY4 = unused +// RDY5 = TCXpire +// FIFOFlag = FIFOFlag +// IntReady = IntReady +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 0: unused +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data +// NextData SameData SameData SameData SameData SameData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 +// Term A +// LFunc +// Term B +// Branch1 +// Branch0 +// Re-Exec +// Sngl/CRC Default Default Default Default Default Default Default +// WEN# 1 1 1 1 1 1 1 1 +// REN# 1 1 1 1 1 1 1 1 +// OE# 1 1 1 1 1 1 1 1 +// unused 0 0 0 0 0 0 0 0 +// unused 0 0 0 0 0 0 0 0 +// unused 0 0 0 0 0 0 0 0 +// +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 1: unused +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data +// NextData SameData SameData SameData SameData SameData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 +// Term A +// LFunc +// Term B +// Branch1 +// Branch0 +// Re-Exec +// Sngl/CRC Default Default Default Default Default Default Default +// WEN# 1 1 1 1 1 1 1 1 +// REN# 1 1 1 1 1 1 1 1 +// OE# 1 1 1 1 1 1 1 1 +// unused 0 0 0 0 0 0 0 0 +// unused 0 0 0 0 0 0 0 0 +// unused 0 0 0 0 0 0 0 0 +// +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 2: FIFORd +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data NO Data NO Data Activate Activate Activate Activate +// NextData SameData SameData SameData SameData SameData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 Wait 1 Wait 1 IF Wait 1 Wait 1 Wait 1 +// Term A TCXpire +// LFunc AND +// Term B TCXpire +// Branch1 ThenIdle +// Branch0 Else 3 +// Re-Exec No +// Sngl/CRC Default Default Default Default Default Default Default +// WEN# 1 1 1 1 1 1 1 1 +// REN# 1 0 0 1 1 1 1 1 +// OE# 1 1 0 1 1 1 1 1 +// unused 0 0 0 0 0 0 0 0 +// unused 0 0 0 0 0 0 0 0 +// unused 0 0 0 0 0 0 0 0 +// +// END DO NOT EDIT +// DO NOT EDIT ... +// +// GPIF Waveform 3: FIFOWr +// +// Interval 0 1 2 3 4 5 6 Idle (7) +// _________ _________ _________ _________ _________ _________ _________ _________ +// +// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val +// DataMode NO Data Activate Activate Activate Activate Activate Activate +// NextData SameData SameData SameData SameData SameData SameData SameData +// Int Trig No Int No Int No Int No Int No Int No Int No Int +// IF/Wait Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 +// Term A TCXpire +// LFunc AND +// Term B TCXpire +// Branch1 ThenIdle +// Branch0 Else 1 +// Re-Exec No +// Sngl/CRC Default Default Default Default Default Default Default +// WEN# 1 1 1 1 1 1 1 1 +// REN# 1 1 1 1 1 1 1 1 +// OE# 1 1 1 1 1 1 1 1 +// unused 0 0 0 0 0 0 0 0 +// unused 0 0 0 0 0 0 0 0 +// unused 0 0 0 0 0 0 0 0 +// +// END DO NOT EDIT + +// GPIF Program Code + +// DO NOT EDIT ... +#include "fx2.h" +#include "fx2regs.h" +#include "fx2sdly.h" // SYNCDELAY macro +// END DO NOT EDIT + +// DO NOT EDIT ... +const char xdata WaveData[128] = +{ +// Wave 0 +/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Output*/ 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, +/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, +// Wave 1 +/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* Output*/ 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, +/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, +// Wave 2 +/* LenBr */ 0x01, 0x01, 0x01, 0x3B, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x00, 0x00, 0x03, 0x02, 0x02, 0x02, 0x00, +/* Output*/ 0x07, 0x05, 0x01, 0x07, 0x07, 0x07, 0x07, 0x07, +/* LFun */ 0x00, 0x00, 0x00, 0x2D, 0x00, 0x00, 0x00, 0x3F, +// Wave 3 +/* LenBr */ 0x01, 0x39, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07, +/* Opcode*/ 0x00, 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00, +/* Output*/ 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, +/* LFun */ 0x00, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, +}; +// END DO NOT EDIT + +// DO NOT EDIT ... +const char xdata FlowStates[36] = +{ +/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +/* Wave 2 FlowStates */ 0x83,0x36,0x01,0x07,0x00,0x03,0x03,0x02,0x00, +/* Wave 3 FlowStates */ 0x81,0x36,0x06,0x07,0x00,0x03,0x03,0x02,0x00, +}; +// END DO NOT EDIT + +// DO NOT EDIT ... +const char xdata InitData[7] = +{ +/* Regs */ 0xE0,0x00,0x00,0x07,0xEE,0x4E,0x00 +}; +// END DO NOT EDIT + +// TO DO: You may add additional code below. + +void GpifInit( void ) +{ + BYTE i; + + // Registers which require a synchronization delay, see section 15.14 + // FIFORESET FIFOPINPOLAR + // INPKTEND OUTPKTEND + // EPxBCH:L REVCTL + // GPIFTCB3 GPIFTCB2 + // GPIFTCB1 GPIFTCB0 + // EPxFIFOPFH:L EPxAUTOINLENH:L + // EPxFIFOCFG EPxGPIFFLGSEL + // PINFLAGSxx EPxFIFOIRQ + // EPxFIFOIE GPIFIRQ + // GPIFIE GPIFADRH:L + // UDMACRCH:L EPxGPIFTRIG + // GPIFTRIG + + // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well... + // ...these have been replaced by GPIFTC[B3:B0] registers + + // 8051 doesn't have access to waveform memories 'til + // the part is in GPIF mode. + + IFCONFIG = 0xEE; + // IFCLKSRC=1 , FIFOs executes on internal clk source + // xMHz=1 , 48MHz internal clk rate + // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz + // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk + // ASYNC=1 , master samples asynchronous + // GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF + // IFCFG[1:0]=10, FX2 in GPIF master mode + + GPIFABORT = 0xFF; // abort any waveforms pending + + GPIFREADYCFG = InitData[ 0 ]; + GPIFCTLCFG = InitData[ 1 ]; + GPIFIDLECS = InitData[ 2 ]; + GPIFIDLECTL = InitData[ 3 ]; + GPIFWFSELECT = InitData[ 5 ]; + GPIFREADYSTAT = InitData[ 6 ]; + + // use dual autopointer feature... + AUTOPTRSETUP = 0x07; // inc both pointers, + // ...warning: this introduces pdata hole(s) + // ...at E67B (XAUTODAT1) and E67C (XAUTODAT2) + + // source + AUTOPTRH1 = MSB( &WaveData ); + AUTOPTRL1 = LSB( &WaveData ); + + // destination + AUTOPTRH2 = 0xE4; + AUTOPTRL2 = 0x00; + + // transfer + for ( i = 0x00; i < 128; i++ ) + { + EXTAUTODAT2 = EXTAUTODAT1; + } + +// Configure GPIF Address pins, output initial value, + PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0] + OEC = 0xFF; // and as outputs + PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8] + OEE |= 0x80; // and as output + +// ...OR... tri-state GPIFADR[8:0] pins +// PORTCCFG = 0x00; // [7:0] as port I/O +// OEC = 0x00; // and as inputs +// PORTECFG &= 0x7F; // [8] as port I/O +// OEE &= 0x7F; // and as input + +// GPIF address pins update when GPIFADRH/L written + SYNCDELAY; // + GPIFADRH = 0x00; // bits[7:1] always 0 + SYNCDELAY; // + GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000 + +// Configure GPIF FlowStates registers for Wave 0 of WaveData + FLOWSTATE = FlowStates[ 0 ]; + FLOWLOGIC = FlowStates[ 1 ]; + FLOWEQ0CTL = FlowStates[ 2 ]; + FLOWEQ1CTL = FlowStates[ 3 ]; + FLOWHOLDOFF = FlowStates[ 4 ]; + FLOWSTB = FlowStates[ 5 ]; + FLOWSTBEDGE = FlowStates[ 6 ]; + FLOWSTBHPERIOD = FlowStates[ 7 ]; +} + diff --git a/doc/GPIF/GPIF Designer/fifo/readme.txt b/doc/GPIF/GPIF Designer/fifo/readme.txt new file mode 100644 index 0000000..798430c --- /dev/null +++ b/doc/GPIF/GPIF Designer/fifo/readme.txt @@ -0,0 +1,5 @@ +readme.txt for FX2_to_extsyncFIFO GPIF FIFO Transactions Auto mode +------------------------------------------------------------------ + +see GPIF Primer section on design examples for operating instructions +and details \ No newline at end of file diff --git a/doc/GPIF/GPIF Designer/help/gpif_hlp.htm b/doc/GPIF/GPIF Designer/help/gpif_hlp.htm new file mode 100644 index 0000000..ec44f1a --- /dev/null +++ b/doc/GPIF/GPIF Designer/help/gpif_hlp.htm @@ -0,0 +1,21 @@ + + +You need a browser that supports frame to veiw this page. + + + + + + + + + + + +<body bgcolor="white" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> + +<p>You need a browser that supports frame to veiw this page.</p> +</body> + + + \ No newline at end of file diff --git a/doc/GPIF/GPIF Designer/help/gpif_hlp/Caption.htm b/doc/GPIF/GPIF Designer/help/gpif_hlp/Caption.htm new file mode 100644 index 0000000..d6c8804 --- /dev/null +++ b/doc/GPIF/GPIF Designer/help/gpif_hlp/Caption.htm @@ -0,0 +1,27 @@ + + + +Index + + + + + + + + + +
+

 

+ 		+

GPIF + User's + Guide

+ 		+

+
+
+

 

+ + + diff --git a/doc/GPIF/GPIF Designer/help/gpif_hlp/FX2UG.htm b/doc/GPIF/GPIF Designer/help/gpif_hlp/FX2UG.htm new file mode 100644 index 0000000..729e50c --- /dev/null +++ b/doc/GPIF/GPIF Designer/help/gpif_hlp/FX2UG.htm @@ -0,0 +1,144 @@ + + + + + GPIF + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

FX2 + Introduction/Overview
  +

+

EZ-USB FX2 offers a highly flexible and configurable Full Speed and High Speed USB peripheral function that's designed + to achieve the maximum USB 2.0 High Speed bandwidth. FX2 accomplishes this through its auto-transfer and peripheral interface architecture. + The GPIF (General Programmable InterFace) engine is one of the vehicles for the auto-transfer architecture, and is used to gluelessly move data + between FX2, your external slave device, and the USB host. The following sections briefly touch upon the silicon architecture and implementation + of FX2, and will lay the groundwork for understanding GPIF concepts discussed later on.
 +

 

+ + + +
+ Why an Auto-Transfer Architecture?
  + + +
+ +

+ In order to achieve the maximum USB 2.0 High Speed bandwidth, it was proven that the CPU (in this case an enhanced 8051 core) + should never be directly involved in moving the payload data from the external slave device to the USB host (and vice versa). The CPU would clearly be + the largest bottleneck in a High Speed design. So instead an Auto-Transfer mode was invented, whereby the payload data is "auto-committed" from the USB + host to the external slave device and likewise in the other direction. The GPIF engine uses this Auto-Transfer mode to move data to and from the external + slave device. Figures 1 and 2 show a system level view of the data flow for both the IN and OUT directions.

  +

+ +


+ Figure 1. System Level View of Data Flow in the OUT Direction
+
+
+ +

+ +


+ Figure 2. System Level View of Data Flow in the IN Direction +

 

+

 

+ +
+ + Silicon features that facilitate the Auto-Transfer Architecture
  + + +
+
    + +

    + Endpoint FIFOs

    In FX2 the USB endpoints share the same physical memory as the FIFO buffers. This is the very backbone of what allows + the Auto-Transfer mechanism to work. Anytime the USB host sends a packet of data the packet is stuffed into an available Endpoint FIFO buffer + (the multiple buffering schemes available allows FX2 to accept up to 4 packets before NAKing the host). The data packet is then ready to be + distributed to the external device. Conversely, a data packet read from the external device can be automatically made available to the USB host. + FX2 can be configured to allow the CPU to manually "commit" the data packets (called Manual Mode) or allow the data packets to be committed + automatically (called Auto Mode) to either the USB or peripheral domain. Figures 3 and 4 show the maximum buffering scheme (4x) in relation to + the overall data path the data packets follow.
          +

+ +
+ +


+
+ Figure 3. Auto-Transfer Dataflow in the OUT direction
+



 

+ +
+ +


+ Figure 4. Auto-Transfer Dataflow in the IN direction

 

+ + + +
+
    +The CPU is the Traffic Cop

    The CPU in FX2 has a minor role in the Auto-Transfer architecture as it does not participate in moving the payload data, + but it does play a very important role nonetheless. The CPU configures and defines how the physical interface operates, sets up the endpoint + configurations, triggers GPIF transfers, and can be allowed to manually commit the data packets to either the USB or peripheral domain. It + can also monitor the status of the external world, thus giving it the capability of regulating GPIF transfers.
          +
+ + + +
+

 

+ + + +
+ + + + diff --git a/doc/GPIF/GPIF Designer/help/gpif_hlp/GenGPIF.htm b/doc/GPIF/GPIF Designer/help/gpif_hlp/GenGPIF.htm new file mode 100644 index 0000000..8ad0904 --- /dev/null +++ b/doc/GPIF/GPIF Designer/help/gpif_hlp/GenGPIF.htm @@ -0,0 +1,432 @@ + + + + + GPIF + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ GPIF Overview
  +
+ +

+ This section introduces the GPIF feature from a hardware standpoint and discusses how to design with GPIF from the ground up. + As the name suggests, the physical connection or interface to the external peripheral is highly configurable. This allows FX2 to become the solution + for 99.9 percent of the parallel interfaces that exist. With the ability to run the physical interface at a maximum rate of 48MHz in 16-bit mode, the + bottleneck in a USB 2.0 system should never be the actual GPIF interconnect itself. One of the objectives of this primer is to guide users down a path + to get the most out of their GPIF designs in terms of performance over the physical interface. Thus, the general thought process for implementing + successful GPIF designs is also discussed, allowing the user to understand and use a design flow methodology for current and future GPIF + implementations. Debugging strategies are provided in Appendix A to guide the user on what the best approaches are for tackling GPIF design problems.
+
The GPIF (General Programmable InterFace) is a key feature of FX2 used to master an external peripheral without any external + glue logic. The GPIF is basically a controllable state machine that allows the user to generate waveforms required by external peripheral read/write + cycle timing. The CPU's role is minimal; as it basically only has to load the micro code that defines the waveform behaviors into designated FX2 on-chip + RAM space, and manages how they are executed in the application firmware.
+   +

+

 

+ +
+Physical Interconnect
+
+ The GPIF has an interconnect which features a configurable 8- or 16-bit data bus, control outputs, and ready inputs. + Figure 5 shows what signals are available to users when they are trying to figure out how to "connect the dots" to their external peripheral.
+
+ +



+ Figure 5. GPIF Interconnect Diagram

+ +

IFCLK (bi-directional)
IFCLK + can be either an input or output signal and is determined by what + the system requirements are. As an output signal, IFCLK can be driven + by the FX2 at either 30 MHz or 48 MHz. As an input signal, its range + is from 5-48MHz. If an external IFCLK is used in the design, it + becomes the reference clock for all GPIF operations. Note that the + GPIF can also run on an internal 30 or 48 MHz clock.
 

+
+ +

GPIFADR[8:0] (output only)
GPIF + can use GPIFADR[8:0] to provide address lines for peripherals that + need them. These are output only signals and the value presented + on this bus can be auto-incremented.
 

+
+ +

FD[15:0] (bi-directional)
This + is the data bus used by GPIF operations and is the conduit for payload + data transferred between FX2 and the external peripheral. It can + be configured to operate as an 8- or 16-bit interface and can be + tri-stated if the system requires it. FD[7:0] represents the least + significant byte (LSB) and FD[15:8] represents the most significant + byte (MSB).
 

+
+ +

CTL[5:0] (output only)
These + are control output signals that can be used to provide signals required + by the external peripheral such as read/write strobes, enables, + etc.
 

+
+ +

RDY[5:0] (input only)
These + are ready input signals that can be used to monitor status outputs + from the external peripheral such as FIFO status flags, data available, + etc. GPIF has the ability to use these signals as decision point + qualifiers for wait-state generation.
 

+
+ +

GSTATE[2:0] (output only)
These + are debug output signals that represent the states executed in a + GPIF waveform. These are typically connected to a debug port such + as a logic analyzer.

+

 

+
+ + Application Design Flow Methodology (ADFM) 
+ +

+The following section presents a design flow methodology for GPIF developers wishing to maximize their "first time success" + experience. Although following this methodology may not completely guarantee a 100 per cent success rate, it will definitely give developers the + right tools for embarking on a systematic GPIF design approach, which more often than not translates into eventual success. The design examples + that are discussed later on in this primer will often refer back to these design principles.
+
 

+ +
    +Design GPIF Interconnect
     +
+
+ +
    + +

    +Using section 3.2, you should have a pretty good basis for determining how FX2 is going to be connected up to your peripheral + device using GPIF. This is also a good time to start collecting the FX2 datasheet and Technical Reference Manual, as well as the peripheral's datasheet + as a minimum. You can then start by asking yourself the following questions:
     +

+ +
+
    +
  • Is the data path going to be 8- or 16-bit? +
      +
    • This decision is often dictated by what size data path the peripheral offers. If it has a 16-bit data path, use it to maximize the bandwidth over the physical interface. +
    • Endianness and bit nomenclature may also come into play here so watch how those lines are wired. +
    +
    +
  • Will an external IFCLK be used or an internal 30 or 48 MHz clock source? +
      +
    • This decision is often made based on how flexible the peripheral is in terms of its own operating modes. For example, if it can accept a 30 or 48 + MHz clock input then there's a good chance the internal 30 or 48 MHz clock source can be used to serve as the clock input for the slave device.
             Does the peripheral require any address lines during its read/write cycles? +
    + + + +
      +
    • If the peripheral requires any lines to be addressed during a read/write cycle operation, then GPIFADR[8:0] can be used. +
    +
    + +
  • How many control lines does the peripheral need? +
      +
    • Designate GPIF control outputs from your choice of CTL[5:0]. The peripheral may require read/write signals, chip selects, among other control + inputs during a read/write cycle. Determine what they are and allocate CTL[5:0] appropriately. +
    +
    + +
  • How many inputs does the GPIF need to monitor from the peripheral? +
      +
    • Determining how many status signals need to be monitored during a read/write cycle usually makes this decision. Determine what they are and allocate RDY[5:0] appropriately.
              +
    +
+
+
+ +
    +
      +

      Note: Not all FX2 package types have the complete set of GPIF signals available so the designer has to be mindful of this when determining the GPIF + interconnect. The designer also needs to consider what other signals may be used (such as port I/O) to interface the FX2 to the peripheral (e.g. reset + signals, other address lines, etc.). For instance, the 56-pin package type does not bring out GPIFADR[8:0]. Therefore, if the peripheral needs some sort + of address scheme before a GPIF read/write cycle is initiated, port I/O pins must be used instead (See TI-DSP example for more details).
      +
       

      +
    +
+ +
+ +
    +Use Firmware Frameworks  +
+
+ +
    +

    Before embarking on any firmware project, let alone a GPIF one, it is recommended to start with a firmware frameworks based Keil + uVision2 project. Not only will this ensure that the integration and test phase will be smoother, it will also help USB applications support know that + you're starting from a well-known and well-tested firmware base. Any of our firmware examples will be frameworks based so you can start with one of + those, or start by copying the contents of C:\Cypress\Usb\Target\Fw\FX2 to a new sub-directory. This will allow you to start with a "clean" firmware + base. Starting with a firmware frameworks project also allows you to concentrate on the user application code as the USB protocol servicing has been + handled already (see the file called fw.c and the development kit documentation for more details).
      +

    +
+ +
+ +
    + +

    +There are basically two major portions to a complete GPIF applications solution: +

    a) + The higher-level firmware that configures the GPIF and launches the transfers (including the rest of the user application code). +  

    b) The GPIF waveform descriptors that implement the physical bus timing.

    Part a) normally consists of five main files (fw.c, periph.c (user can rename this file), dscr.a51, ezusb.lib, usbjmptb.obj) which makes up the Keil + uVision 2 firmware frameworks project.

    Part b) is typically a self-contained source file that contains the GPIF waveform descriptors and is added to the + Keil project. The GPIF Designer a user mode application supplied with the development kit software, exports + this "C" language source file.
    +      

    +
+
+ +
    +Implement GPIF Waveforms Descriptors using GPIF Designer
     +
+
+ +
    +


    As mentioned above, GPIF Designer generates the GPIF waveform descriptors that implement the physical bus timing.    GPIF Designer + can implement any of four waveform types: Single Write, Single Read, FIFO Write, and FIFO Read. Each descriptor is 32 bytes long and resides in a + special GPIF waveform descriptor area in on-chip memory space, once loaded by the CPU.

    It is ultimately the developer's responsibility to create these GPIF waveform descriptors that will, in turn, trigger single or FIFO read/write transactions + to the peripheral. The developer has seven states or intervals (S0-S6) to work with before having to terminate the transaction naturally by branching to a + "special" IDLE state (S7) (Figure 6 shows an example of a simple waveform broken down into the GPIF state transitions). Once the GPIF waveforms are ready + to be exercised by the CPU, the reading or writing of specific GPIF "trigger" registers determine at any one time which of the four waveform types get + executed by the GPIF engine.
    + +

    +
+ +
+ +
    +


     
    +         Figure 6. Illustrating a simple waveform broken down into GPIF states
      +

    +
+ +
+ +
    +

    The usage details of the GPIF Designer + tool will become clear in the discussion of the two design examples. It is important to note at + this point that the first set of waveforms the user should implement is the single read/write transaction waveforms. This will allow the user to flesh-out the physical interconnect and get data moving back and forth between the USB host, FX2, the peripheral, and back. It's always wise to start by + implementing single read/write waveforms before leaping into the more conceptually difficult FIFO read/write transactions, because getting comfortable + with GPIF and that first confidence booster is essential to a successful design. It may sound like starting with single transactions is a waste of time, + but taking the time to absorb the learning curve up front will pay large dividends in the end.
     

    +
+ +
+ +
    +

    +Implement Single Read/Write transactions +

+
+ +
    + +

    +The main goal of implementing single read/write transactions is to be able to confirm that the physical interconnect is sound + between GPIF and the peripheral, and that basic data movement can be achieved in the final system. It is possible to get an entire design working even + if only single transactions are utilized. Another advantage of performing this stage first in the GPIF development cycle is that all areas of the system + (hardware, firmware, software) can be verified within a relatively short period of time (compared to jumping into FIFO transactions first). Especially + for first time users learning about the GPIF, this is a heavily recommended development stage to go through. +  

    Even though single transactions are the easiest of GPIF waveforms to implement, it may take several iterations of integration + and test of the GAS project before the user is happy with the initial design, since this stage can be also considered as the "fleshing out" stage. There + may be hardware-timing issues that pop up, hardware connection issues, firmware code flow issues, driver issues, etc., but this is the right time to + become aware of these types of issues in order not to get burned too much later on if a problem arises.
          +

+
+
    +Implement FIFO Read/Write Transactions
     +
+ +
+
    + +

    + Once the user is satisfied with the single transaction implementation, the next logical step is to implement GPIF FIFO + Read/Write transactions to achieve higher bandwidth numbers. This development stage is a two-phase process in itself because it is highly recommended + that the FIFO Write waveforms be implemented and tested first. FIFO Write transactions are always the easier to implement out of the two types. The + user can perform a FIFO Write transaction and verify the integrity of the data on the peripheral side, and if the data looks good then implementing + FIFO Reads is the next step. This is an important accomplishment because it will rule out the FIFO Write code as the culprit if problems arise with + the FIFO Read waveform. Otherwise, you will never know which side is truly at fault if each operation is not implemented and tested independently.

    At + this development stage, there may be also several iterations of integration and test before the user is happy with the + overall performance of the design. Issues such as meeting setup and hold time arise, especially for synchronous applications where the main reference + for GPIF operations becomes the external IFCLK or the internal 30/48MHz clock source.
    +
    +     +

+ +
+
    +

    + Optimize if Necessary
     +

+ +
+
    + +

    + In generating the GPIF waveforms, the user may initially decide to be generous with the physical bus timing. So, there may + be room for improvement to cut down the cycle time for each GPIF transaction and still meet the timing parameters required by the peripheral. The + design may also be revised to improve firmware code efficiency and overall firmware code flow at this stage.
    +
    +     +

+ +
+
    +

    + Summary
     +

+ +
+
    + +

    + This section has discussed a GPIF application development flow that uses a systematic approach to help ensure a successful GPIF + design the first time around. Although it has been touched on at somewhat of a macro level, it gives the user a good feel for the amount of effort + involved and an approach to tackle a GPIF design from start to finish, no matter the skill level possessed. Figure 7 summarizes this section in an + ADFM Flow Diagram. The sections ahead discuss the two design examples that will dive into the hardware, firmware, and software necessary to implement + them.
    +
    +     +

+ +
+ +

 

+
+ + + diff --git a/doc/GPIF/GPIF Designer/help/gpif_hlp/Intro.htm b/doc/GPIF/GPIF Designer/help/gpif_hlp/Intro.htm new file mode 100644 index 0000000..5f062a1 --- /dev/null +++ b/doc/GPIF/GPIF Designer/help/gpif_hlp/Intro.htm @@ -0,0 +1,48 @@ + + + + + GPIF + + + + + + + + + + + + + + + +
+

Introduction
 

+ +
+

+To achieve the maximum sustained throughput in USB 2.0 High Speed designs, the physical interconnect should never be the primary bottleneck + in the system. EZ-USB FX2's GPIF (General Programmable InterFace) provides a highly configurable and flexible glueless peripheral interface + that allows the highest possible bandwidth to be achieved over the physical layer. However, along with this flexibility comes added complexity, + and so starting on the right foot has never been more important. To help you get started on your own GPIF designs, this online guide sheds some light + on the architecture and implementation of the FX2 GPIF, discusses application usage models, and debugging strategies. Two end-to-end examples (FIFO and DSP) are + also provided to reinforce GPIF concepts and provide users with concrete design examples. For the best learning experience, use this online guide in + conjunction with the FX2 Technical Reference Manual.

  +

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Introduction

+

FX2 Overview

+

GPIF +Overview
   Physical +Interconnect
   Design +Flow Methodology
+     Design +GPIF Interconnect
     Use +Firmware Frameworks
     Design GPIF Waveforms
     Implement +Single Rd/Wr
     Implement +FIFO Rd/Wr

+ + + diff --git a/doc/GPIF/GPIF Designer/help/main.htm b/doc/GPIF/GPIF Designer/help/main.htm new file mode 100644 index 0000000..bf940bf --- /dev/null +++ b/doc/GPIF/GPIF Designer/help/main.htm @@ -0,0 +1,21 @@ + + +You need a browser that supports frame to veiw this page. + + + + + + + + + + + +<body bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000"> + +<p>You need a browser that supports frame to veiw this page.</p> +</body> + + + \ No newline at end of file diff --git a/doc/GPIF/GPIF Designer/help/main_hlp.htm b/doc/GPIF/GPIF Designer/help/main_hlp.htm new file mode 100644 index 0000000..18b8c06 --- /dev/null +++ b/doc/GPIF/GPIF Designer/help/main_hlp.htm @@ -0,0 +1 @@ + Cypress Semiconductor
\ No newline at end of file diff --git a/doc/GPIF/GPIF Designer/help/main_hlp/BlockDiagram.htm b/doc/GPIF/GPIF Designer/help/main_hlp/BlockDiagram.htm new file mode 100644 index 0000000..a15c73e --- /dev/null +++ b/doc/GPIF/GPIF Designer/help/main_hlp/BlockDiagram.htm @@ -0,0 +1,317 @@ + + + + + Block Diagram + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

Block + Diagram 

+ +
+ +

+
The + first tab page presents a block diagram representing the logical + connection of the FX/FX2 to an attached slave device. The + configuration of this diagram controls the parameters available + during creation of the four waveform descriptors (on the next 4 + tab pages).

 +

+


For + instance, the number of CTL lines available when creating a waveform + is configured using the block diagram.

Only one block diagram + is saved in any GPIF Designer project file (*.GPF).

Once + waveforms have been designed, changing the block diagram may give + rise to undesired changes in the waveforms.  For this + reason, it is highly recommended that the first step in designing + GPIF waveforms be the proper configuration of the Block + Diagram.

+ +
+Chip + Selection
+ +

+ The + first step in configuration of the block diagram should be to + designate the Cypress FX/FX2 chip and pin-package for which + you will be designing. +

The large, + blue, left rectange represents the FX/FX2 chip.  Right-click + in the main body of that rectangle to bring-up the chip-selection + dialog box.
+

+

+

Changing + chips, after waveforms have already been configured, will not + erase those waveforms.  However, because the available + CTL and RDY lines may have changed, those waveforms may no longer + represent what the designer had in mind.  If you change + chips after having designed waveforms, you should re-visit each + waveform (paying special attention to STATUS and CTL Action + Points) to verify their correctness.
 

+ +
+Slave + Labeling
+ +

+ The + large, blue, right rectangle represents the device attached + to the FX/FX2 chip.  The label of this device can be modified + by right-clicking in the main body of the rectangle. +

The label + of the slave block has no impact whatever on the waveform generation. +  It is provided as a matter of convenience only.  The + label is saved, along with the block diagram, in GPIF Designer + project files (*.GPF).
 

+ +
+Clock + Settings
+ +

+ Right-click + on the Clock display area of the block diagram to bring-up the + Clock Properties dialog box. +


 

+ +

The Internal + / External radio buttons of the dialog control the setting + of the IFCLKSRC bit (b7) of the IFCONFIG register.

+

The Invert + Clock checkbox (FX2 only) controls the setting of the IFCLKPOL + bit (b4) of the IFCONFIG register.

+

The IFCLK + Output checkbox (FX2 only) controls the setting of the IFCLKOE + bit (b5) of the IFCONFIG register.

+ +

The 30MHz + / 48MHz radio buttons (only available if Internal clock + is selected) control the setting of the 3048MHZ bit (b6) of + the IFCONFIG register.

+

 

+

When + External Clock is selected, the Clock Frequency is only + used + to calculate the DeltaT displayed on the waveform editor tab + pages.  This setting has no impact on the GPIF waveform + descriptor data that is exported to a GPIF.c file.  Rather, + it is useful to correctly depict time intervals during waveform + editing.
 

+
+Data + Bus Selection
+ +

+ The + second black data band, labelled Data [15:8], can be visually + enabled and disabled by right-clicking on that band.

This + setting has no impact on any of the rest of the program or on + the waveform descriptor data generated using the Tools | Export + function.
 

+ADR + Line Configuration
+ +

+ Right-click + on the group of ADR lines to bring-up the Config ADR Lines dialog + box.  The dialog enables individual or group selection + of the address lines.

Like the Data Bus control, these + settings have no implact on the rest of the program or on the + waveform descriptor data generated by the Tools | Export function. +  They serve only to provide a visual reminder of the actual + hardware application for which the waveform descriptors were + designed.
 

+RDY + Line Configuration
+ +

+ The + RDY lines are used in the definition of STATUS + Action Points + (also known as Decision Points) in the waveform editors.  The names + of the selected RDY lines are presented in the list of operands + for a decision point.  So, the proper configuration of + the RDY lines is important.

To bring-up the Config RDY + Lines dialog, right click on any of the block diagram's RDY lines. +

+



The + internal FIFO Flag is always available in the list of + operands for a decision point.  This dialog only allows + you to change the name for this status line that will appear + in the operand list.  [When defining a waveform decision + point, selection of the FIFO Flag operand will generate a value + of 6 in the respective TERMA or TERMB fields of the + LOGIC FUNCTION register for the state instruction.]

The + Internal RDY line is always available in the list + of operands for a decision point.  This dialog only allows + you to change the name for this status line that will appear + in the operand list.  [When defining a waveform decision + point, selection of the Internal RDY operand will generate a + value of 7 in the respective TERMA or TERMB fields + of the LOGIC FUNCTION register for the state instruction.]

The + Init val of Internal RDY radio buttons control the initial + value of the Internal RDY status line.  [They designate + the initial value of the INTRDY bit (b7) of the GPIFREADYCFG + register.]

Check the Sync RDY to IFCLK box if + the RDY signals are synchronized to the internal clock signal. +  [Checking this box causes the SAS bit (b6) of GPIFREADYCFG + to be set to 1.]

The transaction counter (TC) can be + substituted for RDY line #5.  Check the Subst TC for + RDY 5 checkbox to implement the substitution.  When + this box is checked, RDY 5 becomes permanently available in + the list of decision point operands.  When the Subst + TC for RDY 5 box is checked, the program places a default + label of TCXpire for line #5.  This label can be modified, + even though RDY line #5 cannot be de-selected.  [Checking + this box sets the TCXRDY5 bit (b5) of the GPIFREADYCFG register + to 1.]

The External Inputs can all be individually + selected and labelled.  Only the labels for selected lines + are presented in the list of operands for a decision point. +  [When defining a waveform decision point, selection of + the External Input RDY lines as an operand will generate + a value between 0 and 5 in the respective TERMA or TERMB fields + of the LOGIC FUNCTION register for the state instruction.]
 

+ +
+CTL + Line Configuration
+ +

+ To + configure the CTL lines, right click on any of the block diagram's CTL lines. +

+

The Lines + Can Be Tri-Stated? radio buttons significantly impact the + options available for CTL lines in both the block diagram and + the waveform editors.  If the lines can be tri-stated, + a maximum of 4 CTL lines are available (3 for the 56-pin FX2). +  Also, tri-stateable lines cannot be configured for Open-drain + output. [These Tri-Stated? radio buttons control the value of + the TRICTL bit (b7) of the GPIFCTLCFG register.]

Once + the Lines Can Be Tri-Stated? selection has been made, + the CTL lines to be used should be selected and labelled.  Only + selected lines will be displayed and actionable in the waveform + editors.

CTL Action Points placed on the waveforms + have 2 or 3 available actions, depending on whether or not the + lines have been configured as tri-stateable here.

If + the lines cannot be tri-stated, select the output (CMOS vs + Open-drain) for each line.  [Bits 0-5 of GPIFCTLCFG + register are set to 1, for the respective CTL lines, if Open-drain + is selected.  Selecting CMOS sets the respective bits to + 0.]

+
+

 

+ + + diff --git a/doc/GPIF/GPIF Designer/help/main_hlp/Caption.htm b/doc/GPIF/GPIF Designer/help/main_hlp/Caption.htm new file mode 100644 index 0000000..80373d5 --- /dev/null +++ b/doc/GPIF/GPIF Designer/help/main_hlp/Caption.htm @@ -0,0 +1,25 @@ + + + +Index + + + + + + + + + +
+

 

+ 		+

GPIF + Designer User's + Guide 

+ 		+

 

+
+
+ + diff --git a/doc/GPIF/GPIF Designer/help/main_hlp/FileMenu.htm b/doc/GPIF/GPIF Designer/help/main_hlp/FileMenu.htm new file mode 100644 index 0000000..9893906 --- /dev/null +++ b/doc/GPIF/GPIF Designer/help/main_hlp/FileMenu.htm @@ -0,0 +1,275 @@ + + + + + GPIF + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

File + Menu
  +

+ +

+ The + File menu allows GPIF Designer projects to be loaded from and saved + to disk.  It also provides a simple mechanism for starting + fresh, with a pristine, new project.  Finally, some non-waveform-specific + project properties are also accessed from this menu.
+
+ +

+
    +New +
+ +
+ +
    +

    + The + File|New + menu + item erases all user-placed waveform + action points + and resets all block diagram settings to default values + for the selected chip.

    Selection of     File|New + will bring-up the Chip + Selection + dialog box.  The selection of a chip is needed in order + to determine default values for the new block diagram.

    The +     File|New + item severs any attachment to a GPIF Designer project file. +  So, the File|Save + operation is temporarily disabled until the new project has + been saved using the File|Save + As . . . + menu item.
          +

+ +
+
    +Open +
+ +
+ +
    +

    +File|Open + has the expected functionality of allowing the user to select + a previously saved GPIF Designer project file.

    When the + program launches, the default directory for      File|Open + is set to the directory in which GPIF Designer exectable file + is located.  When a Designer project file (.gpf) has been + opened, the starting directory for File|Open + is set to the directory of the current project file.

    One important side effect + of     File|Open is that, if GPIF + Designer finds a file named "app_note.htm" in the + directory from which the project file is loaded, that file will + be accessible from the This + Project + item of the Help menu.

    The name and path of the currently + open (i.e. active) project file is displayed in the caption + of the GPIF Designer main window.
          +

+ +
+
    +Save +
+ +
+ +
    +

    + File|Save + writes all the block diagram and waveform information to the + currently active GPIF Designer project file.  The + waveforms of all enabled banks + are saved.
          +

+ +
+
    +Save + As +
+ +
+ +
    +

    + File|Save + As + prompts for a name and location of the new GPIF Designer project + file in which to save all the block diagram and waveform information. +  After saving the data, the new file becomes the currently + open (i.e. active) project file.

    GPIF Designer project + files should have the suffix .gpf. 
    +     +

+ +
+
    +Properties +
+ +
+ +
    +

    + The + File|Properties + menu item brings-up the Properties dialog box shown below.
     +

    +


    The +     Show + vertical grid on waveform diagrams + checkbox allows modification of the waveform appearance + to show or hide the vertical grid lines.  Below is an example + of a waveform without the grid lines.  

    + +

    +

    By + default, the vertical grid lines are turned-on when File|New + is invoked.  This setting is saved along with all + other parameters to the GPIF Designer project files (*.gpf) + when the File|Save + or File|Save + As + operations are performed.  

    + +
+ +
+
    +

    Debug + Output

    + +
+ +
+
    +

    The + Enable + GPIF Debug Output on PE[2:0] + checkbox controls the value of the GSTATE bit (b2) of the IFCONFIG + register.  Check this box in order to read the values of + GSTATE bits [2:0] on lines [2:0] of port E.
     

    + +
+ +
+
    +

    Waveform + Banks Enabled

    + +
+ +
+
    +

    GPIF + Designer is able to manage up to 8 sets (i.e. banks) of waveform + descriptors.  Each bank consists of 4 waveform descriptors, + which are displayed on the 4 waveform editor tab pages.  At + any one time, only one bank of waveform descriptors is displayed. +  However, the displayed bank of descriptors can be switched + via the Tools|Select + Waveform Bank + menu item.

    The number of waveform banks available is + configured using the     Waveform + Banks Enabled + field of the File|Properties + dialog box.  

    + +

    +

    When the + Tools|Export + to GPIF.c + file menu item is invoked, waveform + descriptor data structures are exported for all enabled banks.  If + more than 1 bank is enabled, the resulting "*.c" file will + be larger + and more complex.

    It is more common to use the multiple + banks to store variations of similar waveforms, for training purposes, + than to actually generate multiple waveform descriptor data + structures in an exported .c file.

    By default, only 1 + waveform bank is enabled when     File|New + is invoked.

    +
+ +
+

 

+ + + diff --git a/doc/GPIF/GPIF Designer/help/main_hlp/HelpMenu.htm b/doc/GPIF/GPIF Designer/help/main_hlp/HelpMenu.htm new file mode 100644 index 0000000..0f051e3 --- /dev/null +++ b/doc/GPIF/GPIF Designer/help/main_hlp/HelpMenu.htm @@ -0,0 +1,115 @@ + + + + + GPIF + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

Help + Menu
  +

+ +

+ Cypress + GPIF Designer help menu provides access to on-line documentation + for the Designer tool itself, for Cypress-provided GPIF Designer application + files, and for the FX and FX2 GPIFs, generally.
+
+
+ +

+
    +This + Tool +
+ +
+ +
    +

    + Accesses + the GPIF Designer User's Guide that you are now reading.
    +
    +
    +     +

+ +
+
    +This + Project
     +
+ +
+ +
    +

    + This + menu item opens a project-specific application note.  The program + displays a file called "app_note.htm" from the + directory from which the currently open GPIF Designer project + file was loaded. +
    +
    +     +

+ +
+
    +General + GPIF +
+ +
+ +
    +

    + This + menu item opens an on-line GPIF Primer document, providing technical + information about the FX / FX2 GPIF.
    +     +

     

    + +
+
+ + + diff --git a/doc/GPIF/GPIF Designer/help/main_hlp/Overview.htm b/doc/GPIF/GPIF Designer/help/main_hlp/Overview.htm new file mode 100644 index 0000000..bbd990e --- /dev/null +++ b/doc/GPIF/GPIF Designer/help/main_hlp/Overview.htm @@ -0,0 +1,72 @@ + + + + + Overview + + + + + + + + + + + + + + + + + + + + + + +
+

Overview
  +

+ +

+ Cypress + GPIF Designer allows the user to create and modify GPIF waveform descriptors for the EZ-USB FX and FX2 chips using a graphical user interface.
+
+ The main window consists of 5 tab pages. The first page + presents a block diagram representing the logical connection of + the the FX/FX2 to an associated slave device.

Each + of the remaining four pages contains a waveform editor.  These + editors enable the creation of 4 distinct GPIF state machines + or "waveforms".

As a general rule, existing settings + can usually be modified by right-clicking the mouse on the region + where the setting is displayed.  This applies to both the block + diagram and the waveforms.

Waveforms are modified by placing, + moving or modifying Action Points on various waveform Bands.  Use + the left mouse button to place or drag action points.  Use + the right mouse button to modify an existing action point.
+
  +

+ Additional + Information +
+ +

+ An + extensive discussion of general GPIF functionality and programming + is distributed as a General + GPIF User's Guide, + accessible from the main Help menu.

PDF (Adobe Acrobat) files + of a GPIF Primer as well as the FX and FX2 Technical Reference + Manuals are located in the PDFs sub-directory within GPIF + Designer install directory.

Also, design examples + provided by Cypress include on-line application notes for those + examples.  Those notes are automatically loaded when the project's + *.gpf file is opened.  (See the Help + section of this User's Guide for more information.)

+ +

+ + + diff --git a/doc/GPIF/GPIF Designer/help/main_hlp/ToolsMenu.htm b/doc/GPIF/GPIF Designer/help/main_hlp/ToolsMenu.htm new file mode 100644 index 0000000..8e32038 --- /dev/null +++ b/doc/GPIF/GPIF Designer/help/main_hlp/ToolsMenu.htm @@ -0,0 +1,240 @@ + + + + + GPIF + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

Tools + Menu
  +

+ +

+ Several + essential, but unrelated, functions are presented under the Tools + menu.  These operations allow, among other things, the exporting + of of defined waveforms to "C" programming language data + structures.  Also, waveforms defined using Cypress' older GPIF + tool can be imported into GPIF + Designer + from the Tools + menu.
+
+ +

+
    +Select + Waveform Bank +
+ +
+ +
    +

    GPIF + Designer is able to manage up to 8 sets (i.e. banks) of waveform + descriptors.  Each bank consists of 4 waveform descriptors, + which are displayed on the 4 waveform editor tab pages.  At + any one time, only one bank of waveform descriptors is displayed. +  However, the displayed bank of descriptors can be switched + via the Tools|Select + Waveform Bank + menu item.

    + +

    +

    The + bank number of the currently active waveform bank is displayed + at the bottom of each waveform editor tab page, as shown above.

    By + default, only a single waveform bank is enabled.  To     enable + additional banks, + use the File|Properties + menu.
     

    +
+ +
+
    +Map + Waveforms to WFSELECT +
+ +
+ +
    +

    + Each + of the 4 waveforms can be configured to perform any arbitrary + function (single/fifo read or write).  That is, there is + no constraint on what function must be implemented on any given + waveform tab page.  For instance, after performing a File|New + operation, the 4 waveform tabs are labelled, successively + as Single + Read, Single Write, Fifo Read, + and Fifo + Write, as shown below.  (After + a File|New + operation, there are no waveforms defined.  So, the labelling + of the tabs is completely arbitrary.)
     +

    +



    In + the Fifo design example, shown below, the first waveform tab + has been used to define a FIFORd operation.  The second + waveform has been used to define a FIFOWr operation.  The + 3rd and 4th waveforms are unused.

    +

    +



    Because + there is no requirement that waveform tab labels reflect the + actual function of the waveform defined on that page, and because + the designer is allowed the freedom of placing any functional + waveform on any tab page, a mapping is needed to tell the GPIF + what function is really found on each waveform tab page.  

    This + mapping is defined in the GPIF register, WFSELECT, and is configured + via the     Tools|Map + Waveforms to WFSELECT . . . + menu item.  The Map + Waveforms to WFSELECT + dialog box is shown below, with the configuration of the FIFO + design example.

    +


    +



    Note + that, after a File|New operation, the 4 waveforms have + been mapped into WFSELECT such that the function named in the + tab label would be appropriate for that tab sheet.  That + is, after a File|New operation, the designer could implement + the Single Read function in the first waveform, the + Single Write function in the second waveform, the FIFO + Read function in waveform #3 and the FIFO Write function in + the last waveform.  If the designer created these waveform + functions, corresponding to the default waveform tab labels, + the WFSELECT mapping would not need to be changed.

    +

     

    +


    +

    + +
+ +
+
    +Export + to GPIF.c file +
+ +
+ +
    +

    + The + principal objective in defining a set of GPIF waveforms is to + generate the waveform descriptors, as "C" language + data structures for inclusion in a firmware project + for the FX / FX2.  Once the block diagram has been specified + and the waveforms have been correctly defined using the waveform + editors, GPIF Designer can generate correct "C" language + data structures to be used in programming the device.  

    The + generation of the data structures is accomplished via the     Tools|Export + to GPIF.c file + menu item.  When this menu item is invoked, the user will + be prompted to specify a location and file name for the data + structures.  It is important to understand that the Export + to GPIF.c file + function completely over-writes the specified file with + the waveform descriptor data.  It does NOT merely append + or insert the data structures into an existing file.  For + this reason, the user will usually want to specify a new file + as the target of the Export operation.

    Also note that + it is not necessary to export the waveform descriptor data structures + to the same directory as the GPIF Designer project file.

    The + file generated by the Tools|Export to GPIF.c file function contains + many comments reflecting the original GPIF Designer project + file from which the data structures were derived.  These + comments contain strings that reflect waveform tab labels and + block diagram configurations such as CTL and RDY line labels. +  In order to generate a "*.c" file compatible + with the older GPIF tool, many of these labels are truncated + when exported to the "*.c" file.  One should + expect to lose some string information if attempting to import + a file generated by the Tools|Export to GPIF.c file operation.

    The + primary vehicle for saving and loading GPIF waveform designs + is the     File + menu.  The Tools|Export/Import + functions do not retain or recover all the information stored + in a GPIF Designer (*.gpf) file.
          +

+ +
+
    +Import + older GPIF.c file +
+ +
+ +
    +

    + GPIF + Designer is the second-generation of Cypress tools for defining + GPIF waveform descriptors for the FX/FX2.  Waveform descriptors + generated by the previous tool can be read into GPIF Designer + via the + Tools|Import older EZ-USB FX GPIF.c file + and Tools|Import + older FX2 GPIF.c file + menu items.

    Because the file formats generated by the + older tool differ for EZ-USB FX and FX2, separate import menu + items are used to import the appropriate file types.  Be + sure to invoke the correct operation for the file type that + is to be imported.

    Note that, in order for the import + functions to work, the target file must be in a format compatible + with the old tool.  If the file has been manually modified + so as to render its format incompatible with the older + GPIF tool, the import functions will fail to import the file.
          +

+ +
+ + + diff --git a/doc/GPIF/GPIF Designer/help/main_hlp/WavefmEditors.htm b/doc/GPIF/GPIF Designer/help/main_hlp/WavefmEditors.htm new file mode 100644 index 0000000..61eca99 --- /dev/null +++ b/doc/GPIF/GPIF Designer/help/main_hlp/WavefmEditors.htm @@ -0,0 +1,735 @@ + + + + + Waveform Editors + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

Waveform + Editors  +

+ +

+
The + four tab pages following the Block Diagram page present graphical + editors for defining four distinct GPIF waveforms (i.e. state machines).

Each + of the four waveforms may be configured for a specific type + of data transaction.  For instance, the waveform depicted below + is for iterative reading of data from a connected FIFO device.  The + second waveform (on the tab labeled "FIFOWr") is for iterative + writing of data to a connected FIFO device.

Each of the waveforms + can be configured for any IO task (i.e. Single Read, Single Write, + Multi Read, Multi Write, etc.)  That is, the first waveform + could be created for Single Write operation, rather than the FIFO + Read operation shown below.

The label of each waveform tab + can be modified by right-clicking on the page tab. +


+

 

+

Each + waveform tab page contains certain graphic elements which are used + in the design of a waveform.  The thick, horizontal lines are + called bands.  The States band shows the GPIF states that are + implied by Action Points of the other bands.  Action Points, + placed on the several bands, define the state machine that is the + waveform.

+

+

The DeltaT + displayed in the lower left corner of each Waveform Editor tab shows + the time, in ns, from the cursor to the nearest Action Point left + of the cursor.
+
+

+ +
+Action + Points
+ +

+ Action + Points are the vehicle for imposing state and line transitions + in a waveform.  To place an action point on a band, left-click + on the band.  Action points can be dragged to different + positions on the band in which they reside.  

Each + type of band has a corresponding specific type of action point + associated with it.  And, each type of action point has + a different set of behaviors or properties that can be configured. +  To set the properties of an action point, right-click + the action point.  (The Addr action points are not configurable. +  They have a single function which is to increment the + address.) +

To + delete an action point, right-click the action point and select + "Delete" from the pop-up menu.  To delete all + the user-placed action points from a waveform, right-click the + waveform tab and select "Clear waveform" from the + pop-up menu.

An "empty" waveform contains the + permanent action points shown below.  These permanent action + points cannot be deleted or moved.  However, their properties + can be modified by right-clicking on them.

+

+


To + copy all the action points from one waveform to another, right-click + on the current waveform tab and select "Copy waveform . + . ." from the pop-up menu.  A dialog box will pop-up, + prompting for the destination tab page to receive the new action + points.  The "Copy waveform" function erases + all existing action points from the destination waveform before + copying the new action points to that location.  So, the + destination waveform becomes an exact copy of the source. +  
 

+ +
+
    +DATA + Action Points +
+
+ +
    +

    + Data + action points control two parameters of the data bus. +  First, the action point controls whether to keep the + same data on the bus or place new data onto the bus.  Second, + the action point controls whether to activate or de-activate + the data bus.

    Same + vs Next + status of the bus is depicted by the COLOR of the data trace. +  A change in color depicts Next data.  Constant + color connotes Same data.

    Active vs Inactive status + of the bus is depicted by the POSITION of the data trace. +  A trace running along the bottom of the band represents + inactive.  A trace along the top connotes an active + bus.
     +



    +
+
    +

     
    In + the waveform above, the first data action point keeps the + same data (trace color stays the same) on the bus and de-activates + the data (trace moves to bottom of band).  The + next data action point places Next data on the bus (trace + color changes) and activates the data (trace moves to top + of band).  The third data action point keeps the same + data (trace color stays yellow) on the bus and de-activates + the data (trace moves to bottom of the band).  Finally, + the last data action point keeps the same data (trace stays + yellow) and activates the bus (trace moves to top of band).

    Data + action points, for the FX2 series chips, also have two variations + on the "    Next + Data" + theme.  These are SGLDATAH/L + and UDMA_CRCH/L. +  Either of those selection has the same effect as Next + FIFO Data + on the displayed data trace.  SGLDATAH/L + and UDMA_CRCH/L + merely specify alternate sources of the next data.

    When + a new Data action point is placed on the Data band, the + initial state of the action point is     Same + Data + with opposite activity to the last (rightmost) action + point on the band.

    Data action points located on + the left edge of the IDLE state cannot present any form + of "Next Data".  Such Data action points + are limited to     Activate + / De-activate + as their functional domain. 

    HINT: Rather than + clicking on the Data action points directly, it is also possible + to modify the state of the Data trace by right-clicking on the Data + band in the region of the trace.  This action simply modifies + the properties of the nearest Data action point left of the mouse.   When + you click on the band, rather than an action point, the "Delete" + menu item will not appear.
     

    + +
+
+
    +ADDR + Action Points
     +
+
+ +
    +

    + Addr + action points are represented as a plus symbol (+) on the + Addr band.  Placing an Addr action point causes the + value of the address bus to be incremented at that point. +  

    Addr action points have no other functionality. +  So, the pop-up menu for these action points only provides + the mechanism for deletion of the point.  Of course, + like all action points, Addr action points can be dragged.

    Addr + action points cannot be placed on the left boundary + of the IDLE state because the IDLE state does not have the + capability of incrementing the address. 
          +

+
+
    +Status + Action Points
     +
+
+ +
    +

    + Status + action points are also referred to as Decision Points.  These + action points are used to cause the GPIF to remain in a + given state until (or branch to a different state when) + some condition of the RDY lines is achieved.

    Status + action points create states of indefinite length.  (The + state will last until the decision causes a branch away + from the state.)  To indicate this, the clock trace + at the top of each waveform diagram is "broken" + above any status action point.

    After a Status action + point has been placed, the     Specify + Decision Point + dialog box will automatically be displayed to allow specification + of the branching / exit condition for the state.  (Note that + the Status action point has already been placed when the dialog + pops-up.  Clicking the Cancel + button of the dialog will not delete the action point.)  The + Specify Decision Point + dialog box can be accessed later by right-clicking on the decision + point and selecting Edit from the pop-up menu.

    The exit / branch decision is a + logic operation between any two of the enabled RDY lines + (including internal status lines) as specified on the     block + diagram.  When the GPIF enters a state containing a + decision point, any other actions indicated by action points + at the start of the state are executed.  Then, the + logic condition is evaluated.  If the condition is + satisfied, the GPIF will branch to (GOTO) the first state + specified.  Otherwise, it will branch to the second + (ELSE) state specified.
     +

    +
+
    +

    The + decision point, displayed above, is of interest.  It + specifies that, on entry into state S3, the transaction + counter (TCXpire) should be tested.  (Note that TCXpire + is compared against itself, causing the decision to be based + on a single input.)  If TCXpire = 1 the GPIF will branch + to the IDLE state, concluding the waveform.  If TCXpire + = 0,  the GPIF will branch to state S3 (the current + state).  This decision point essentially says "Stay + in S3 until the transaction counter expires.  Then + exit the waveform."

    For instructions on how + to make the transaction counter (TC) an input to decision + points, see the discussion of     RDY + Line Configuration + in the Block Diagram section.

    Status action points + are not allowed on the left boundary of the IDLE state because + the IDLE state is not able to execute the conditional branching + mechanism of a decision point.  If you attempt to place + a Status action point on the IDLE state boundary, the waveform + editor will automatically insert a buffer state between + the action point and the IDLE state.

    Because the + input arguments for a decision point depend on the RDY line + configuration of the Block Diagram, all decision points of + each waveform should be edited and verified for correctness + whenever the configuration of the RDY lines is changed. 
     

    + +
+
+
    +LOOP + / Re-Execute
     +
+
+ +
    +

    + The + LOOP (Re-execute) checkbox in the Specify Decision Point + dialog, controls whether or not the other actions of + the state are repeated when the decision branches to + the same state.  For instance, at the beginning + of S3 in the below waveform, the Data bus + is asserted and next data is placed on the bus, the + address is incremented, and CTL lines REN# and + OE# are sent high.  
     +

    +

    If + TCXpire is not 1, the GPIF will branch back to S3, the + current state.  Because the LOOP (Re-execute) box + is checked, next data will again be placed on the data + bus and the address again be incremented  These + activities will repeat each time the decision point + branches back into S3.

    [If LOOP (Re-execute) + is checked, the Re-Execute bit (b7) of the Length/Branch + register of the state instruction is set to 1.] 
     

    + +
+
+
    +CTRL + Action Points
     +
+
+ +
    +

    + Depending + on the CTL + line Configuration + of the Block diagram, up to 6 CTL bands will be displayed + in the waveform editors.  Each CTL action point can + be configured as High (1), Low (0), or Tri-state (z) if + the CTL lines have been configured to allow tri-state.

    Whenever + a new CTL line is dropped onto a CTL band, it's initial + state is opposite to that of the last (rightmost) action + point on the band.  (In deciding this initial + status tri-state is considered to be Low (0).)

    HINT: + Rather than clicking on the CTL action points directly, it + is also possible to modify the state of the CTL traces by right-clicking + on the CTL bands in the region of the traces.  This action + simply modifies the properties of the nearest CTL action + point left of the mouse.   When you click on the + band, rather than an action point, the "Delete" menu item + will not appear.
          +

+
+States
+ +

+ The + FX/FX2 GPIF is implemented as a state machine, capable of 8 + distinct states (including the IDLE) state.  Each waveform + editor contains a States band that displays the states + implied by the action points of the waveform.

New states + cannot be created directly, by left-clicking on the state band. +  Rather, they are created by placing action points on other + bands.  Whenever an action point is placed on a band, the + waveform editor checks to see if the action point has been placed + on an existing state boundary.  If not, a new state is + created.  When the GPIF state machine enters one of the + states of a waveform, it will execute those action + points found along the state's left boundary.

By default, + state durations are calculated from their displayed length in + the waveform.  (See Set + State Duration, + to learn about setting the duration to a fixed length.) +  When the cursor moves over a state, the duration of the + state will be briefly pop-up just below the cursor.

[The IDLE state has no specific duration + and is only defined by the action points of the Data and + CTL bands.] 
 

+
    +State + Properties
     +
+
+ +
    +

    + There + are some state properties that are not implied by action + points.  These are configured by right-clicking on + the state to bring up a State Properties dialog box.  
     +

    +

    The + State Properties dialog for non-decision point states (such + as S2, above) do not allow configuration of Flow State. +  



    The State Properties dialog for state + S3 (a decision point state) has the Flow State configuration + controls enabled, below.

    +

    +


    [The + IDLE state does not have properties that can be configured + via the State Properties dialog box.  Right clicking + on the IDLE state has no effect.]
     

    + +
+
+
    +Generate + Interrupt +
+
+ +
    +

    + On + entry to a given state, the GPIF can generate a GPIFWF interrupt + on the INT4 line.  To enable the interrupt, bring-up the State + Properties + dialog box by right-clicking on the state.  Then, check + the Generate + Interrupt + box in the dialog.
    +
    [Checking the Generate Interrupt box will + set the GINT bit (b4) of the OPCODE register of the state instruction + to 1.]
          +

+
+
    +Set + State Duration +
+
+ +
    +

    + Non-decision + point states can range in duration from 1 to 256 clock cycles.  However, + the waveform editors only display 20 clock cycles.  In order + to create states with longer durations, the state must be designated + as a "fixed duration", rather than a calculated duration + state.  Once this is done, there is no correlation between + the states visible length and its duration.

    To set a fixed state + duration, bring-up the     State + Properties + dialog by right-clicking on the state of interest.  (Only non-decision + point states can have their duration set.)  Then click the + Set + State Duration + button.  The dialog box, shown below, will appear.
     +

      +

      +
    +

    Un-check + the Calculate + Duration from Waveform Diagram + box.  This will cause the duration to stay at the value of + the Duration + (Clock Cycles) + field, regardless of how long the state is made to appear on the + waveform diagram.

    When viewing a waveform, the only way to + be sure of a state's duration is to move the mouse over the state + and read the duration shown in the pop-up hint.

    Note that + the need to make a state's duration fixed is somewhat uncommon.
     

    +
+
+
    +Use + as the Flow State
     +
+
+ +
    +

    + Decision + point states can also be designated as a Flow State.  To designate + a decision point state as the flow state, right-click on the decision + point state to bring-up the State + Properties + dialog box.  Then, check the Use + as the Flow State + box. 

    Only one Flow State can exist in a given waveform. +  When a state has been designated as the flow state for a waveform, + the state will be colored yellow.
     +

    +
      +
        +

         

        + +
      +
    +
+
+
    +Configure + Flow State +
+
+ +
    +

    + If the + Use + as the Flow State + box of the State + Properties + dialog is checked, the Configure + Flow State + button will be enabled, allowing configuration of the flow-state + parameters.  Click on the Configure + Flow State + button to bring-up the Flow + State Parameters + dialog box, below.
     +

    +
      +
        +

         

        + +
      +
    +
+
+
    +Flow + Logic +
+
+ +
    +

    + The + Flow Logic tab of the Flow + State Parameters + dialog is used to define the state of CTL lines, based on the + state of RDY lines.  This is similar to the configuration of + Status + action points, + except that the flow logic does not control exit conditions of the + state.  Rather, the flow logic test is repeatedly performed + and the configuration of the CTL lines repeatedly changed based + on the outcome of the test.  This repeated functionality persists + until the branching conditions of the state's decision point cause + the GPIF to exit the state.

    To cause a CTL line to be set + High (1) when the condition of the test is satisfied, check the + box for  the CTL line in the THEN section.  Un-check the + box to make the line go Low (0).  Similarly, when the condition + is not satisfied, the state of the CTL lines can be explicitly controlled + using the checkboxes of the ELSE section.     +

    +

    +If + Tri-state has been enabled in the Configure + CTL lines + dialog of the block diagram, the Enable + output + checkboxes will be enabled.

    [The THEN section of checkboxes + controls the contents of the FLOWEQ1CTL register.  The ELSE + section of checkboxes controls the FLOWEQ0CTL register.]
          +

+
+
    +Strobe +
+
+ +
    +

    +The + Strobe tab configures a Master + Strobe Pin + to be used in causing data to be read or written during the flow + state. [Most of the settings on this tab control bits of the FLOWSTB + register.]

    The     Slave + checkbox should be checked if the GPIF is acting as a slave + on the bus.  In this condition, the Master + Strobe Pin + can be selected from a list of the available RDY + lines. +  Also, in this condition, check the RDYASYNC + box to make the selected Master + Strobe Pin + synchronous to IFCLK.
     +

    +



    Un-check + the     Slave + checkbox if the GPIF is acting as the bus master.  In this + condition, the Master + Strobe Pin + can be selected from a list of the available + CTL lines. +   Also, in this condition, check the CTLTOGL + box to cause the THEN (i.e. satisfied) condition of the Flow + Logic + to toggle the Master + Strobe Pin. +  Un-check the CTLTOGL + box to cause the ELSE (i.e. not satisfied) condition of the Flow + Logic to toggle the Master + Strobe Pin.

    +

    +

    Uncheck the + SUSTAIN + box + to allow  the Master Strobe Pin CTL line to be restored + to its waveform-defined state when the GPIF exits the flow state.


    C    heck + the RISING EDGE DATA XFER box to transfer data on the rising + edge of the clock when Master Strobe Pin is toggled.  Check + the Falling EDGE DATA XFER box to transfer data on the falling edge + of the clock when Master Strobe Pin is toggled.  Both + RISING EDGE and FALLING EDGE can be selected to cause + double-edge data transfers when Master Strobe Pin is toggled. +  [The DATA XFER check boxes control bits 0 and 1 of the FLOWSTBEDGE + register.]

    The Master Strobe Half Period field defines + the half period of the Master Strobe Pin toggling frequency. +  The minimum value is 2 (or 1 clock pulse).  A value of + 3 would cause the Master Strobe Pin to toggle every 1.5 clock + pulses.
     

    +
+
+
    +Hold-Off +
+
+ +
    +

    + The + Hold-Off tab contains controls to configure the FLOWHOLDOFF register + and the GPIFHOLDTIME register. +  

    These settings are only useful in certain conditions. +  If the GPIF is acting as a slave on the bus (    Slave + box on the Strobe + tab is checked) and the Master Strobe is asynchronous to the IFCLK + signal (RDYASYNC + box on the Strobe tab is not checked), the Hold-Off settings will + be used when data is written to the GPIF.

    Check the     HOCTL + pin is asserted when Not Ready (HOSTATE) + box to cause the Hold-off CTL bin to be sent High (1) when not ready. + [Checking this box causes the HOSTATE bit (b3) of the FLOWHOLDOFF + register to be set to 1.]

    Select the CTL pin that will be + used to indicate a Hold-off condition from the     CTL + Pin Used to indicate Hold-Off + drop-down list. [The line selected determines the value of the HOCTL + bits (2:0) of FLOWHOLDOFF register.]

    The     Hold-Off + Period (clocks) + field indicates how long to keep the CTL + Pin Used to indicate Hold-Off + in the Hold-Off State in order to allow the external bus master + to catch-up.  [This value is placed in the HOPERIOD field (bits + 7:4) of the FLOWHOLDOFF register.]

    The     Hold + Time (clocks) + field determines how long data is held on the DATA bus when + written by the GPIF.  This value can be set to 0, 1/2 or + 1 clock cycle.  [The Hold + Time (clocks) + setting controls the value of the GPIFHOLDTIME register.]
     +


    +

    +
+
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Overview

+

Block Diagram
    Chip +Selection
    Slave Labeling
   Clock Settings
+   Data Bus Selection
   ADR line Configuration
 +   RDY line Configuration
   CTL line Configuration

+

Waveform Editors
    Action +Points
       DATA Action Points
        ADDR +Action Points
       STATUS Action Points
+           Loop / Re-Execute
+       CTRL Action Points
   States
+       Properties
           Generate +Interrupt
            Set +State Duration
           Use +as the Flow State
           Configure +Flow State
               Flow +Logic
               Strobe
+               Hold-Off

+

File
   New
+   Open
   Save
   Save +As
    Properties
+       Debug +Output
       Banks +Enabled

+

Tools
   Select +Waveform Bank
   Map Wforms to WFSELECT
   Export +to GPIF.c file
   Import older GPIF.c file

+

Help
    This +tool
    This project
    General GPIF

+ + + diff --git a/lib/fx2lp/compile_flags.txt b/lib/fx2lp/compile_flags.txt new file mode 100644 index 0000000..6cfe596 --- /dev/null +++ b/lib/fx2lp/compile_flags.txt @@ -0,0 +1,2 @@ +-I +./inc diff --git a/lib/fx2lp/inc/fx2.h b/lib/fx2lp/inc/fx2.h new file mode 100644 index 0000000..de3471e --- /dev/null +++ b/lib/fx2lp/inc/fx2.h @@ -0,0 +1,413 @@ +#ifndef FX2_H +#define FX2_H + +// ---------------------------------------------------------------------------- +// Constants +// ---------------------------------------------------------------------------- +#define TRUE 1 +#define FALSE 0 + +#define true 1 +#define false 0 + + +typedef unsigned char bool; + +typedef unsigned char BYTE; +typedef unsigned short WORD; +typedef unsigned long DWORD; + + +#define DSCR_DEVICE 1 // Descriptor type: Device +#define DSCR_CONFIG 2 // Descriptor type: Configuration +#define DSCR_STRING 3 // Descriptor type: String +#define DSCR_INTRFC 4 // Descriptor type: Interface +#define DSCR_ENDPNT 5 // Descriptor type: Endpoint +#define DSCR_DEVQUAL 6 // Descriptor type: Device Qualifier +#define DSCR_OTHERSPEED 7 // Descriptor type: Other Speed Configuration + +#define bmBIT0 0x01 +#define bmBIT1 0x02 +#define bmBIT2 0x04 +#define bmBIT3 0x08 +#define bmBIT4 0x10 +#define bmBIT5 0x20 +#define bmBIT6 0x40 +#define bmBIT7 0x80 + +#define bmBUSPWR bmBIT7 +#define bmSELFPWR bmBIT6 +#define bmRWU bmBIT5 + +#define bmEPOUT bmBIT7 +#define bmEPIN 0 + +#define EP_VALID 0x80 +#define EP_INVALID 0x00 + +#define EP_IN 0x40 +#define EP_OUT 0x00 + +#define EP_INT 0x30 +#define EP_BULK 0x20 +#define EP_ISO 0x10 + +#define EP_1024 0x08 +#define EP_512 0x00 +#define EP_64 0x00 + +#define EP_3x 0x03 +#define EP_2x 0x02 +#define EP_4x 0x00 + +#define IRQ_EP0IN bmBIT0 +#define IRQ_EP0OUT bmBIT1 +#define IRQ_EP1IN bmBIT2 +#define IRQ_EP1OUT bmBIT3 +#define IRQ_EP2 bmBIT4 +#define IRQ_EP4 bmBIT5 +#define IRQ_EP6 bmBIT6 +#define IRQ_EP8 bmBIT7 + +#define SUD_SIZE 8 // Setup data size + + +#define VECT_INT0 0 +#define VECT_TMR0 1 +#define VECT_INT1 2 +#define VECT_TMR1 3 +#define VECT_COM0 4 +#define VECT_TMR2 5 +#define VECT_WKUP 6 +#define VECT_COM1 7 +#define VECT_USB 8 +#define VECT_I2C 9 +#define VECT_INT4 10 +#define VECT_INT5 11 +#define VECT_INT6 12 + +// ---------------------------------------------------------------------------- +// USB interrupt INT2IVEC values +// ---------------------------------------------------------------------------- +#define INT2_SUDAV 0x00 +#define INT2_SOF 0x04 +#define INT2_SUTOK 0x08 +#define INT2_SUSPEND 0x0C +#define INT2_RESET 0x10 +#define INT2_HISPEED 0x14 +#define INT2_EP0ACK 0x18 +#define INT2_EP0IN 0x20 +#define INT2_EP0OUT 0x24 +#define INT2_EP1IN 0x28 +#define INT2_EP1OUT 0x2C +#define INT2_EP2 0x30 +#define INT2_EP4 0x34 +#define INT2_EP6 0x38 +#define INT2_EP8 0x3C +#define INT2_IBN 0x40 +#define INT2_EP0PING 0x48 +#define INT2_EP1PING 0x4C +#define INT2_EP2PING 0x50 +#define INT2_EP4PING 0x54 +#define INT2_EP6PING 0x58 +#define INT2_EP8PING 0x5C +#define INT2_ERRLIMIT 0x60 +#define INT2_EP2ISOERR 0x70 +#define INT2_EP4ISOERR 0x74 +#define INT2_EP6ISOERR 0x78 +#define INT2_EP8ISOERR 0x7C + +// ---------------------------------------------------------------------------- +// GPIF/FIFO interrupt INT4IVEC values +// ---------------------------------------------------------------------------- +#define INT4_EP2PF 0x80 +#define INT4_EP4PF 0x84 +#define INT4_EP6PF 0x88 +#define INT4_EP8PF 0x8C + +#define INT4_EP2EF 0x90 +#define INT4_EP4EF 0x94 +#define INT4_EP6EF 0x98 +#define INT4_EP8EF 0x9C + +#define INT4_EP2FF 0xA0 +#define INT4_EP4FF 0xA4 +#define INT4_EP6FF 0xA8 +#define INT4_EP8FF 0xAC + +#define INT4_GPIF_DONE 0xB0 +#define INT4_GPIF_WF 0xB4 + + + +// ---------------------------------------------------------------------------- +// HID constants +// ---------------------------------------------------------------------------- +#define SETUP_MASK 0x60 // Used to mask off request type +#define SETUP_REQ_STANDARD 0x00 // Standard request +#define SETUP_REQ_CLASS 0x20 // Class request +#define SETUP_REQ_VENDOR 0x40 // Vendor request +#define SETUP_REQ_RESERVED 0x60 // Reserved or illegal request + +// ---------------------------------------------------------------------------- +// Setup commands +// ---------------------------------------------------------------------------- +#define SC_GET_STATUS 0x00 +#define SC_CLEAR_FEATURE 0x01 +#define SC_RESERVED 0x02 +#define SC_SET_FEATURE 0x03 +#define SC_SET_ADDRESS 0x05 +#define SC_GET_DESCRIPTOR 0x06 +#define SC_SET_DESCRIPTOR 0x07 +#define SC_GET_CONFIGURATION 0x08 +#define SC_SET_CONFIGURATION 0x09 +#define SC_GET_INTERFACE 0x0a +#define SC_SET_INTERFACE 0x0b +#define SC_SYNC_FRAME 0x0c +#define SC_ANCHOR_LOAD 0xa0 + +#define GD_DEVICE 0x01 +#define GD_CONFIGURATION 0x02 +#define GD_STRING 0x03 +#define GD_INTERFACE 0x04 +#define GD_ENDPOINT 0x05 +#define GD_DEVICE_QUALIFIER 0x06 +#define GD_OTHER_SPEED_CONFIG 0x07 +#define GD_INTERFACE_POWER 0x08 +#define GD_HID 0x21 +#define GD_REPORT 0x22 + +#define GS_DEVICE 0x80 // Get Status: Device +#define GS_INTERFACE 0x81 // Get Status: Interface +#define GS_ENDPOINT 0x82 // Get Status: Endpoint + +#define FT_DEVICE 0x00 // Feature: Device +#define FT_ENDPOINT 0x02 // Feature: Endpoint + + + +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +// Data types +// +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +// ---------------------------------------------------------------------------- +// Descriptor header +// ---------------------------------------------------------------------------- +typedef struct +{ + BYTE length; + BYTE type; +} DSCR; + +// ---------------------------------------------------------------------------- +// Device descriptor [type=1] +// ---------------------------------------------------------------------------- +typedef struct +{ + BYTE length; // descriptor length ( = sizeof(DEVICE_DSCR) ) + BYTE type; // descriptor type ( Device = 1) + + BYTE spec_ver_minor; // specification version (BCD) minor + BYTE spec_ver_major; // specification version (BCD) major + + BYTE dev_class; // device class + BYTE dev_subclass; // device subclass + BYTE dev_protocol; // device protocol + + BYTE max_packet; // maximum packet size + + WORD id_vendor; // vendor ID + WORD id_product; // product ID + WORD id_version; // product version ID + + BYTE str_manufacturer; // manufacturer string index + BYTE str_product; // product string index + BYTE str_serial; // serial number string index + + BYTE configs; // number of configurations +} DEVICE_DSCR; + +// ---------------------------------------------------------------------------- +// Device qualifier descriptor [type=6] +// ---------------------------------------------------------------------------- +typedef struct +{ + BYTE length; // descriptor length ( = sizeof(DEVICEQUAL_DSCR) ) + BYTE type; // descriptor type ( Device Qualifier = 6) + + BYTE spec_ver_minor; // specification version (BCD) minor + BYTE spec_ver_major; // specification version (BCD) major + + BYTE dev_class; // device class + BYTE dev_subclass; // device subclass + BYTE dev_protocol; // device protocol + + BYTE max_packet; // maximum packet size + + BYTE configs; // number of configurations + BYTE reserved; +} DEVICEQUAL_DSCR; + +// ---------------------------------------------------------------------------- +// Configuration descriptor [type=2] +// ---------------------------------------------------------------------------- +typedef struct +{ + BYTE length; // descriptor length ( = sizeof(CONFIG_DSCR) ) + BYTE type; // descriptor type ( Configuration = 2) + + WORD config_length; // configuration + endpoints length + BYTE interfaces; // number of interfaces + BYTE index; // configuration number + BYTE str_config; // configuration string index + BYTE attrib; // attributes (buspwr,selfpwr,rwu) + BYTE power; // power requirement (div 2 mA) +} CONFIG_DSCR; + +// ---------------------------------------------------------------------------- +// Interface descriptor [type=4] +// ---------------------------------------------------------------------------- +typedef struct +{ + BYTE length; // descriptor length ( = sizeof(INTERFACE_DSCR) ) + BYTE type; // descriptor type ( Interface = 4) + + BYTE index; // zero-based index of this interface + BYTE alt_setting; // alternate setting + BYTE ep_count; // number of endpoints + + BYTE if_class; // interface class + BYTE if_subclass; // interface subclass + BYTE if_protocol; // interface protocol + + BYTE str_interface; // interface string index +} INTERFACE_DSCR; + +// ---------------------------------------------------------------------------- +// Endpoint descriptor [type=5] +// ---------------------------------------------------------------------------- +typedef struct +{ + BYTE length; // descriptor length ( = sizeof(ENDPOINT_DSCR) ) + BYTE type; // descriptor type ( Endpoint = 5) + + BYTE ep_address; // endpoint address + BYTE ep_type; // endpoint type + + BYTE mp_low; // maximum packet size (LOW) + BYTE mp_high; // maximum packet size (HIGH) + + BYTE interval; // interrupt polling interval +} ENDPOINT_DSCR; + +// ---------------------------------------------------------------------------- +// String descriptor [type=3] +// ---------------------------------------------------------------------------- +typedef struct +{ + BYTE length; // descriptor length ( = sizeof(STRING_DSCR) ) + BYTE type; // descriptor type ( String = 3) +} STRING_DSCR; + + + +// ---------------------------------------------------------------------------- +// Setup Data Valid structure +// ---------------------------------------------------------------------------- +typedef struct SUDAV +{ + BYTE RequestType; + BYTE Request; + + union + { + WORD Word; + + struct + { + BYTE Hi; + BYTE Lo; + } Byte; + } Value; + + union + { + WORD Word; + + struct + { + BYTE Hi; + BYTE Lo; + } Byte; + } Index; +} SUDAV; + +typedef SUDAV xdata* PSUDAV; + +// ---------------------------------------------------------------------------- +// Macros +// ---------------------------------------------------------------------------- +#define min(a,b) (((a)<(b))?(a):(b)) +#define max(a,b) (((a)>(b))?(a):(b)) + +#define MSB(word) (BYTE)(((WORD)(word) >> 8) & 0xff) +#define LSB(word) (BYTE)(((WORD)(word) >> 0) & 0xff) + +#define SWAP(word) ((BYTE*)&word)[0] ^= ((BYTE*)&word)[1]; \ + ((BYTE*)&word)[1] ^= ((BYTE*)&word)[0]; \ + ((BYTE*)&word)[0] ^= ((BYTE*)&word)[1] + +#define I2C_IRQ_ENABLE() (EI2C = 1) +#define I2C_IRQ_DISABLE() (EI2C = 0) +#define I2C_IRQ_CLEAR() (EXIF &= ~0x20) +#define I2C_IRQ_FIRE() (EXIF |= 0x20) + +#define USB_IRQ_ENABLE() EUSB = 1 +#define USB_IRQ_DISABLE() EUSB = 0 +#define USB_IRQ_CLEAR() EXIF &= ~0x10 + +#define USB_IRQ_CLEAR_EP0IN() EPIRQ = IRQ_EP0IN +#define USB_IRQ_CLEAR_EP0OUT() EPIRQ = IRQ_EP0OUT +#define USB_IRQ_CLEAR_EP1IN() EPIRQ = IRQ_EP1IN +#define USB_IRQ_CLEAR_EP1OUT() EPIRQ = IRQ_EP1OUT +#define USB_IRQ_CLEAR_EP2() EPIRQ = IRQ_EP2 +#define USB_IRQ_CLEAR_EP4() EPIRQ = IRQ_EP4 +#define USB_IRQ_CLEAR_EP6() EPIRQ = IRQ_EP6 +#define USB_IRQ_CLEAR_EP8() EPIRQ = IRQ_EP8 + +#define FX2_TOG_CLEAR( a) TOGCTL = a & 0x1F; TOGCTL = (a | 0x20) & 0x3F + +#define RSM_IRQ_ENABLE() (EICON |= 0x20) +#define RSM_IRQ_DISABLE() (EICON &= ~0x20) +#define RSM_IRQ_CLEAR() (EICON &= ~0x10) + +#define FX2_STALL_EP0() EP0CS |= bmEPSTALL +#define FX2_STALL_EP1IN() EP1INCS |= bmEPSTALL +#define FX2_STALL_EP1OUT() EP1OUTCS |= bmEPSTALL +#define FX2_STALL_EP2() EP2CS |= bmEPSTALL +#define FX2_STALL_EP4() EP4CS |= bmEPSTALL +#define FX2_STALL_EP6() EP6CS |= bmEPSTALL +#define FX2_STALL_EP8() EP8CS |= bmEPSTALL + +extern const DEVICE_DSCR code DscrDevice; +extern const DEVICEQUAL_DSCR code DscrDeviceQual; +extern const CONFIG_DSCR code DscrHsConfig; +extern const CONFIG_DSCR code DscrFsConfig; +extern const STRING_DSCR code DscrString; + +extern void FX2_Disconnect(bool renum); +extern void FX2_Delay(WORD ms); + +extern bool FX2_Init(); +extern void FX2_Suspend(); +extern void FX2_Resume(); + + + +#endif diff --git a/lib/fx2lp/inc/fx2_eeprom.h b/lib/fx2lp/inc/fx2_eeprom.h new file mode 100644 index 0000000..12f8929 --- /dev/null +++ b/lib/fx2lp/inc/fx2_eeprom.h @@ -0,0 +1,14 @@ +#ifndef FX2_EEPROM_H +#define FX2_EEPROM_H + +#include +extern BYTE FX2_EEPROM_Read( WORD page, BYTE offset, BYTE length, BYTE xdata *dat); +extern BYTE FX2_EEPROM_Write( WORD page, BYTE offset, BYTE length, BYTE xdata *dat); + +extern BYTE FX2_EEPROM_ReadPage( WORD page, BYTE length, BYTE xdata *dat); +extern BYTE FX2_EEPROM_WritePage( WORD page, BYTE length, BYTE xdata *dat); + +extern BYTE FX2_EEPROM_ReadPage0( BYTE addr, BYTE length, BYTE xdata *dat); +extern BYTE FX2_EEPROM_WritePage0( BYTE addr, BYTE length, BYTE xdata *dat); + +#endif diff --git a/lib/fx2lp/inc/fx2_globals.h b/lib/fx2lp/inc/fx2_globals.h new file mode 100644 index 0000000..13a284f --- /dev/null +++ b/lib/fx2lp/inc/fx2_globals.h @@ -0,0 +1,19 @@ +#ifndef FX2_GLOBALS_H +#define FX2_GLOBALS_H + +#include + +extern xdata bool Sleep; +extern xdata bool GotSUD; +extern xdata bool Rwuen; +extern xdata bool SelfPower; + +extern bool (*fx2_ep0_hook)(); +extern bool (*fx2_ep1_hook)(); + +extern bool (*fx2_ep2_hook)(); +extern bool (*fx2_ep4_hook)(); +extern bool (*fx2_ep6_hook)(); +extern bool (*fx2_ep8_hook)(); + +#endif diff --git a/lib/fx2lp/inc/fx2_gpif.h b/lib/fx2lp/inc/fx2_gpif.h new file mode 100644 index 0000000..e9d3dce --- /dev/null +++ b/lib/fx2lp/inc/fx2_gpif.h @@ -0,0 +1,7 @@ +#ifndef FX2_GPIF_H +#define FX2_GPIF_H + +extern void fx2_gpif_init(); +extern void fx2_gpif_flowstate( int sel); + +#endif diff --git a/lib/fx2lp/inc/fx2_i2c.h b/lib/fx2lp/inc/fx2_i2c.h new file mode 100644 index 0000000..1dbee38 --- /dev/null +++ b/lib/fx2lp/inc/fx2_i2c.h @@ -0,0 +1,68 @@ +#ifndef FX2_IIC_H +#define FX2_IIC_H + +#include + +// I2C error codes +// ----------------------------------------------------------------------------- +#define I2C_OK 0x00 +#define I2C_ERROR 0x80 +#define I2C_ABORT 0xFF +#define SMB_ERROR 0xC0 + + +// I2C state machine states +// ----------------------------------------------------------------------------- +#define I2C_IDLE 0x00 +#define I2C_SENDING 0x01 +#define I2C_RECEIVING 0x02 +#define I2C_PRIME 0x03 +#define I2C_BERROR 0x04 +#define I2C_NACK 0x05 +#define I2C_STOP 0x06 +#define I2C_WAITSTOP 0x07 + + +// I2C state machine states for read operation with repeated start condition +// ----------------------------------------------------------------------------- +#define I2C_SUBADDR_HI 0x10 // sending HI(subaddr) +#define I2C_SUBADDR_LO 0x11 // sending LO(subaddr) +#define I2C_RESTART 0x12 // + + +// SMBus state machine states +// ----------------------------------------------------------------------------- +#define SMB_SENDING 0x40 +#define SMB_RECEIVING 0x41 +#define SMB_PRIME 0x43 +#define SMB_BERROR 0x44 +#define SMB_NACK 0x45 +#define SMB_STOP 0x46 +#define SMB_WAITSTOP 0x47 +#define SMB_PEC 0x48 +#define SMB_CMD_READWORD 0x50 +#define SMB_READWORD 0x51 + + +extern void fx2_i2c_init(); + +extern BYTE fx2_i2c_wait( BYTE addr); + +extern BYTE fx2_i2c_read( BYTE addr, + BYTE length, + BYTE xdata *dat); + +extern BYTE fx2_i2c_write( BYTE addr, + BYTE length, + BYTE xdata *dat); + +extern BYTE fx2_i2c_read_rsw( BYTE addr, + WORD subaddr, + BYTE length, + BYTE xdata *dat); + +extern BYTE fx2_sm_readword( BYTE addr, + BYTE command, + BYTE xdata *dat); + +#endif diff --git a/lib/fx2lp/inc/fx2_regs.h b/lib/fx2lp/inc/fx2_regs.h new file mode 100644 index 0000000..97e6ba7 --- /dev/null +++ b/lib/fx2lp/inc/fx2_regs.h @@ -0,0 +1,518 @@ +#ifndef FX2_REGS_H +#define FX2_REGS_H + +#ifdef ALLOCATE_EXTERN + #define XBYTE( name, addr) xdata volatile unsigned char name _at_ addr +#else + #define XBYTE( name, addr) extern xdata volatile unsigned char name +#endif + +// ============================================================================ +// General configuration +// ============================================================================ +XBYTE( CPUCS , 0xE600); // Control & Status +XBYTE( IFCONFIG , 0xE601); // Interface Configuration +XBYTE( PINFLAGSAB , 0xE602); // FIFO FLAGA and FLAGB Assignments +XBYTE( PINFLAGSCD , 0xE603); // FIFO FLAGC and FLAGD Assignments +XBYTE( FIFORESET , 0xE604); // Restore FIFOS to default state +XBYTE( BREAKPT , 0xE605); // Breakpoint +XBYTE( BPADDRH , 0xE606); // Breakpoint Address H +XBYTE( BPADDRL , 0xE607); // Breakpoint Address L +XBYTE( UART230 , 0xE608); // 230 Kbaud clock for T0,T1,T2 +XBYTE( FIFOPINPOLAR , 0xE609); // FIFO polarities +XBYTE( REVID , 0xE60A); // Chip Revision +XBYTE( REVCTL , 0xE60B); // Chip Revision Control + +// ============================================================================ +// Endpoint configuration registers +// ============================================================================ +XBYTE( EP1OUTCFG , 0xE610); // Endpoint 1-OUT Configuration +XBYTE( EP1INCFG , 0xE611); // Endpoint 1-IN Configuration +XBYTE( EP2CFG , 0xE612); // Endpoint 2 Configuration +XBYTE( EP4CFG , 0xE613); // Endpoint 4 Configuration +XBYTE( EP6CFG , 0xE614); // Endpoint 6 Configuration +XBYTE( EP8CFG , 0xE615); // Endpoint 8 Configuration +XBYTE( EP2FIFOCFG , 0xE618); // Endpoint 2 FIFO configuration +XBYTE( EP4FIFOCFG , 0xE619); // Endpoint 4 FIFO configuration +XBYTE( EP6FIFOCFG , 0xE61A); // Endpoint 6 FIFO configuration +XBYTE( EP8FIFOCFG , 0xE61B); // Endpoint 8 FIFO configuration +XBYTE( EP2AUTOINLENH , 0xE620); // Endpoint 2 Packet Length H (IN only) +XBYTE( EP2AUTOINLENL , 0xE621); // Endpoint 2 Packet Length L (IN only) +XBYTE( EP4AUTOINLENH , 0xE622); // Endpoint 4 Packet Length H (IN only) +XBYTE( EP4AUTOINLENL , 0xE623); // Endpoint 4 Packet Length L (IN only) +XBYTE( EP6AUTOINLENH , 0xE624); // Endpoint 6 Packet Length H (IN only) +XBYTE( EP6AUTOINLENL , 0xE625); // Endpoint 6 Packet Length L (IN only) +XBYTE( EP8AUTOINLENH , 0xE626); // Endpoint 8 Packet Length H (IN only) +XBYTE( EP8AUTOINLENL , 0xE627); // Endpoint 8 Packet Length L (IN only) +XBYTE( EP2FIFOPFH , 0xE630); // EP2 Programmable Flag trigger H +XBYTE( EP2FIFOPFL , 0xE631); // EP2 Programmable Flag trigger L +XBYTE( EP4FIFOPFH , 0xE632); // EP4 Programmable Flag trigger H +XBYTE( EP4FIFOPFL , 0xE633); // EP4 Programmable Flag trigger L +XBYTE( EP6FIFOPFH , 0xE634); // EP6 Programmable Flag trigger H +XBYTE( EP6FIFOPFL , 0xE635); // EP6 Programmable Flag trigger L +XBYTE( EP8FIFOPFH , 0xE636); // EP8 Programmable Flag trigger H +XBYTE( EP8FIFOPFL , 0xE637); // EP8 Programmable Flag trigger L +XBYTE( EP2ISOINPKTS , 0xE640); // EP2 (if ISO) IN Packets per frame (1-3) +XBYTE( EP4ISOINPKTS , 0xE641); // EP4 (if ISO) IN Packets per frame (1-3) +XBYTE( EP6ISOINPKTS , 0xE642); // EP6 (if ISO) IN Packets per frame (1-3) +XBYTE( EP8ISOINPKTS , 0xE643); // EP8 (if ISO) IN Packets per frame (1-3) +XBYTE( INPKTEND , 0xE648); // Force IN Packet End +XBYTE( OUTPKTEND , 0xE649); // Force OUT Packet End + +// ============================================================================ +// Interrupts +// ============================================================================ +XBYTE( EP2FIFOIE , 0xE650); // Endpoint 2 Flag Interrupt Enable +XBYTE( EP2FIFOIRQ , 0xE651); // Endpoint 2 Flag Interrupt Request +XBYTE( EP4FIFOIE , 0xE652); // Endpoint 4 Flag Interrupt Enable +XBYTE( EP4FIFOIRQ , 0xE653); // Endpoint 4 Flag Interrupt Request +XBYTE( EP6FIFOIE , 0xE654); // Endpoint 6 Flag Interrupt Enable +XBYTE( EP6FIFOIRQ , 0xE655); // Endpoint 6 Flag Interrupt Request +XBYTE( EP8FIFOIE , 0xE656); // Endpoint 8 Flag Interrupt Enable +XBYTE( EP8FIFOIRQ , 0xE657); // Endpoint 8 Flag Interrupt Request + +XBYTE( IBNIE , 0xE658); // IN-BULK-NAK Interrupt Enable +XBYTE( IBNIRQ , 0xE659); // IN-BULK-NAK interrupt Request + +XBYTE( NAKIE , 0xE65A); // Endpoint Ping NAK interrupt Enable +XBYTE( NAKIRQ , 0xE65B); // Endpoint Ping NAK interrupt Request + +XBYTE( USBIE , 0xE65C); // USB Int Enables +XBYTE( USBIRQ , 0xE65D); // USB Interrupt Requests + +XBYTE( EPIE , 0xE65E); // Endpoint Interrupt Enables +XBYTE( EPIRQ , 0xE65F); // Endpoint Interrupt Requests + +XBYTE( GPIFIE , 0xE660); // GPIF Interrupt Enable +XBYTE( GPIFIRQ , 0xE661); // GPIF Interrupt Request + +XBYTE( USBERRIE , 0xE662); // USB Error Interrupt Enables +XBYTE( USBERRIRQ , 0xE663); // USB Error Interrupt Requests +XBYTE( ERRCNTLIM , 0xE664); // USB Error counter and limit + +XBYTE( CLRERRCNT , 0xE665); // Clear Error Counter EC[3..0] + +XBYTE( INT2IVEC , 0xE666); // Interupt 2 (USB) Autovector +XBYTE( INT4IVEC , 0xE667); // Interupt 4 (FIFOS & GPIF) Autovector +XBYTE( INTSETUP , 0xE668); // Interrupt 2&4 Setup + +// ============================================================================ +// Input/Output +// ============================================================================ +XBYTE( PORTACFG , 0xE670); // I/O Port A Alternate Configuration +XBYTE( PORTCCFG , 0xE671); // I/O Port C Alternate Configuration +XBYTE( PORTECFG , 0xE672); // I/O Port E Alternate Configuration + +XBYTE( I2CS , 0xE678); // I2C Control & Status +XBYTE( I2DAT , 0xE679); // I2C Data +XBYTE( I2CTL , 0xE67A); // I2C Control + +XBYTE( XAUTODAT1 , 0xE67B); // Autopointer1 MOVX access +XBYTE( XAUTODAT2 , 0xE67C); // Autopointer2 MOVX access + +// ============================================================================ +// USB Control +// ============================================================================ +XBYTE( USBCS , 0xE680); // USB Control & Status +XBYTE( SUSPEND , 0xE681); // Put chip into suspend +XBYTE( WAKEUPCS , 0xE682); // Wakeup source and polarity +XBYTE( TOGCTL , 0xE683); // Toggle Control +XBYTE( USBFRAMEH , 0xE684); // USB Frame count H +XBYTE( USBFRAMEL , 0xE685); // USB Frame count L +XBYTE( MICROFRAME , 0xE686); // Microframe count, 0-7 +XBYTE( FNADDR , 0xE687); // USB Function address + +// ============================================================================ +// Endpoints +// ============================================================================ +XBYTE( EP0BCH , 0xE68A); // Endpoint 0 Byte Count H +XBYTE( EP0BCL , 0xE68B); // Endpoint 0 Byte Count L +XBYTE( EP1OUTBC , 0xE68D); // Endpoint 1 OUT Byte Count +XBYTE( EP1INBC , 0xE68F); // Endpoint 1 IN Byte Count +XBYTE( EP2BCH , 0xE690); // Endpoint 2 Byte Count H +XBYTE( EP2BCL , 0xE691); // Endpoint 2 Byte Count L +XBYTE( EP4BCH , 0xE694); // Endpoint 4 Byte Count H +XBYTE( EP4BCL , 0xE695); // Endpoint 4 Byte Count L +XBYTE( EP6BCH , 0xE698); // Endpoint 6 Byte Count H +XBYTE( EP6BCL , 0xE699); // Endpoint 6 Byte Count L +XBYTE( EP8BCH , 0xE69C); // Endpoint 8 Byte Count H +XBYTE( EP8BCL , 0xE69D); // Endpoint 8 Byte Count L + +XBYTE( EP0CS , 0xE6A0); // Endpoint Control and Status +XBYTE( EP1OUTCS , 0xE6A1); // Endpoint 1 OUT Control and Status +XBYTE( EP1INCS , 0xE6A2); // Endpoint 1 IN Control and Status +XBYTE( EP2CS , 0xE6A3); // Endpoint 2 Control and Status +XBYTE( EP4CS , 0xE6A4); // Endpoint 4 Control and Status +XBYTE( EP6CS , 0xE6A5); // Endpoint 6 Control and Status +XBYTE( EP8CS , 0xE6A6); // Endpoint 8 Control and Status + +XBYTE( EP2FIFOFLGS , 0xE6A7); // Endpoint 2 Flags +XBYTE( EP4FIFOFLGS , 0xE6A8); // Endpoint 4 Flags +XBYTE( EP6FIFOFLGS , 0xE6A9); // Endpoint 6 Flags +XBYTE( EP8FIFOFLGS , 0xE6AA); // Endpoint 8 Flags + +XBYTE( EP2FIFOBCH , 0xE6AB); // EP2 FIFO total byte count H +XBYTE( EP2FIFOBCL , 0xE6AC); // EP2 FIFO total byte count L +XBYTE( EP4FIFOBCH , 0xE6AD); // EP4 FIFO total byte count H +XBYTE( EP4FIFOBCL , 0xE6AE); // EP4 FIFO total byte count L +XBYTE( EP6FIFOBCH , 0xE6AF); // EP6 FIFO total byte count H +XBYTE( EP6FIFOBCL , 0xE6B0); // EP6 FIFO total byte count L +XBYTE( EP8FIFOBCH , 0xE6B1); // EP8 FIFO total byte count H +XBYTE( EP8FIFOBCL , 0xE6B2); // EP8 FIFO total byte count L + +XBYTE( SUDPTRH , 0xE6B3); // Setup Data Pointer high address byte +XBYTE( SUDPTRL , 0xE6B4); // Setup Data Pointer low address byte +XBYTE( SUDPTRCTL , 0xE6B5); // Setup Data Pointer Auto Mode + +XBYTE( SETUPDAT[8] , 0xE6B8); // 8 bytes of SETUP data + +// ============================================================================ +// GPIF +// ============================================================================ +XBYTE( GPIFWFSELECT , 0xE6C0); // Waveform Selector +XBYTE( GPIFIDLECS , 0xE6C1); // GPIF Done, GPIF IDLE drive mode +XBYTE( GPIFIDLECTL , 0xE6C2); // Inactive Bus, CTL states +XBYTE( GPIFCTLCFG , 0xE6C3); // CTL OUT pin drive +XBYTE( GPIFADRH , 0xE6C4); // GPIF Address H +XBYTE( GPIFADRL , 0xE6C5); // GPIF Address L + +XBYTE( GPIFTCB3 , 0xE6CE); // GPIF Transaction Count Byte 3 +XBYTE( GPIFTCB2 , 0xE6CF); // GPIF Transaction Count Byte 2 +XBYTE( GPIFTCB1 , 0xE6D0); // GPIF Transaction Count Byte 1 +XBYTE( GPIFTCB0 , 0xE6D1); // GPIF Transaction Count Byte 0 + +#define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility +#define EP2GPIFTCL GPIFTCB0 // +#define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility +#define EP4GPIFTCL GPIFTCB0 // +#define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility +#define EP6GPIFTCL GPIFTCB0 // +#define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility +#define EP8GPIFTCL GPIFTCB0 // + +XBYTE( EP2GPIFFLGSEL , 0xE6D2); // EP2 GPIF Flag select +XBYTE( EP2GPIFPFSTOP , 0xE6D3); // Stop GPIF EP2 transaction on prog. flag +XBYTE( EP2GPIFTRIG , 0xE6D4); // EP2 FIFO Trigger +XBYTE( EP4GPIFFLGSEL , 0xE6DA); // EP4 GPIF Flag select +XBYTE( EP4GPIFPFSTOP , 0xE6DB); // Stop GPIF EP4 transaction on prog. flag +XBYTE( EP4GPIFTRIG , 0xE6DC); // EP4 FIFO Trigger +XBYTE( EP6GPIFFLGSEL , 0xE6E2); // EP6 GPIF Flag select +XBYTE( EP6GPIFPFSTOP , 0xE6E3); // Stop GPIF EP6 transaction on prog. flag +XBYTE( EP6GPIFTRIG , 0xE6E4); // EP6 FIFO Trigger +XBYTE( EP8GPIFFLGSEL , 0xE6EA); // EP8 GPIF Flag select +XBYTE( EP8GPIFPFSTOP , 0xE6EB); // Stop GPIF EP8 transaction on prog. flag +XBYTE( EP8GPIFTRIG , 0xE6EC); // EP8 FIFO Trigger +XBYTE( XGPIFSGLDATH , 0xE6F0); // GPIF Data H (16-bit mode only) +XBYTE( XGPIFSGLDATLX , 0xE6F1); // Read/Write GPIF Data L & trigger transac +XBYTE( XGPIFSGLDATLNOX , 0xE6F2); // Read GPIF Data L, no transac trigger +XBYTE( GPIFREADYCFG , 0xE6F3); // Internal RDY,Sync/Async, RDY5CFG +XBYTE( GPIFREADYSTAT , 0xE6F4); // RDY pin states +XBYTE( GPIFABORT , 0xE6F5); // Abort GPIF cycles + +// ============================================================================ +// UDMA +// ============================================================================ +XBYTE( FLOWSTATE , 0xE6C6); // Defines GPIF flow state +XBYTE( FLOWLOGIC , 0xE6C7); // Defines flow/hold decision criteria +XBYTE( FLOWEQ0CTL , 0xE6C8); // CTL states during active flow state +XBYTE( FLOWEQ1CTL , 0xE6C9); // CTL states during hold flow state +XBYTE( FLOWHOLDOFF , 0xE6CA); +XBYTE( FLOWSTB , 0xE6CB); // CTL/RDY Signal to use as master data strobe +XBYTE( FLOWSTBEDGE , 0xE6CC); // Defines active master strobe edge +XBYTE( FLOWSTBHPERIOD , 0xE6CD); // Half Period of output master strobe +XBYTE( GPIFHOLDAMOUNT , 0xE60C); // Data delay shift +XBYTE( UDMACRCH , 0xE67D); // CRC Upper byte +XBYTE( UDMACRCL , 0xE67E); // CRC Lower byte +XBYTE( UDMACRCQUAL , 0xE67F); // UDMA In only, host terminated use only + +// ============================================================================ +// Endpoint Buffers +// ============================================================================ +XBYTE( EP0BUF [64] , 0xE740); // EP0 IN-OUT buffer +XBYTE( EP1OUTBUF [64] , 0xE780); // EP1-OUT buffer +XBYTE( EP1INBUF [64] , 0xE7C0); // EP1-IN buffer +XBYTE( EP2FIFOBUF [1024] , 0xF000); // 512/1024-byte EP2 buffer (IN or OUT) +XBYTE( EP4FIFOBUF [1024] , 0xF400); // 512 byte EP4 buffer (IN or OUT) +XBYTE( EP6FIFOBUF [1024] , 0xF800); // 512/1024-byte EP6 buffer (IN or OUT) +XBYTE( EP8FIFOBUF [1024] , 0xFC00); // 512 byte EP8 buffer (IN or OUT) + +// ============================================================================ +// Error Correction Code (ECC) Registers (FX2LP/FX1 only) +// ============================================================================ +XBYTE( ECCCFG , 0xE628); // ECC Configuration +XBYTE( ECCRESET , 0xE629); // ECC Reset +XBYTE( ECC1B0 , 0xE62A); // ECC1 Byte 0 +XBYTE( ECC1B1 , 0xE62B); // ECC1 Byte 1 +XBYTE( ECC1B2 , 0xE62C); // ECC1 Byte 2 +XBYTE( ECC2B0 , 0xE62D); // ECC2 Byte 0 +XBYTE( ECC2B1 , 0xE62E); // ECC2 Byte 1 +XBYTE( ECC2B2 , 0xE62F); // ECC2 Byte 2 + +// ============================================================================ +// Feature Registers (FX2LP/FX1 only) +// ============================================================================ +XBYTE( GPCR2 , 0xE50D); // Chip Features + +// ============================================================================ +// Special Function Registers (sfr) +// ============================================================================ +#include +#include +#include +#include +#include +#include +#include +#include + +// ============================================================================ +// Bit masks +// ============================================================================ +// ---------------------------------------------------------------------------- +// CPU Control & Status Register (CPUCS) +// ---------------------------------------------------------------------------- +#define bmPRTCSTB bmBIT5 +#define bmCLKSPD (bmBIT4 | bmBIT3) +#define bmCLKSPD1 bmBIT4 +#define bmCLKSPD0 bmBIT3 +#define bmCLKINV bmBIT2 +#define bmCLKOE bmBIT1 +#define bm8051RES bmBIT0 + +// ---------------------------------------------------------------------------- +// Port A (PORTACFG) +// ---------------------------------------------------------------------------- +#define bmFLAGD bmBIT7 +#define bmINT1 bmBIT1 +#define bmINT0 bmBIT0 + +// ---------------------------------------------------------------------------- +// Port C (PORTCCFG) +// ---------------------------------------------------------------------------- +#define bmGPIFA7 bmBIT7 +#define bmGPIFA6 bmBIT6 +#define bmGPIFA5 bmBIT5 +#define bmGPIFA4 bmBIT4 +#define bmGPIFA3 bmBIT3 +#define bmGPIFA2 bmBIT2 +#define bmGPIFA1 bmBIT1 +#define bmGPIFA0 bmBIT0 + +// ---------------------------------------------------------------------------- +// Port E (PORTECFG) +// ---------------------------------------------------------------------------- +#define bmGPIFA8 bmBIT7 +#define bmT2EX bmBIT6 +#define bmINT6 bmBIT5 +#define bmRXD1OUT bmBIT4 +#define bmRXD0OUT bmBIT3 +#define bmT2OUT bmBIT2 +#define bmT1OUT bmBIT1 +#define bmT0OUT bmBIT0 + +// ---------------------------------------------------------------------------- +// I2C Control & Status Register (I2CS) +// ---------------------------------------------------------------------------- +#define bmSTART bmBIT7 +#define bmSTOP bmBIT6 +#define bmLASTRD bmBIT5 +#define bmID (bmBIT4 | bmBIT3) +#define bmBERR bmBIT2 +#define bmACK bmBIT1 +#define bmDONE bmBIT0 + +// ---------------------------------------------------------------------------- +// I2C Control Register (I2CTL) +// ---------------------------------------------------------------------------- +#define bmSTOPIE bmBIT1 +#define bm400KHZ bmBIT0 + +// ---------------------------------------------------------------------------- +// Interrupt 2 (USB) Autovector Register (INT2IVEC) +// ---------------------------------------------------------------------------- +#define bmIV4 bmBIT6 +#define bmIV3 bmBIT5 +#define bmIV2 bmBIT4 +#define bmIV1 bmBIT3 +#define bmIV0 bmBIT2 + +// ---------------------------------------------------------------------------- +// USB Interrupt Request & Enable Registers (USBIE/USBIRQ) +// ---------------------------------------------------------------------------- +#define bmEP0ACK bmBIT6 +#define bmHSGRANT bmBIT5 +#define bmURES bmBIT4 +#define bmSUSP bmBIT3 +#define bmSUTOK bmBIT2 +#define bmSOF bmBIT1 +#define bmSUDAV bmBIT0 + +// ---------------------------------------------------------------------------- +// USB Interrupt Request & Enable Registers (EPIE/EPIRQ) +// ---------------------------------------------------------------------------- +#define bmEP8 bmBIT7 +#define bmEP6 bmBIT6 +#define bmEP4 bmBIT5 +#define bmEP2 bmBIT4 +#define bmEP1OUT bmBIT3 +#define bmEP1IN bmBIT2 +#define bmEP0OUT bmBIT1 +#define bmEP0IN bmBIT0 + +// ---------------------------------------------------------------------------- +// GPIF Interrupt Request & Enable Registers (GPIFIE/GPIFIRQ) +// ---------------------------------------------------------------------------- +#define bmGPIFWF bmBIT1 +#define bmGPIFDONE bmBIT0 + + +// ---------------------------------------------------------------------------- +// Breakpoint register (BREAKPT) +// ---------------------------------------------------------------------------- +#define bmBREAK bmBIT3 +#define bmBPPULSE bmBIT2 +#define bmBPEN bmBIT1 + +// ---------------------------------------------------------------------------- +// Interrupt 2 & 4 Setup (INTSETUP) +// ---------------------------------------------------------------------------- +#define bmAV2EN bmBIT3 +#define INT4IN bmBIT1 +#define bmAV4EN bmBIT0 + +// ---------------------------------------------------------------------------- +// USB Control & Status Register (USBCS) +// ---------------------------------------------------------------------------- +#define bmHSM bmBIT7 +#define bmDISCON bmBIT3 +#define bmNOSYNSOF bmBIT2 +#define bmRENUM bmBIT1 +#define bmSIGRESUME bmBIT0 + +// ---------------------------------------------------------------------------- +// Wakeup Control and Status Register (WAKEUPCS) +// ---------------------------------------------------------------------------- +#define bmWU2 bmBIT7 +#define bmWU bmBIT6 +#define bmWU2POL bmBIT5 +#define bmWUPOL bmBIT4 +#define bmDPEN bmBIT2 +#define bmWU2EN bmBIT1 +#define bmWUEN bmBIT0 + +// ---------------------------------------------------------------------------- +// End Point 0 Control & Status Register (EP0CS) +// ---------------------------------------------------------------------------- +#define bmHSNAK bmBIT7 + +// ---------------------------------------------------------------------------- +// End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) +// ---------------------------------------------------------------------------- +#define bmEPBUSY bmBIT1 +#define bmEPSTALL bmBIT0 + +// ---------------------------------------------------------------------------- +// End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) +// ---------------------------------------------------------------------------- +#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4) +#define bmEPFULL bmBIT3 +#define bmEPEMPTY bmBIT2 + +/* Endpoint Status (EP2468STAT) SFR bits */ +#define bmEP8FULL bmBIT7 +#define bmEP8EMPTY bmBIT6 +#define bmEP6FULL bmBIT5 +#define bmEP6EMPTY bmBIT4 +#define bmEP4FULL bmBIT3 +#define bmEP4EMPTY bmBIT2 +#define bmEP2FULL bmBIT1 +#define bmEP2EMPTY bmBIT0 + + +// ---------------------------------------------------------------------------- +// SETUP Data Pointer Auto Mode (SUDPTRCTL) +// ---------------------------------------------------------------------------- +#define bmSDPAUTO bmBIT0 + +// ---------------------------------------------------------------------------- +// Endpoint Data Toggle Control (TOGCTL) +// ---------------------------------------------------------------------------- +#define bmQUERYTOGGLE bmBIT7 +#define bmSETTOGGLE bmBIT6 +#define bmRESETTOGGLE bmBIT5 +#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0 + +// ---------------------------------------------------------------------------- +// IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) +// ---------------------------------------------------------------------------- +#define bmEP8IBN bmBIT5 +#define bmEP6IBN bmBIT4 +#define bmEP4IBN bmBIT3 +#define bmEP2IBN bmBIT2 +#define bmEP1IBN bmBIT1 +#define bmEP0IBN bmBIT0 + +// ---------------------------------------------------------------------------- +// PING-NAK enable and request bits (NAKIE/NAKIRQ) +// ---------------------------------------------------------------------------- +#define bmEP8PING bmBIT7 +#define bmEP6PING bmBIT6 +#define bmEP4PING bmBIT5 +#define bmEP2PING bmBIT4 +#define bmEP1PING bmBIT3 +#define bmEP0PING bmBIT2 +#define bmIBN bmBIT0 + +// ---------------------------------------------------------------------------- +// Interface Configuration bits (IFCONFIG) +// ---------------------------------------------------------------------------- +#define bmIFCLKSRC bmBIT7 +#define bm3048MHZ bmBIT6 +#define bmIFCLKOE bmBIT5 +#define bmIFCLKPOL bmBIT4 +#define bmASYNC bmBIT3 +#define bmGSTATE bmBIT2 +#define bmIFCFG1 bmBIT1 +#define bmIFCFG0 bmBIT0 + +#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1) +#define bmIFGPIF bmIFCFG1 + +// ---------------------------------------------------------------------------- +// EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) +// ---------------------------------------------------------------------------- +#define bmINFM bmBIT6 +#define bmOEP bmBIT5 +#define bmAUTOOUT bmBIT4 +#define bmAUTOIN bmBIT3 +#define bmZEROLENIN bmBIT2 +#define bmWORDWIDE bmBIT0 + +// ---------------------------------------------------------------------------- +// Chip Revision Control Bits (REVCTL) - used to ebable/disable revision +// specific features. +// ---------------------------------------------------------------------------- +#define bmNOAUTOARM bmBIT1 +#define bmSKIPCOMMIT bmBIT0 + +// ---------------------------------------------------------------------------- +// FIFO polarity (FIFOPINPOLAR) +// ---------------------------------------------------------------------------- +#define bmPKTEND bmBIT5 +#define bmSLOE bmBIT4 +#define bmSLRD bmBIT3 +#define bmSLWR bmBIT2 +#define bmEF bmBIT1 +#define bmFF bmBIT0 + +// ---------------------------------------------------------------------------- +// FIFO Reset bits (FIFORESET) +// ---------------------------------------------------------------------------- +#define bmNAKALL bmBIT7 + +// ---------------------------------------------------------------------------- +// Chip Feature Register (GPCR2) +// ---------------------------------------------------------------------------- +#define bmFULLSPEEDONLY bmBIT4 + +#endif \ No newline at end of file diff --git a/lib/fx2lp/inc/fx2_regs_sfr8x.h b/lib/fx2lp/inc/fx2_regs_sfr8x.h new file mode 100644 index 0000000..c36af67 --- /dev/null +++ b/lib/fx2lp/inc/fx2_regs_sfr8x.h @@ -0,0 +1,106 @@ +// ============================================================================ +// FX2LP SFR Registers at 0x80 - 0x8F +// ---------------------------------------------------------------------------- +// 0x80 - IOA +// 0x81 - SP +// 0x82 - DPL0 +// 0x83 - DPH0 +// 0x84 - DPL1 +// 0x85 - DPH1 +// 0x86 - DPS +// 0x87 - PCON +// 0x88 - TCON +// 0x89 - TMOD +// 0x8A - TL0 +// 0x8B - TL1 +// 0x8C - TH0 +// 0x8D - TH1 +// 0x8E - CKCON +// 0x8F - (SFUNC) ???? +// +// TODO: check documentation!!! +// ============================================================================ +#ifndef FX2REGS_SFR8X_H +#define FX2REGS_SFR8X_H + +sfr IOA = 0x80; +sfr SP = 0x81; +sfr DPL = 0x82; +sfr DPH = 0x83; +sfr DPL1 = 0x84; +sfr DPH1 = 0x85; +sfr DPS = 0x86; +sfr PCON = 0x87; +sfr TCON = 0x88; +sfr TMOD = 0x89; +sfr TL0 = 0x8A; +sfr TL1 = 0x8B; +sfr TH0 = 0x8C; +sfr TH1 = 0x8D; +sfr CKCON = 0x8E; +sfr SFUNC = 0x8F; + +sfr16 DP0 = 0x82; +sfr16 DP1 = 0x84; + +// ------------------------------------ +// PortA (0x80) +// ------------------------------------ +sbit PA0 = 0x80 + 0; +sbit PA1 = 0x80 + 1; +sbit PA2 = 0x80 + 2; +sbit PA3 = 0x80 + 3; +sbit PA4 = 0x80 + 4; +sbit PA5 = 0x80 + 5; +sbit PA6 = 0x80 + 6; +sbit PA7 = 0x80 + 7; + +// ------------------------------------ +// TCON (0x88) +// ------------------------------------ +sbit IT0 = 0x88 +0; +sbit IE0 = 0x88 +1; +sbit IT1 = 0x88 +2; +sbit IE1 = 0x88 +3; +sbit TR0 = 0x88 +4; +sbit TF0 = 0x88 +5; +sbit TR1 = 0x88 +6; +sbit TF1 = 0x88 +7; + +// ------------------------------------ +// PCON bits (0x87) +// ------------------------------------ +#define bmIDLE 0x01 +//#define bmSTOP 0x02 // ?? +//#define bmGF0 0x04 // ?? +//#define bmGF1 0x08 // ?? +#define bmSMOD0 0x80 + +// ------------------------------------ +// TMOD bits (0x89) +// ------------------------------------ +#define bmM00 0x01 +#define bmM10 0x02 +#define bmCT0 0x04 +#define bmGATE0 0x08 +#define bmM01 0x10 +#define bmM11 0x20 +#define bmCT1 0x40 +#define bmGATE1 0x80 + +// ------------------------------------ +// CKCON bits (0x8E) +// ------------------------------------ +#define bmMD0 0x01 +#define bmMD1 0x02 +#define bmMD2 0x04 +#define bmT0M 0x08 +#define bmT1M 0x10 +#define bmT2M 0x20 + +// ------------------------------------ +// SFUNC bits +// ------------------------------------ +//sbit WRS = 0x8F +0; + +#endif diff --git a/lib/fx2lp/inc/fx2_regs_sfr9x.h b/lib/fx2lp/inc/fx2_regs_sfr9x.h new file mode 100644 index 0000000..587790f --- /dev/null +++ b/lib/fx2lp/inc/fx2_regs_sfr9x.h @@ -0,0 +1,67 @@ +// ============================================================================ +// FX2LP SFR Registers at 0x90 - 0x9F +// ---------------------------------------------------------------------------- +// 0x90 - IOB +// 0x91 - EXIF +// 0x92 - MPAGE +// 0x93 - +// 0x94 - +// 0x95 - +// 0x96 - +// 0x97 - +// 0x98 - SCON0 +// 0x99 - SBUF0 +// 0x9A - AUTOPTRH1 +// 0x9B - AUTOPTRL1 +// 0x9C - +// 0x9D - AUTOPTRH2 +// 0x9E - AUTOPTRL2 +// 0x9F - +// ============================================================================ +#ifndef FX2REGS_SFR9X_H +#define FX2REGS_SFR9X_H + +sfr IOB = 0x90; +sfr EXIF = 0x91; +sfr MPAGE = 0x92; +sfr SCON0 = 0x98; +sfr SBUF0 = 0x99; +sfr AUTOPTRH1 = 0x9A; +sfr AUTOPTRL1 = 0x9B; +sfr AUTOPTRH2 = 0x9D; +sfr AUTOPTRL2 = 0x9E; + +// ------------------------------------ +// PortB (0x90) +// ------------------------------------ +sbit PB0 = 0x90 +0; +sbit PB1 = 0x90 +1; +sbit PB2 = 0x90 +2; +sbit PB3 = 0x90 +3; +sbit PB4 = 0x90 +4; +sbit PB5 = 0x90 +5; +sbit PB6 = 0x90 +6; +sbit PB7 = 0x90 +7; + +// ------------------------------------ +// SCON0 (0x98) +// ------------------------------------ +sbit RI = 0x98 +0; +sbit TI = 0x98 +1; +sbit RB8 = 0x98 +2; +sbit TB8 = 0x98 +3; +sbit REN = 0x98 +4; +sbit SM2 = 0x98 +5; +sbit SM1 = 0x98 +6; +sbit SM0 = 0x98 +7; + +// ------------------------------------ +// EXIF (0x91) +// ------------------------------------ +#define bmUSBINT 0x10 +#define bmI2CINT 0x20 +#define bmIE4 0x40 +#define bmIE5 0x80 + +#endif + diff --git a/lib/fx2lp/inc/fx2_regs_sfrAx.h b/lib/fx2lp/inc/fx2_regs_sfrAx.h new file mode 100644 index 0000000..9f0b43e --- /dev/null +++ b/lib/fx2lp/inc/fx2_regs_sfrAx.h @@ -0,0 +1,102 @@ +// ============================================================================ +// FX2LP SFR Registers at 0xA0 - 0xAF +// ---------------------------------------------------------------------------- +// 0xA0 - IOC +// 0xA1 - INT2CLR +// 0xA2 - INT4CLR +// 0xA3 - +// 0xA4 - +// 0xA5 - +// 0xA6 - +// 0xA7 - +// 0xA8 - IE +// 0xA9 - +// 0xAA - EP2468STAT +// 0xAB - EP24FIFOFLGS +// 0xAC - EP68FIFOFLGS +// 0xAD - +// 0xAE - +// 0xAF - AUTOPTRSETUP +// ============================================================================ +#ifndef FX2REGS_SFRAX_H +#define FX2REGS_SFRAX_H + +sfr IOC = 0xA0; +sfr INT2CLR = 0xA1; +sfr INT4CLR = 0xA2; +sfr IE = 0xA8; +sfr EP2468STAT = 0xAA; +sfr EP24FIFOFLGS= 0xAB; +sfr EP68FIFOFLGS= 0xAC; +sfr AUTOPTRSETUP= 0xAF; + + +// ------------------------------------ +// IOC (0xA0) +// ------------------------------------ +sbit PC0 = 0xA0 +0; +sbit PC1 = 0xA0 +1; +sbit PC2 = 0xA0 +2; +sbit PC3 = 0xA0 +3; +sbit PC4 = 0xA0 +4; +sbit PC5 = 0xA0 +5; +sbit PC6 = 0xA0 +6; +sbit PC7 = 0xA0 +7; + + +// ------------------------------------ +// IE (0xA8) +// ------------------------------------ +sbit EX0 = 0xA8 +0; +sbit ET0 = 0xA8 +1; +sbit EX1 = 0xA8 +2; +sbit ET1 = 0xA8 +3; +sbit ES0 = 0xA8 +4; +sbit ET2 = 0xA8 +5; +sbit ES1 = 0xA8 +6; +sbit EA = 0xA8 +7; + +// ------------------------------------ +// EP2468STAT (0xAA) +// ------------------------------------ +#define bmEP2E 0x01 +#define bmEP2F 0x02 +#define bmEP4E 0x04 +#define bmEP4F 0x08 +#define bmEP6E 0x10 +#define bmEP6F 0x20 +#define bmEP8E 0x40 +#define bmEP8F 0x80 + +// ------------------------------------ +// EP24FIFOFLGS (0XAB) +// ------------------------------------ +#define bmEP2FF 0x01 +#define bmEP2EF 0x02 +#define bmEP2PF 0x04 +#define bmEP4FF 0x10 +#define bmEP4EF 0x20 +#define bmEP4PF 0x40 + +// ------------------------------------ +// EP68FIFOFLGS (0XAC) +// ------------------------------------ +#define bmEP6FF 0x01 +#define bmEP6EF 0x02 +#define bmEP6PF 0x04 +#define bmEP8FF 0x10 +#define bmEP8EF 0x20 +#define bmEP8PF 0x40 + +// ------------------------------------ +// AUTOPTRSETUP (0xAF) +// ------------------------------------ +#define bmAPTREN 0x01 +#define bmAPTR1INC 0x02 +#define bmAPTR2INC 0x04 + + + + +#endif + diff --git a/lib/fx2lp/inc/fx2_regs_sfrBx.h b/lib/fx2lp/inc/fx2_regs_sfrBx.h new file mode 100644 index 0000000..aef2f59 --- /dev/null +++ b/lib/fx2lp/inc/fx2_regs_sfrBx.h @@ -0,0 +1,64 @@ +// ============================================================================ +// FX2LP SFR Registers at 0xB0 - 0xBF +// ---------------------------------------------------------------------------- +// 0xB0 - IOD +// 0xB1 - IOE +// 0xB2 - OEA +// 0xB3 - OEB +// 0xB4 - OEC +// 0xB5 - OED +// 0xB6 - OEE +// 0xB7 - +// 0xB8 - IP +// 0xB9 - +// 0xBA - EP01STAT +// 0xBB - GPIFTRIG +// 0xBC - +// 0xBD - GPIFSGL_DATH +// 0xBE - GPIFSGL_DATLX +// 0xBF - GPIFSGL_DATLNOX +// ============================================================================ +#ifndef FX2REGS_SFRBX_H +#define FX2REGS_SFRBX_H + +sfr IOD = 0xB0; +sfr IOE = 0xB1; +sfr OEA = 0xB2; +sfr OEB = 0xB3; +sfr OEC = 0xB4; +sfr OED = 0xB5; +sfr OEE = 0xB6; +sfr IP = 0xB8; + +sfr EP01STAT = 0xBA; +sfr GPIFTRIG = 0xBB; +sfr GPIFSGLDATH = 0xBD; +sfr GPIFSGLDATLX = 0xBE; +sfr GPIFSGLDATLNOX = 0xBF; + + +// ------------------------------------ +// PortD (0xB0) +// ------------------------------------ +sbit PD0 = 0xB0 +0; +sbit PD1 = 0xB0 +1; +sbit PD2 = 0xB0 +2; +sbit PD3 = 0xB0 +3; +sbit PD4 = 0xB0 +4; +sbit PD5 = 0xB0 +5; +sbit PD6 = 0xB0 +6; +sbit PD7 = 0xB0 +7; + +// ------------------------------------ +// IP bits +// ------------------------------------ +sbit PX0 = 0xB8 +0; +sbit PT0 = 0xB8 +1; +sbit PX1 = 0xB8 +2; +sbit PT1 = 0xB8 +3; +sbit PS0 = 0xB8 +4; +sbit PT2 = 0xB8 +5; +sbit PS1 = 0xB8 +6; + +#endif + diff --git a/lib/fx2lp/inc/fx2_regs_sfrCx.h b/lib/fx2lp/inc/fx2_regs_sfrCx.h new file mode 100644 index 0000000..be75204 --- /dev/null +++ b/lib/fx2lp/inc/fx2_regs_sfrCx.h @@ -0,0 +1,59 @@ +// ============================================================================ +// FX2LP SFR Registers at 0xC0 - 0xCF +// ---------------------------------------------------------------------------- +// 0xC0 - SCON1 +// 0xC1 - SBUF1 +// 0xC2 - +// 0xC3 - +// 0xC4 - +// 0xC5 - +// 0xC6 - +// 0xC7 - +// 0xC8 - T2CON +// 0xC9 - +// 0xCA - RCAP2L +// 0xCB - RCAP2H +// 0xCC - TL2 +// 0xCD - TH2 +// 0xCE - +// 0xCF - +// ============================================================================ +#ifndef FX2REGS_SFRCX_H +#define FX2REGS_SFRCX_H + +sfr SCON1 = 0xC0; +sfr SBUF1 = 0xC1; +sfr T2CON = 0xC8; +sfr RCAP2L = 0xCA; +sfr RCAP2H = 0xCB; +sfr TL2 = 0xCC; +sfr TH2 = 0xCD; + + +// ------------------------------------ +// SCON1 (0xC0) +// ------------------------------------ +sbit RI1 = 0xC0 +0; +sbit TI1 = 0xC0 +1; +sbit RB81 = 0xC0 +2; +sbit TB81 = 0xC0 +3; +sbit REN1 = 0xC0 +4; +sbit SM21 = 0xC0 +5; +sbit SM11 = 0xC0 +6; +sbit SM01 = 0xC0 +7; + + +// ------------------------------------ +// T2CON (0xC8) +// ------------------------------------ +sbit CP_RL2 = 0xC8 +0; +sbit C_T2 = 0xC8 +1; +sbit TR2 = 0xC8 +2; +sbit EXEN2 = 0xC8 +3; +sbit TCLK = 0xC8 +4; +sbit RCLK = 0xC8 +5; +sbit EXF2 = 0xC8 +6; +sbit TF2 = 0xC8 +7; + +#endif + diff --git a/lib/fx2lp/inc/fx2_regs_sfrDx.h b/lib/fx2lp/inc/fx2_regs_sfrDx.h new file mode 100644 index 0000000..d7916bf --- /dev/null +++ b/lib/fx2lp/inc/fx2_regs_sfrDx.h @@ -0,0 +1,49 @@ +// ============================================================================ +// FX2LP SFR Registers at 0xD0 - 0xDF +// ---------------------------------------------------------------------------- +// 0xD0 - PSW +// 0xD1 - +// 0xD2 - +// 0xD3 - +// 0xD4 - +// 0xD5 - +// 0xD6 - +// 0xD7 - +// 0xD8 - EICON +// 0xD9 - +// 0xDA - +// 0xDB - +// 0xDC - +// 0xDD - +// 0xDE - +// 0xDF - +// ============================================================================ +#ifndef FX2REGS_SFRDX_H +#define FX2REGS_SFRDX_H + +sfr PSW = 0xD0; +sfr EICON = 0xD8; + +// ------------------------------------ +// PSW bits +// ------------------------------------ +sbit P = 0xD0 +0; +sbit FL = 0xD0 +1; +sbit OV = 0xD0 +2; +sbit RS0 = 0xD0 +3; +sbit RS1 = 0xD0 +4; +sbit F0 = 0xD0 +5; +sbit AC = 0xD0 +6; +sbit CY = 0xD0 +7; + + +// ------------------------------------ +// EICON bits +// ------------------------------------ +sbit INT6 = 0xD8 +3; +sbit RESI = 0xD8 +4; +sbit ERESI = 0xD8 +5; +sbit SMOD1 = 0xD8 +7; + +#endif + diff --git a/lib/fx2lp/inc/fx2_regs_sfrEx.h b/lib/fx2lp/inc/fx2_regs_sfrEx.h new file mode 100644 index 0000000..161338d --- /dev/null +++ b/lib/fx2lp/inc/fx2_regs_sfrEx.h @@ -0,0 +1,37 @@ +// ============================================================================ +// FX2LP SFR Registers at 0xE0 - 0xEF +// ---------------------------------------------------------------------------- +// 0xE0 - ACC +// 0xE1 - +// 0xE2 - +// 0xE3 - +// 0xE4 - +// 0xE5 - +// 0xE6 - +// 0xE7 - +// 0xE8 - EIE +// 0xE9 - +// 0xEA - +// 0xEB - +// 0xEC - +// 0xED - +// 0xEE - +// 0xEF - +// ============================================================================ +#ifndef FX2REGS_SFREX_H +#define FX2REGS_SFREX_H + +sfr ACC = 0xE0; +sfr EIE = 0xE8; + +// ------------------------------------ +// EIE bits +// ------------------------------------ +sbit EUSB = 0xE8 +0; +sbit EI2C = 0xE8 +1; +sbit EIEX4 = 0xE8 +2; +sbit EIEX5 = 0xE8 +3; +sbit EIEX6 = 0xE8 +4; + +#endif + diff --git a/lib/fx2lp/inc/fx2_regs_sfrFx.h b/lib/fx2lp/inc/fx2_regs_sfrFx.h new file mode 100644 index 0000000..19c9a1a --- /dev/null +++ b/lib/fx2lp/inc/fx2_regs_sfrFx.h @@ -0,0 +1,37 @@ +// ============================================================================ +// FX2LP SFR Registers at 0xF0 - 0xFF +// ---------------------------------------------------------------------------- +// 0xF0 - B +// 0xF1 - +// 0xF2 - +// 0xF3 - +// 0xF4 - +// 0xF5 - +// 0xF6 - +// 0xF7 - +// 0xF8 - EIP +// 0xF9 - +// 0xFA - +// 0xFB - +// 0xFC - +// 0xFD - +// 0xFE - +// 0xFF - +// ============================================================================ +#ifndef FX2REGS_SFRFX_H +#define FX2REGS_SFRFX_H + +sfr B = 0xF0; +sfr EIP = 0xF8; + +// ------------------------------------ +// EIP bits +// ------------------------------------ +sbit PUSB = 0xF8 +0; +sbit PI2C = 0xF8 +1; +sbit EIPX4 = 0xF8 +2; +sbit EIPX5 = 0xF8 +3; +sbit EIPX6 = 0xF8 +4; + +#endif + diff --git a/lib/fx2lp/inc/fx2_syncdelay.h b/lib/fx2lp/inc/fx2_syncdelay.h new file mode 100644 index 0000000..02e5158 --- /dev/null +++ b/lib/fx2lp/inc/fx2_syncdelay.h @@ -0,0 +1,240 @@ +//----------------------------------------------------------------------------- +// File: fx2sdly.h +// Contents: EZ-USB FX2 Synchronization Delay (SYNCDELAY) Macro +// +// Enter with _IFREQ = IFCLK in kHz +// Enter with _CFREQ = CLKOUT in kHz +// +// Copyright (c) 2001 Cypress Semiconductor, All rights reserved +//----------------------------------------------------------------------------- +#include "intrins.h" + + // Registers which require a synchronization delay, see section 15.14 + // FIFORESET FIFOPINPOLAR + // INPKTEND OUTPKTEND + // EPxBCH:L REVCTL + // GPIFTCB3 GPIFTCB2 + // GPIFTCB1 GPIFTCB0 + // EPxFIFOPFH:L EPxAUTOINLENH:L + // EPxFIFOCFG EPxGPIFFLGSEL + // PINFLAGSxx EPxFIFOIRQ + // EPxFIFOIE GPIFIRQ + // GPIFIE GPIFADRH:L + // UDMACRCH:L EPxGPIFTRIG + // GPIFTRIG + + // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well... + // ...these have been replaced by GPIFTC[B3:B0] registers + +// _IFREQ can be in the range of: 5000 to 48000 +#ifndef _IFREQ +#define _IFREQ 48000 // IFCLK frequency in kHz +#endif + +// CFREQ can be any one of: 48000, 24000, or 12000 +#ifndef _CFREQ +#define _CFREQ 48000 // CLKOUT frequency in kHz +#endif + +#if( _IFREQ < 5000 ) +#error "_IFREQ too small! Valid Range: 5000 to 48000..." +#endif + +#if( _IFREQ > 48000 ) +#error "_IFREQ too large! Valid Range: 5000 to 48000..." +#endif + +#if( _CFREQ != 48000 ) +#if( _CFREQ != 24000 ) +#if( _CFREQ != 12000 ) +#error "_CFREQ invalid! Valid values: 48000, 24000, 12000..." +#endif +#endif +#endif + +// Synchronization Delay formula: see TRM section 15-14 +#define _SCYCL ( 3*(_CFREQ) + 5*(_IFREQ) - 1 ) / ( 2*(_IFREQ) ) + +#if( _SCYCL == 1 ) +#define SYNCDELAY _nop_( ) +#endif + +#if( _SCYCL == 2 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ) +#endif + +#if( _SCYCL == 3 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ); \ + _nop_( ) +#endif + +#if( _SCYCL == 4 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ) +#endif + +#if( _SCYCL == 5 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ) +#endif + +#if( _SCYCL == 6 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ) +#endif + +#if( _SCYCL == 7 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ) +#endif + +#if( _SCYCL == 8 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ) +#endif + +#if( _SCYCL == 9 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ) +#endif + +#if( _SCYCL == 10 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ) +#endif + +#if( _SCYCL == 11 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ) +#endif + +#if( _SCYCL == 12 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ) +#endif + +#if( _SCYCL == 13 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ) +#endif + +#if( _SCYCL == 14 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ) +#endif + +#if( _SCYCL == 15 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ) +#endif + +#if( _SCYCL == 16 ) +#define SYNCDELAY _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ); \ + _nop_( ) +#endif diff --git a/lib/fx2lp/inc/fx2_usart.h b/lib/fx2lp/inc/fx2_usart.h new file mode 100644 index 0000000..3b3af3f --- /dev/null +++ b/lib/fx2lp/inc/fx2_usart.h @@ -0,0 +1,45 @@ +#ifndef __FX2_USART_H__ +#define __FX2_USART_H__ + + +typedef enum _usart_cfg +{ + // ----------------------------------------------------- + // 11 bit total length configuraations + // ----------------------------------------------------- + uc8n2, // 8 data bit no parity 2 stop bit + uc8e1, // 8 data bit even parity 1 stop bit + uc8o1, // 8 data bit odd parity 1 stop bit + + // ----------------------------------------------------- + // 10 bit total length configuraations + // ----------------------------------------------------- + uc8n1, // 8 data bit no parity 1 stop +} usart_cfg; + +// USART error codes +// ----------------------------------------------------------------------------- +#define USART_OK 0x00 +#define USART_ERROR 0x80 +#define USART_ABORT 0xFF + + +// I2C state machine states +// ----------------------------------------------------------------------------- +#define USART_IDLE 0x00 +#define USART_SENDING 0x01 +#define USART_RECEIVING 0x02 +//#define I2C_PRIME 0x03 +//#define I2C_BERROR 0x04 +//#define I2C_NACK 0x05 +//#define I2C_STOP 0x06 +//#define I2C_WAITSTOP 0x07 + + + +void fx2_usart_init( unsigned int baud, usart_cfg cfg); +BYTE fx2_usart_send( BYTE length, BYTE xdata *dat, BYTE xdata *pause); + + + +#endif diff --git a/lib/fx2lp/src/fx2_conf.s51 b/lib/fx2lp/src/fx2_conf.s51 new file mode 100644 index 0000000..c9dbffd --- /dev/null +++ b/lib/fx2lp/src/fx2_conf.s51 @@ -0,0 +1,748 @@ +$NOMOD51 DEBUG +;------------------------------------------------------------------------------ +; This file is part of the RTX-51 TINY Real-Time Operating System Package +; Copyright KEIL ELEKTRONIK GmbH and Keil Software, Inc. 1991-2002 +; Version 2.02 +;------------------------------------------------------------------------------ +; CONF_TNY.A51: This code allows the configuration of the +; RTX-51 TINY Real-Time Operating System +; +; Copy this file to your project folder and add the copy to your uVision2 +; project. You can customize several parameters of RTX51 Tiny within this +; configuration file. +; +; If you use command line tools, translate this file with: +; +; Ax51 CONF_TNY.A51 +; +; If you use command line tools, link the modified CONF_TNY.OBJ file to +; your application with: +; +; Lx51 , CONF_TNY.OBJ +; +;------------------------------------------------------------------------------ +; +; RTX-51 TINY Hardware-Timer +; ========================== +; +; With the following EQU statements the initialization of the RTX-51 TINY +; Hardware-Timer can be defined (RTX-51 TINY uses the 8051 Timer 0 for +; controlling RTX-51 software timers). +; +; Note: For Cypress FX2LP it is changed to use Timer 2. +;------------------------------------------------------------------------------ + +; Define the register bank used for the timer interrupt. +INT_REGBANK EQU 1 ; default is Registerbank 1 +; +; Define Hardware-Timer tick time in 8051 machine cycles. +INT_CLOCK EQU 40000 ; default is 40000 cycles +; +; Define Round-Robin Timeout in Hardware-Timer ticks. +TIMESHARING EQU 5 ; default is 5 Hardware-Timer ticks. +; ; 0 disables Round-Robin Task Switching +; +; Long User Interrupt Routines: set to 1 if your application contains +; user interrupt functions that may take longer than a hardware timer +; interval for execution. +LONG_USR_INTR EQU 0 ; 0 user interrupts execute fast. +; ; 1 user interrupts take long execution times. + + +;------------------------------------------------------------------------------ +; +; USER CODE FOR 8051 HARDWARE TIMER INTERRUPT +; =========================================== +; +; The following macro defines the code executed on a hardware timer interrupt. +; Define instructions executed on a hardware timer interrupt. +;------------------------------------------------------------------------------ +HW_TIMER_CODE MACRO + ; Empty Macro by default + RETI + ENDM + + +;------------------------------------------------------------------------------ +; +; CODE BANKING SUPPORT +; ==================== +; +; The following EQU statement controls the code banking support for RTX51 TINY. +; +; Enable or disable code banking support +CODE_BANKING EQU 0 ; 0 (default) application uses no code banking +; ; 1 application uses code banking +; +;------------------------------------------------------------------------------ +; +; RTX-51 TINY Stack Space +; ======================= +; +; The following EQU statements defines the size of the internal RAM used +; for stack area and the minimum free space on the stack. A macro defines +; the code executed when there is there is not enough free stack on the +; CPU stack. +; +; Define the highest RAM address used for CPU stack +RAMTOP EQU 0FFH ; default is address (256-1) +; +FREE_STACK EQU 20 ; default is 20 bytes free space on stack +; ; the value 0 disables stack checking +; +STACK_ERROR MACRO + CLR EA ; disable interrupts + SJMP $ ; endless loop if stack space is exhausted + ENDM +; +; +;------------------------------------------------------------------------------ +; +; 8051 CPU IDLE CODE +; ================== +; +; Many 8051 devices provide an IDLE MODE that reduces power consumption and +; EMC. The following macro defines the code executed when there is no +; ready task in the system. The code must set the CPU into an IDLE MODE +; that stops instruction execution until an 8051 hardware interrupt occurs. +; + +; Disable or Enable CPU_IDLE CODE +CPU_IDLE_CODE EQU 0 ; 0 CPU_IDLE MACRO is not inserted + ; 1 CPU_IDLE MACRO is executed + +PCON DATA 087H ; Power Control SFR on most 8051 devices + +; Stop CPU execution until hardware interrupt; executed when there is no +; active task in the system. +CPU_IDLE MACRO + ORL PCON,#1 ; set 8051 CPU to IDLE + ENDM +; +; +;------------------------------------------------------------------------------ +;----------------- !!! End of User Configuration Part !!! ------------------ +;----------------- !!! Do not modify code sections below !!! ------------------ +;------------------------------------------------------------------------------ + +; SFR Symbols +PSW DATA 0D0H +ACC DATA 0E0H +B DATA 0F0H +SP DATA 81H +DPL DATA 82H +DPH DATA 83H + +TCON DATA 88H +TMOD DATA 89H +TL0 DATA 8AH +TL1 DATA 8BH +TH0 DATA 8CH +TH1 DATA 8DH + +IE DATA 0A8H + + +; TCON +TF1 BIT 8FH +TR1 BIT 8EH +TF0 BIT 8DH +TR0 BIT 8CH +IE1 BIT 8BH +IT1 BIT 8AH +IE0 BIT 89H +IT0 BIT 88H + +EA BIT 0AFH +ES BIT 0ACH +ET1 BIT 0ABH +EX1 BIT 0AAH +ET0 BIT 0A9H +EX0 BIT 0A8H + +; --------------------------- +T2CON DATA 0C8h; +RCAP2L DATA 0CAh +RCAP2H DATA 0CBh +TL2 DATA 0CCh +TH2 DATA 0CDh + +ET2 BIT 0A8h +5; +T2M BIT 08Eh +5; + +// -------------------------- +// T2CON bits +// -------------------------- +CP_RL2 BIT 0C8h +0 +C_T2 BIT 0C8h +1 +TR2 BIT 0C8h +2 +TF2 BIT 0C8h +7; + + +; Check Configuration Values + + + NAME ?RTX51_TINY_KERNAL + +PUBLIC ?RTX_CURRENTTASK +PUBLIC ?RTX_RAMTOP +PUBLIC os_switch_task +PUBLIC ?RTX?SET_ISR + +EXTRN NUMBER (?RTX_MAXTASKN) ; max Task Number + +?RTX_RAMTOP EQU RAMTOP +?RTX_CLOCK EQU -INT_CLOCK + +?RTX_REGISTERBANK EQU INT_REGBANK * 8 + DSEG AT ?RTX_REGISTERBANK + DS 2 ; temporary space +?RTX_SAVEACC: DS 1 +saveacc EQU R2 ; for access in interrupt service routine +?RTX_SAVEPSW: DS 1 +savepsw EQU R3 ; for access in interrupt service routine +?RTX_CURRENTTASK: DS 1 +currenttask EQU R4 ; for access in interrupt service routine + +IF (TIMESHARING <> 0) +?RTX_ROBINTIME: DS 1 +robintime EQU R5 ; for access in interrupt service routine +ENDIF + +IF (CODE_BANKING <> 0) +EXTRN DATA (?B_CURRENTBANK) +EXTRN CODE (?B_RESTORE_BANK) +ENDIF + +;------------------------------------------------ +; Table of Task Entry Pointers +;------------------------------------------------ +PUBLIC ?RTX_TASKENTRY + +?RTX?TASKENT?S SEGMENT CODE + RSEG ?RTX?TASKENT?S +?RTX_TASKENTRY: DS 2 + +;------------------------------------------------ +; Table of Stack Pointers for each task +;------------------------------------------------ +PUBLIC ?RTX_TASKSP + +?RTX?TASKSP?S SEGMENT IDATA + RSEG ?RTX?TASKSP?S +?RTX_TASKSP: DS 1 + +;------------------------------------------------ +; Table of Task Timer/State Pointers +;------------------------------------------------ +PUBLIC ?RTX_TASKSTATUS + +?RTX?TASKSTATE?S SEGMENT IDATA + RSEG ?RTX?TASKSTATE?S +?RTX_TASKSTATUS: +TimerVal: DS 1 ; Task Timer (Software Timer for each task) +TaskState: DS 1 ; Task Status (state of each Task) + +; Definitions for Bits in Task State +; TaskState.0 = Wait for Signal +; TaskState.1 = Wait for TimeOut +; TaskState.2 = Signal Flag +; TaskState.3 = TimeOut Flag +; TaskState.4 = Task Ready (Wait for Running) +; TaskState.5 = Task Active (enabled with os_create) +; TaskState.6 = Round Robin Time Out +; TaskState.7 = Run Flag + +; byte mask definitions +K_SIG EQU 1 +K_TMO EQU 2 +SIG_EVENT EQU 4 +TMO_EVENT EQU 8 +K_READY EQU 16 +K_ACTIVE EQU 32 +K_ROBIN EQU 64 +K_IVL EQU 128 ; not a task state bit; only used in os_wait +RDY_EVENT EQU 128 ; READY status flag +K_RDY EQU 128 + +; bit position definitions +B_WAITSIG EQU 0 +B_WAITTIM EQU 1 +B_SIGNAL EQU 2 +B_TIMEOUT EQU 3 +B_READY EQU 4 +B_ACTIVE EQU 5 +B_ROBIN EQU 6 +B_IVL EQU 7 ; not a task state bit; only used in os_wait +B_RDY EQU 7 + + +IF (TIMESHARING OR CPU_IDLE_CODE) +?RTX?BITS SEGMENT BIT + RSEG ?RTX?BITS +ENDIF + +IF (TIMESHARING) +?RTX_TS_DELAY: DBIT 1 ; Status bit set when task switch in progress +ENDIF + +IF (CPU_IDLE_CODE) +?RTX_ISR_SIG: DBIT 1 ; Status bit set when interrupt or os_set_signal +ENDIF + + + CSEG AT 02BH + JMP TIMERINT + +?RTX?CODE SEGMENT CODE + RSEG ?RTX?CODE + USING 0 ; Registerbank 0 for following code + +IF (FREE_STACK <> 0) +?RTX_STACKERROR: + STACK_ERROR ; User defined Stack Error Code +ENDIF + +HW_TIMER: HW_TIMER_CODE + +TIMERINT: + CLR TF2 + +IF (LONG_USR_INTR) + PUSH ACC + MOV A,PSW + ANL A,#018H + XRL A,#?RTX_REGISTERBANK + JNZ CONT_TIMINT +; avoid recursive timer interrupt + POP ACC + RETI ; Return from Recursive Timer Interrupt +CONT_TIMINT: POP ACC + +ENDIF + + CALL HW_TIMER ; Enable Interrupts again. + + MOV ?RTX_SAVEPSW,PSW + MOV PSW, #?RTX_REGISTERBANK + + + MOV saveacc, ACC ; ACC required by some Cygnal devices + + ;; ---------------------------------------------------------- + ;; On Cypress FX2LP timer 2 used in 16 bit autoload mode, so + ;; reloading the timer manualy is not necessary. + ;; ---------------------------------------------------------- + ; Update 8051 Interrupt Timer + ;CLR TR0 + ; + ;MOV A, TL0 + ;ADD A, #LOW (?RTX_CLOCK + 7) + ;MOV TL0, A + ; + ;MOV A, TH0 + ;ADDC A, #HIGH (?RTX_CLOCK + 7) + ;MOV TH0,A + ; + ;SETB TR0 + ;; ---------------------------------------------------------- + +IF (FREE_STACK <> 0) +; Check if enough free stack is available + MOV A,currenttask + ADD A,#?RTX?TASKSP?S+1 + MOV R0,A + MOV A,@R0 + CJNE currenttask,#?RTX_MAXTASKN,checkstack + MOV A,#RAMTOP +checkstack: CLR C + SUBB A,SP + CJNE A,#FREE_STACK,$+3 + JC ?RTX_STACKERROR +ENDIF + +; Update & Check Task Timers + MOV R1,#?RTX_MAXTASKN+1 + MOV R0,#?RTX?TASKSTATE?S +TIMERLOOP: DEC @R0 ; Decrement timer + MOV A,@R0 + INC R0 ; advance to TaskState + JNZ NoTimeout + CLR EA + MOV A,@R0 + JNB ACC.B_WAITTIM,NoWaitTimeout + ORL A,#(K_READY+TMO_EVENT) + MOV @R0,A +NoWaitTimeout: SETB EA +NoTimeout: INC R0 ; advance to TaskTimer + DJNZ R1,TIMERLOOP + + MOV A,saveacc + MOV PSW,savepsw + USING 0 ; Registerbank 0 for following code + +IF (TIMESHARING == 0) +; Round Robin Task Switching not required. System Interrupt ends here +?RTX?SET_ISR: +IF (CPU_IDLE_CODE) + SETB ?RTX_ISR_SIG +ENDIF + RET +ENDIF + +IF (TIMESHARING) +; Round Robin Task Switching required. Check if task generates timeout +; Check for Round Robin Timeout on the current task + JNB ?RTX_TS_DELAY,CheckRobinTime +NoRobinTimeout: +?RTX?SET_ISR: +IF (CPU_IDLE_CODE) + SETB ?RTX_ISR_SIG +ENDIF + RET +CheckRobinTime: DJNZ ?RTX_ROBINTIME,NoRobinTimeout + +?RTX_TASKSWITCHING: + PUSH ACC + PUSH PSW + PUSH B + PUSH DPH + PUSH DPL + PUSH AR0 + PUSH AR1 + PUSH AR2 + PUSH AR3 + PUSH AR4 + PUSH AR5 + PUSH AR6 + PUSH AR7 +IF (CODE_BANKING <> 0) + PUSH ?B_CURRENTBANK +ENDIF + + MOV A,?RTX_CURRENTTASK + RL A + ADD A,#?RTX?TASKSTATE?S+1 + MOV R0,A + MOV A,#K_ROBIN + CLR EA + ORL A,@R0 + MOV @R0,A + SETB EA +IF (CODE_BANKING <> 0) + SJMP os_switch_task1 +ENDIF +ENDIF + +;------------------------------------------------ +; Perform a Task-Switch +; void os_switch_task (void) +; uchar i; +; uchar limit; + +;---- Variable 'current' assigned to Register 'R6' ---- +;---- Variable 'next' assigned to Register 'R7' ---- +;---- Variable 'i' assigned to Register 'R0' ---- +;---- Variable 'limit' assigned to Register 'R5' ---- +; +;------------------------------------------------ + +os_switch_task: + +IF (CODE_BANKING <> 0) + PUSH ?B_CURRENTBANK +ENDIF + +os_switch_task1: + +; next = current; +IF (TIMESHARING <> 0) + SETB ?RTX_TS_DELAY ; Delay Task Switching +ENDIF + MOV A,?RTX_CURRENTTASK + MOV R7,A +; while (1) { + RL A + ADD A,#?RTX?TASKSTATE?S+1 + MOV R0,A +?C0001: +; if (++next == MAXTASKN+1) next = 0; + INC R7 + INC R0 + INC R0 +IF (CPU_IDLE_CODE) + MOV A,R7 + CJNE A,?RTX_CURRENTTASK,NoIDLE + JBC ?RTX_ISR_SIG,NoIDLE + CPU_IDLE ; CPU sleep +NoIDLE: +ENDIF + CJNE R7,#?RTX_MAXTASKN+1,?C0003 + MOV R7,#0 + MOV R0,#?RTX?TASKSTATE?S+1 +?C0003: +; if (STATE[next].st & K_READY) break; + MOV A,@R0 + JNB ACC.B_READY,?C0001 +; } +; + +PUBLIC ?RTX_NEXTID +PUBLIC ?RTX_NEXTTASK + +?RTX_NEXTID EQU AR7 +?RTX_NEXTTASK: NOP ; for Debugging + +; while (current < next) { +?C0005: + MOV A,?RTX_CURRENTTASK + CLR C + SUBB A,R7 + JNC ?C0011 + +; current++; + INC ?RTX_CURRENTTASK +; i = STKP[current]; + MOV A,#?RTX?TASKSP?S + ADD A,?RTX_CURRENTTASK + MOV R0,A + MOV A,@R0 + MOV R5,A +; STKP[current] = SP; + MOV @R0,SP +; if (current == MAXTASKN) limit = RAMTOP; + INC R0 + MOV A,@R0 + MOV R6,?RTX_CURRENTTASK + CJNE R6,#?RTX_MAXTASKN,?C0007 + MOV A,#RAMTOP +?C0007: + XCH A,R5 + MOV R0,A +; else limit = STKP[current+1]; +; +; while (i != limit) { +?C0009: + MOV A,R0 + XRL A,R5 + JZ ?C0005 +; SP++; +; i++; +; STACK[SP] = STACK[i]; + INC R0 + MOV A,@R0 + PUSH ACC + SJMP ?C0009 +; } +; } +?C0011: +; +; while (current > next) { + MOV A,?RTX_CURRENTTASK + SETB C + SUBB A,R7 + JC ?C0012 + + MOV A,?RTX_CURRENTTASK + ADD A,#?RTX?TASKSP?S+1 + MOV R0,A + MOV A,@R0 +; if (current == (MAXTASKN)) i = RAMTOP; +; else i = STKP[current+1]; + MOV R6,?RTX_CURRENTTASK + CJNE R6,#?RTX_MAXTASKN,?C0013 + MOV A,#RAMTOP +?C0013: + MOV R5,A +; limit = STKP[current]; + DEC R0 + MOV A,@R0 + XCH A,R5 + MOV R0,A +; +; while (SP != limit) { +?C0015: + MOV A,SP + XRL A,R5 + JZ ?C0016 +; STACK[i] = STACK[SP]; +; i--; +; SP--; + POP ACC + MOV @R0,A + DEC R0 + + SJMP ?C0015 +?C0016: +; } +; STKP[current] = i; + MOV A,?RTX_CURRENTTASK + ADD A,#?RTX?TASKSP?S + XCH A,R0 + MOV @R0,A +; current--; + DEC ?RTX_CURRENTTASK + SJMP ?C0011 +?C0012: +; } + +; RoundRobinTime = ?RTX_TIMESHARING +IF (TIMESHARING) + MOV ?RTX_ROBINTIME,#TIMESHARING +ENDIF + +; if (STATE[current].st & K_ROBIN) goto RobinOn; + MOV A,?RTX_CURRENTTASK + RL A + ADD A,#?RTX?TASKSTATE?S+1 + MOV R0,A + MOV R7,#SIG_EVENT + CLR EA + MOV A,@R0 +IF (TIMESHARING) + JBC ACC.B_ROBIN,RobinOn +ENDIF +; if ((STATE[current].st & K_SIG) && (STATE[current].st & SIG_EVENT) +; goto SignalOn; + JNB ACC.B_WAITSIG,SignalOff + JBC ACC.B_SIGNAL,SignalOn +SignalOff: +; if ((STATE[current].st & K_TMO) && (STATE[current].st & TMO_EVENT) +; goto TimeOutOn; + MOV R7,#0 ; No Event + JNB ACC.B_WAITTIM,NoEvent + JNB ACC.B_TIMEOUT,NoEvent +TimeOutOn: + MOV R7,#TMO_EVENT + ANL A,#0F4H +SignalOn: +NoEvent: ANL A,#NOT (K_RDY + K_TMO + K_SIG) ; Clear RDY + Wait bits + XCH A,@R0 + SETB EA + + ANL A,#K_RDY + ORL AR7,A +IF (TIMESHARING <> 0) + IF (CODE_BANKING) + POP ACC + CALL ?B_RESTORE_BANK + ENDIF + CLR ?RTX_TS_DELAY + RET +ELSE + IF (CODE_BANKING) + POP ACC + JMP ?B_RESTORE_BANK + ENDIF + RET +ENDIF + + + +;------------------------------------------------ +IF (TIMESHARING <> 0) +RobinOn: MOV @R0,A + SETB EA +IF (CODE_BANKING) + POP ACC + CALL ?B_RESTORE_BANK +ENDIF + POP AR7 + POP AR6 + POP AR5 + POP AR4 + POP AR3 + POP AR2 + POP AR1 + POP AR0 + POP DPL + POP DPH + POP B + POP PSW + POP ACC + CLR ?RTX_TS_DELAY + RET ; Restart Task +ENDIF +; } +; } + + + +;;; =========================================================================== +;;; Start RTX-51 Tiny Kernel +;;; =========================================================================== +EXTRN CODE (?C_STARTUP) + + +PUBLIC main + +main: + MOV R0, #?RTX?TASKSP?S + MOV @R0, SP + MOV A, #?RTX_MAXTASKN + JZ main2 + + MOV R7, A +main1: INC R0 + MOV @R0,#RAMTOP + DJNZ R7,main1 + +main2: MOV R7,#?RTX_MAXTASKN+1 + CLR A + MOV R0,#?RTX?TASKSTATE?S + +main1x: + MOV @R0, A + INC R0 + MOV @R0, A + INC R0 + DJNZ R7,main1x + + MOV R0, #?RTX?TASKSTATE?S+1 + MOV @R0, #K_ACTIVE+K_READY + MOV DPTR, #?RTX?TASKENT?S + MOV A, #1 + MOVC A, @A+DPTR + PUSH ACC + CLR A + MOVC A,@A+DPTR + PUSH ACC + +IF (TIMESHARING <> 0) + MOV ?RTX_ROBINTIME, #TIMESHARING +ENDIF + + ; ------------------------------------------------- + ; Initialize Timer 2 + ; ------------------------------------------------- + MOV RCAP2L, #LOW (?RTX_CLOCK) + MOV RCAP2H, #HIGH(?RTX_CLOCK) + + MOV TL2, RCAP2L + MOV TH2, RCAP2H + + MOV T2CON, #00H + + SETB ET2 + SETB TR2 + +; Timer 0 initialization +; ORL TMOD, #01H ; Timer 0 Mode 1 +; MOV TL0, #LOW (?RTX_CLOCK) +; MOV TH0, #HIGH(?RTX_CLOCK) +; SETB TR0 +; SETB ET0 + + ; ------------------------------------------------- + ; Start task 0 by enabling interrupts + ; ------------------------------------------------- + SETB EA + RET + + +;------------------------------------------------ + +PUBLIC ?RTX_TASKIDX +?RTX_TASKIDX: DB ?RTX_MAXTASKN ; for Debugging + + END diff --git a/lib/fx2lp/src/fx2_delay.c b/lib/fx2lp/src/fx2_delay.c new file mode 100644 index 0000000..9e32d0b --- /dev/null +++ b/lib/fx2lp/src/fx2_delay.c @@ -0,0 +1,23 @@ +#include +#include + +extern void FX2_Delay1ms(); + +// ============================================================================ +// FX2_Delay +// ============================================================================ +void FX2_Delay( WORD ms) +{ + // ---------------------------------------------------- + // Adjust the delay based on the CPU clock. + // FX2_Delay1ms() assumes a 24 MHz clock. + // ---------------------------------------------------- + if((CPUCS & bmCLKSPD) == 0) // 12 MHz + ms = (ms +1) >> 1; + + else if(( CPUCS & bmCLKSPD) == bmCLKSPD1) // 48 MHz + ms = ms << 1; + + while(ms--) + FX2_Delay1ms(); +} diff --git a/lib/fx2lp/src/fx2_delay1ms.s51 b/lib/fx2lp/src/fx2_delay1ms.s51 new file mode 100644 index 0000000..fb060c8 --- /dev/null +++ b/lib/fx2lp/src/fx2_delay1ms.s51 @@ -0,0 +1,29 @@ + NAME DELAY1MS + PUBLIC FX2_Delay1ms + +FX2LP segment code + + rseg FX2LP + +DPS DATA 086H + + ;; ==================================================================== + ;; Delay for 1 millisecond (1000 microseconds). + ;; 10 cycles * 166.6 ns per cycle is 1.66 microseconds per loop. + ;; 1000 microseconds / 1.66 = 602 [assumes 24 MHz clock]. + ;; ==================================================================== +FX2_Delay1ms: + mov a, #0 + mov DPS, a + mov dptr,#(0ffffh -602) + mov r4,#5 + +loop: + inc dptr ; 3 cycles + mov a, dpl ; 2 cycles + orl a, dph ; 2 cycles + jnz loop ; 3 cycles + + ret + + END \ No newline at end of file diff --git a/lib/fx2lp/src/fx2_disconnect.c b/lib/fx2lp/src/fx2_disconnect.c new file mode 100644 index 0000000..d913f84 --- /dev/null +++ b/lib/fx2lp/src/fx2_disconnect.c @@ -0,0 +1,35 @@ +#include +#include + +// ============================================================================ +// FX2_Disconnect +// ============================================================================ +void FX2_Disconnect(bool renum) +{ + // ---------------------------------------------------- + // If renumerate (i.e. 8051 will handle SETUP commands) + // disconnect from USB and set the renumerate bit. + // ---------------------------------------------------- + if(renum) + USBCS |= (bmDISCON | bmRENUM); + else + USBCS |= bmDISCON; + + // ---------------------------------------------------- + // Wait 1500 ms + // ---------------------------------------------------- + FX2_Delay(1500); + + // ---------------------------------------------------- + // Clear any pending interrupt requests. They are for + // our old life. + // ---------------------------------------------------- + USBIRQ = 0xFF; + EPIRQ = 0xFF; + USB_IRQ_CLEAR(); + + // ---------------------------------------------------- + // Reconnect USB + // ---------------------------------------------------- + USBCS &= ~bmDISCON; +} diff --git a/lib/fx2lp/src/fx2_eeprom.c b/lib/fx2lp/src/fx2_eeprom.c new file mode 100644 index 0000000..7574c40 --- /dev/null +++ b/lib/fx2lp/src/fx2_eeprom.c @@ -0,0 +1,123 @@ +#include +#include + +#define EEPROM_ADDR 0x51 + +BYTE xdata buffer[34]; +WORD xdata address; + + +// ================================================================================================ +// Read EEPROM data +// ================================================================================================ +BYTE FX2_EEPROM_Read( WORD page, BYTE offset, BYTE length, BYTE xdata *dat) +{ + BYTE rc; + + address = (page << 5) + (offset & 0x1F); + length = (length > 32) ? 32 : length; + + if((rc = fx2_i2c_write( EEPROM_ADDR, 2, (BYTE xdata *) &address)) == I2C_OK) + rc = fx2_i2c_read( EEPROM_ADDR, length, dat); + + return rc; +} + +// ================================================================================================ +// Write EEPROM data +// ================================================================================================ +BYTE FX2_EEPROM_Write( WORD page, BYTE offset, BYTE length, BYTE xdata *dat) +{ + BYTE rc = 0xcc; + WORD i; + + length = (length > 32) ? 32 : length; + *(WORD xdata*)buffer = (page << 5) + (offset & 0x1F); + + for( i=0; i 32) ? 32 : length; + + if((rc = fx2_i2c_write( EEPROM_ADDR, 2, (BYTE xdata *) &address)) == I2C_OK) + rc = fx2_i2c_read( EEPROM_ADDR, length, dat); + + return rc; +} + +// ================================================================================================ +// Write EEPROM data to page N +// ================================================================================================ +BYTE FX2_EEPROM_WritePage( WORD page, BYTE length, BYTE xdata *dat) +{ + BYTE rc = 0xcc; + WORD i; + + length = (length > 32) ? 32 : length; + *(WORD xdata*)buffer = page << 5; + + for( i=0; i +#include + +xdata bool Sleep; +xdata bool GotSUD; +xdata bool Rwuen; +xdata bool SelfPower; diff --git a/lib/fx2lp/src/fx2_gpif.c b/lib/fx2lp/src/fx2_gpif.c new file mode 100644 index 0000000..27d33de --- /dev/null +++ b/lib/fx2lp/src/fx2_gpif.c @@ -0,0 +1,107 @@ +#include +#include +#include + +#include + +extern const char code InitData[]; +extern const char code WaveData[]; +extern const char code FlowStates[]; + +// ============================================================================ +// Init +// +// todo: +// PORTC bits (GPIF address bits) + +// ============================================================================ +void fx2_gpif_init() +{ + int i; + + unsigned char code *ptr1; + unsigned char xdata *ptr2; + + // --------------------------------------------------------- + // 8051 doesn't have access to waveform memories until the + // part is in GPIF mode. + // + // bit[7] (IFCLKSRC) = 1 : internal clock source + // bit[6] (xMHz) = 1 : 48 MHz + // bit[5] (IFCLKOE) = 1 : enable IFCLK output + // bit[4] (IFCLKPOL) = 0 : don't invert IFCLK + // bit[3] (ASYNC) = 0 : master synchronous + // bit[2] (GSTATE) = 1 : GPIF state -> PORTE[2:0] + // bit[1:0] (IFCFG) = 2 : GPIF mode + // --------------------------------------------------------- + IFCONFIG = 0xe2; + + // --------------------------------------------------------- + // abort any waveforms pending + // --------------------------------------------------------- + GPIFABORT = 0xFF; + + // --------------------------------------------------------- + // setup GPIF + // --------------------------------------------------------- + GPIFREADYCFG = InitData[0]; + GPIFCTLCFG = InitData[1]; + GPIFIDLECS = InitData[2]; + GPIFIDLECTL = InitData[3]; + GPIFWFSELECT = InitData[5]; + GPIFREADYSTAT = InitData[6]; + + // --------------------------------------------------------- + // use dual autopointer feature + // --------------------------------------------------------- +// AUTOPTRSETUP = 7; // increment both pointers + // warning: this introduces pdata + // holes at E67B (XAUTODAT1) + // and E67C (XAUTODAT2) + + // --------------------------------------------------------- + // transfer waveform data + // --------------------------------------------------------- + ptr1 = WaveData; + ptr2 = 0xE400; + + for( i=0; i<128; i++) + ptr2[i] = ptr1[i]; + + // --------------------------------------------------------- + // configure GPIF address pins + // --------------------------------------------------------- + // PORTCCFG = 0xFF; // PC[7:0] -> GPIFADR[7:0] + // PORTECFG |= 0x80; // PE[8] -> GPIFADR[8] + // + // OEC = 0xFF; // PC[7:0] output + // OEE |= 0x80; // PE[8] output + + // --------------------------------------------------------- + // GPIF address pins update when GPIFADRH/L writen + // --------------------------------------------------------- + // GPIFADRH = 0x00; SYNCDELAY; + // GPIFADRL = 0x00; SYNCDELAY; + + // --------------------------------------------------------- + // configure GPIF flowstate registers for Wave 0 + // --------------------------------------------------------- + fx2_gpif_flowstate(0); +} + +// ============================================================================ +// ============================================================================ +void fx2_gpif_flowstate( int sel) +{ + if( sel >= 0 && sel <4) + { + FLOWSTATE = FlowStates[sel*9+0]; SYNCDELAY; + FLOWLOGIC = FlowStates[sel*9+1]; SYNCDELAY; + FLOWEQ0CTL = FlowStates[sel*9+2]; SYNCDELAY; + FLOWEQ1CTL = FlowStates[sel*9+3]; SYNCDELAY; + FLOWHOLDOFF = FlowStates[sel*9+4]; SYNCDELAY; + FLOWSTB = FlowStates[sel*9+5]; SYNCDELAY; + FLOWSTBEDGE = FlowStates[sel*9+6]; SYNCDELAY; + FLOWSTBHPERIOD = FlowStates[sel*9+7]; SYNCDELAY; + } +} \ No newline at end of file diff --git a/lib/fx2lp/src/fx2_i2c.c b/lib/fx2lp/src/fx2_i2c.c new file mode 100644 index 0000000..0e647b4 --- /dev/null +++ b/lib/fx2lp/src/fx2_i2c.c @@ -0,0 +1,484 @@ +#include +#include +#include +//#include + +typedef struct +{ + BYTE length; + BYTE count; + BYTE status; + + BYTE i2caddr; // + BYTE subaddr[2]; // for read with repeated start condition + + BYTE address; // SMBus address + BYTE cmd; // SMBus command + + BYTE xdata *dat; +} I2CPACKET; + +I2CPACKET volatile I2CPacket; + +static bool i2c_read( BYTE addr, BYTE length, BYTE xdata *dat); +static bool i2c_write( BYTE addr, BYTE length, BYTE xdata *dat); + +static bool i2c_read_rsw( BYTE addr, WORD subaddr,BYTE length, BYTE xdata *dat); + + + +// ================================================================================================= +// Init +// ================================================================================================= +void fx2_i2c_init() +{ + I2CPacket.length= 0; + I2CPacket.count = 0; + I2CPacket.status= I2C_IDLE; + + I2CTL &= ~bm400KHZ; // 100 kHz + +// I2CTL |= bm400KHZ; // 400 kHz +// I2CTL |= bmSTOPIE; // Enable I2C STOP interrupt + + PI2C = 1; + EI2C = 1; // Enable I2C interrupt +} + +// ================================================================================================= +// wait for I2C operation finish +// ================================================================================================= +static BYTE i2c_wait() +{ + while( true) + { + switch( I2CPacket.status) + { + case I2C_IDLE: + return I2C_OK; + + case I2C_ABORT: + I2CPacket.status = I2C_IDLE; + return I2C_ABORT; + + case I2C_NACK: + I2CPacket.status = I2C_IDLE; + return I2C_NACK; + + case I2C_BERROR: + I2CPacket.status = I2C_IDLE; + return I2C_BERROR; + } + } +} + +// ================================================================================================= +// Read with Repeated Start condition (16 bit subaddress) +// ================================================================================================= +BYTE fx2_i2c_read_rsw( BYTE addr, WORD subaddr, BYTE length, BYTE xdata *dat) +{ + BYTE rc = I2C_ERROR; + + if( i2c_read_rsw( addr, subaddr, length, dat)) + rc = i2c_wait(); + + return rc; +} + + +// ================================================================================================= +// Read +// ================================================================================================= +BYTE fx2_i2c_read( BYTE addr, BYTE length, BYTE xdata *dat) +{ + BYTE rc = I2C_ERROR; + + if( i2c_read( addr, length, dat)) + rc = i2c_wait(); + + return rc; +} + +// ================================================================================================= +// Write +// ================================================================================================= +BYTE fx2_i2c_write( BYTE addr, BYTE length, BYTE xdata *dat) +{ + BYTE rc = I2C_ERROR; + + if( i2c_write( addr, length, dat)) + { + while( true) + { + switch( I2CPacket.status) + { + case I2C_IDLE: + return I2C_OK; + + case I2C_NACK: + I2CPacket.status = I2C_IDLE; + return I2C_NACK; + + case I2C_BERROR: + I2CPacket.status = I2C_IDLE; + return I2C_BERROR; + } + } + } + + return rc; +} + +// ================================================================================================= +// Wait +// ================================================================================================= +BYTE fx2_i2c_wait( BYTE addr) +{ + BYTE cnt; + BYTE rc; + + cnt = 200; // "timeout" is 200 cycles + EI2C = 0; // disable i2c interrupts + + while( I2CS & bmSTOP) + ; + + do + { + // -------------------------------------- + // Generate START condition and send I2C + // address. + // -------------------------------------- + I2CS = I2CS | bmSTART; + I2DAT = addr << 1; + + // -------------------------------------- + // Wait for end of sending. + // -------------------------------------- + while( !(I2CS & bmDONE)) + ; + + // -------------------------------------- + // Generate STOP condition + // -------------------------------------- + I2CS = I2CS | bmSTOP; + + // -------------------------------------- + // Wait for stop condition finishing. + // -------------------------------------- + while( (I2CS & bmSTOP)) + ; + + // -------------------------------------- + // Decrement "timeout" counter. + // -------------------------------------- + cnt--; + } while( !(I2CS & bmACK) && cnt); + + I2CPacket.status = I2C_IDLE; + + rc = (I2CS & bmACK) ? I2C_OK : I2C_NACK; + + EI2C = 1; // enable I2C interrupts + + return rc; +} + + + +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +// SMBus implementation +// +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +BYTE fx2_sm_readword( BYTE addr, BYTE command, BYTE xdata *dat) +{ + BYTE rc = I2C_ERROR; + + while(I2CS & bmSTOP) + ; + + if( I2CPacket.status == I2C_IDLE) + { + I2CS |= bmSTART; + I2DAT = addr << 1; + + I2CPacket.address = addr; + I2CPacket.count = 0; + I2CPacket.cmd = command; + I2CPacket.dat = dat; + I2CPacket.length = 2; + I2CPacket.status = SMB_CMD_READWORD; + + + while( true) + { + switch( I2CPacket.status) + { + case I2C_IDLE: + return I2C_OK; + + case I2C_ABORT: + I2CPacket.status = I2C_IDLE; + return I2C_ABORT; + + case I2C_NACK: + I2CPacket.status = I2C_IDLE; + return I2C_NACK; + + case I2C_BERROR: + I2CPacket.status = I2C_IDLE; + return I2C_BERROR; + } + } + } + + return rc; +} + + + +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +// INTERNAL ROUTINES +// +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +// ================================================================================================= +// i2c_write +// ================================================================================================= +static bool i2c_write( BYTE addr, BYTE length, BYTE xdata *dat) +{ + while( I2CS & bmSTOP) + ; + + if( I2CPacket.status == I2C_IDLE) + { + I2CS |= bmSTART; + I2DAT = addr << 1; + + I2CPacket.count = 0; + I2CPacket.dat = dat; + I2CPacket.length = length; + I2CPacket.status = I2C_SENDING; + + return true; + } + + return false; +} + +// ================================================================================================= +// i2c_read +// ================================================================================================= +static bool i2c_read( BYTE addr, BYTE length, BYTE xdata *dat) +{ + while( I2CS & bmSTOP) + ; + + if( I2CPacket.status == I2C_IDLE) + { + I2CS |= bmSTART; + I2DAT = (addr << 1) | 0x01; + + I2CPacket.count = 0; + I2CPacket.dat = dat; + I2CPacket.length = length; + I2CPacket.status = I2C_PRIME; + + return true; + } + + return false; +} + +// ================================================================================================= +// i2c_read_rs +// ================================================================================================= +static bool i2c_read_rsw( BYTE addr, WORD subaddr, BYTE length, BYTE xdata *dat) +{ + while( I2CS & bmSTOP) + ; + + if( I2CPacket.status == I2C_IDLE) + { + I2CS |= bmSTART; + I2DAT = addr << 1; + + I2CPacket.i2caddr = addr; + + I2CPacket.subaddr[0]= subaddr >> 8; + I2CPacket.subaddr[1]= subaddr; + + I2CPacket.count = 0; + I2CPacket.dat = dat; + I2CPacket.length = length; + I2CPacket.status = I2C_SUBADDR_HI; + + return true; + } + + return false; +} + + + +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +// I2C INTERRUPT HANDLER +// +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +// ================================================================================================= +// i2c_isr +// +// TODO: IMplement I2C_ABORT +// ================================================================================================= +void i2c_isr() interrupt 9 +{ + BYTE PEC; + + // ------------------------------------------------------------------------ + // BUS error. Arbitration lost. + // ------------------------------------------------------------------------ + if( I2CS & bmBERR) + { + I2CS |= bmSTOP; + I2CPacket.status = I2C_BERROR; + } + + // ------------------------------------------------------------------------ + // NACK + // ------------------------------------------------------------------------ + + else if((!(I2CS & bmACK)) && (I2CPacket.status != I2C_RECEIVING)) + { + I2CS |= bmSTOP; + I2CPacket.status = I2C_NACK; + } + + else + { + switch( I2CPacket.status) + { + case SMB_CMD_READWORD: + I2CPacket.count = 0; + I2CPacket.status = SMB_READWORD; + I2DAT = I2CPacket.cmd; + break; + + case SMB_READWORD: + switch( I2CPacket.count) + { + case 0: + I2CPacket.count = 1; + I2CS |= bmSTART; + I2DAT = (I2CPacket.address << 1) | 0x01; + break; + + // address sent, trigger next byte read with a dummy read + case 1: + I2CPacket.count = 2; + I2CPacket.dat[0] = I2DAT; + break; + + // read low byte + case 2: + I2CPacket.count = 3; + I2CPacket.dat[0] = I2DAT; + break; + + // read high byte + case 3: + I2CPacket.count = 4; + I2CPacket.dat[1] = I2DAT; + break; + + case 4: + I2CS |= bmSTOP; + PEC = I2DAT; + I2CPacket.status = I2C_IDLE; + break; + } + + break; + + case I2C_SENDING: + I2DAT = I2CPacket.dat[I2CPacket.count++]; + + if( I2CPacket.count == I2CPacket.length) + I2CPacket.status = I2C_STOP; + + break; + + case I2C_PRIME: + I2CPacket.dat[I2CPacket.count] = I2DAT; + I2CPacket.status = I2C_RECEIVING; + + if( I2CPacket.length == 1) + I2CS |= bmLASTRD; + + break; + + case I2C_RECEIVING: + if( I2CPacket.count == I2CPacket.length -2) + I2CS |= bmLASTRD; + + if( I2CPacket.count == I2CPacket.length -1) + { + I2CS |= bmSTOP; + I2CPacket.status = I2C_IDLE; + } + + I2CPacket.dat[I2CPacket.count++] = I2DAT; + break; + + // read with repeated start + // --------------------------------------------- + case I2C_SUBADDR_HI: + I2DAT = I2CPacket.subaddr[0]; + I2CPacket.status = I2C_SUBADDR_LO; + break; + + case I2C_SUBADDR_LO: + I2DAT = I2CPacket.subaddr[1]; + I2CPacket.status = I2C_RESTART; + break; + + case I2C_RESTART: + I2CS |= bmSTART; + I2DAT = (I2CPacket.i2caddr << 1) | 0x01; + + I2CPacket.status = I2C_PRIME; + break; + + + // --------------------------------------------- + case I2C_STOP: + I2CS |= bmSTOP; + I2CPacket.status = I2C_IDLE; + break; + + case I2C_WAITSTOP: + I2CPacket.status = I2C_IDLE; + break; + + } + } + + EXIF &= ~0x20; +} + diff --git a/lib/fx2lp/src/fx2_init.c b/lib/fx2lp/src/fx2_init.c new file mode 100644 index 0000000..aed64e9 --- /dev/null +++ b/lib/fx2lp/src/fx2_init.c @@ -0,0 +1,61 @@ +#include +#include +#include + +// ============================================================================ +// FX2_Init +// +// Standard FX2 initialization. +// ============================================================================ +bool FX2_Init(void) +{ + // -------------------------------------------------------------- + // Initialize hardware + // + // - Set CPU clock to 48 MHz. + // + // bmCLKSPD0: 24 MHz + // bmCLKSPD1: 48 MHz + // -------------------------------------------------------------- + CPUCS |= bmCLKSPD1; SYNCDELAY; + + // -------------------------------------------------------------- + // - Set IFCLK to CLK (internal clock is 48 MHz) + // - Set PORT mode on all pin. + // -------------------------------------------------------------- + IFCONFIG = bmIFCLKSRC | bm3048MHZ; SYNCDELAY; // 48 MHz + IFCONFIG |= 0x20; SYNCDELAY; // Enable IFCLK + IFCONFIG &= 0xFC; SYNCDELAY; // Port mode + + // -------------------------------------------------------------- + // No endpoints are used + // -------------------------------------------------------------- + EP1INCFG = 0x20; SYNCDELAY; // invalid, in, bulk, 64, 1x + EP1OUTCFG = 0x20; SYNCDELAY; // invalid, out, bulk, 64, 1x + + EP2CFG = 0x22; SYNCDELAY; // invalid, out, bulk, 512, 2x + EP6CFG = 0x22; SYNCDELAY; // invalid, out, bulk, 512, 2x + EP4CFG = 0x20; SYNCDELAY; // invalid, out, bulk, 512, 2x + EP8CFG = 0x20; SYNCDELAY; // invalid, out, bulk, 512, 2x + + // -------------------------------------------------------------- + // FIFO configuration + // + // (temp: switch off WORDWIDE bit) + // -------------------------------------------------------------- + EP2FIFOCFG = 0x00; + EP4FIFOCFG = 0x00; + EP6FIFOCFG = 0x00; + EP8FIFOCFG = 0x00; + + // -------------------------------------------------------------- + // IO PORTA Alternate Configuration + // + // PA7 - standard IO, not FALGD nor SLCS + // PA1 - standard IO, not INT1 + // PA0 - standard IO, not INT0 + // -------------------------------------------------------------- + PORTACFG = 0x00; SYNCDELAY; + + return true; +} diff --git a/lib/fx2lp/src/fx2_jmptbl.s51 b/lib/fx2lp/src/fx2_jmptbl.s51 new file mode 100644 index 0000000..249896b --- /dev/null +++ b/lib/fx2lp/src/fx2_jmptbl.s51 @@ -0,0 +1,109 @@ +ISR MACRO routine + ljmp routine + nop + ENDM + + NAME UsbJmpTbl + + EXTRN code (ISR_sudav, ISR_sof, ISR_sutok, ISR_susp, ISR_ures) + EXTRN code (ISR_highspeed, ISR_ep0ack, ISR_stub, ISR_ibn, ISR_errorlimit) + EXTRN code (ISR_ep0in, ISR_ep0out, ISR_ep1in, ISR_ep1out) + EXTRN code (ISR_ep2inout, ISR_ep4inout, ISR_ep6inout, ISR_ep8inout) + + EXTRN code (ISR_ep0pingnak, ISR_ep1pingnak) + + EXTRN code (ISR_ep2pingnak, ISR_ep4pingnak, ISR_ep6pingnak, ISR_ep8pingnak) + EXTRN code (ISR_ep2piderror, ISR_ep4piderror,ISR_ep6piderror,ISR_ep8piderror) + EXTRN code (ISR_ep2pflag, ISR_ep4pflag, ISR_ep6pflag, ISR_ep8pflag) + EXTRN code (ISR_ep2eflag, ISR_ep4eflag, ISR_ep6eflag, ISR_ep8eflag) + EXTRN code (ISR_ep2fflag, ISR_ep4fflag, ISR_ep6fflag, ISR_ep8fflag) + + EXTRN code (ISR_gpifcomplete) + EXTRN code (ISR_gpifwaveform) + + ;; -------------------------------------------------------------------- + ;; Interrupt vectors + ;; -------------------------------------------------------------------- + cseg at 43h + ljmp JumpTable ; Autovector will replace byte at 45h + + cseg at 53h + ljmp JumpTable ; Autovector will replace byte at 55h + +;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +;; +;; USB Jump Table +;; +;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +USBJT segment code page + rseg USBJT + +JumpTable: + ;; -------------------------------------------------------------------- + ;; INT2 - USB Interrupts + ;; -------------------------------------------------------------------- + ISR ISR_sudav ;(00) Setup Data Available + ISR ISR_sof ;(04) Start of Frame + ISR ISR_sutok ;(08) Setup Data Loading + ISR ISR_susp ;(0C) Global Suspend + ISR ISR_ures ;(10) USB Reset + ISR ISR_highspeed ;(14) Entered High Speed + ISR ISR_ep0ack ;(18) EP0ACK + ISR ISR_stub ;(1C) reserved + + ISR ISR_ep0in ;(20) EP0 In + ISR ISR_ep0out ;(24) EP0 Out + ISR ISR_ep1in ;(28) EP1 In + ISR ISR_ep1out ;(2C) EP1 Out + ISR ISR_ep2inout ;(30) EP2 In/Out + ISR ISR_ep4inout ;(34) EP4 In/Out + ISR ISR_ep6inout ;(38) EP6 In/Out + ISR ISR_ep8inout ;(3C) EP8 In/Out + + ISR ISR_ibn ;(40) IBN (IN-Bulk-NAK [any IN endpoint]) + ISR ISR_stub ;(44) reserved + + ISR ISR_ep0pingnak ;(48) EP0 out was pinged and it NAK'd + ISR ISR_ep1pingnak ;(4C) EP1 out was pinged and it NAK'd + ISR ISR_ep2pingnak ;(50) EP2 out was pinged and it NAK'd + ISR ISR_ep4pingnak ;(54) EP4 out was pinged and it NAK'd + ISR ISR_ep6pingnak ;(58) EP6 out was pinged and it NAK'd + ISR ISR_ep8pingnak ;(5C) EP8 out was pinged and it NAK'd + + ISR ISR_errorlimit ;(60) Bus errors exceeded the programmed limit + + ISR ISR_stub ;(64) reserved + ISR ISR_stub ;(68) reserved + ISR ISR_stub ;(6C) reserved + + ISR ISR_ep2piderror ;(70) EP2 ISO Pid Sequence Error + ISR ISR_ep4piderror ;(74) EP4 ISO Pid Sequence Error + ISR ISR_ep6piderror ;(78) EP6 ISO Pid Sequence Error + ISR ISR_ep8piderror ;(7C) EP8 ISO Pid Sequence Error + + ;; -------------------------------------------------------------------- + ;; INT4 - FIFO/GPIF Interrupts + ;; -------------------------------------------------------------------- + ISR ISR_ep2pflag ;(80) EP2 Programmable Flag + ISR ISR_ep4pflag ;(84) EP4 Programmable Flag + ISR ISR_ep6pflag ;(88) EP6 Programmable Flag + ISR ISR_ep8pflag ;(8C) EP8 Programmable Flag + + ISR ISR_ep2eflag ;(90) EP2 Empty Flag + ISR ISR_ep4eflag ;(94) EP4 Empty Flag + ISR ISR_ep6eflag ;(98) EP6 Empty Flag + ISR ISR_ep8eflag ;(9C) EP8 Empty Flag + + ISR ISR_ep2fflag ;(A0) EP2 Full Flag + ISR ISR_ep4fflag ;(A4) EP4 Full Flag + ISR ISR_ep6fflag ;(A8) EP6 Full Flag + ISR ISR_ep8fflag ;(AC) EP8 Full Flag + + ISR ISR_gpifcomplete ;(B0) GPIF Operation Complete + ISR ISR_gpifwaveform ;(B4) GPIF Waveform + + END \ No newline at end of file diff --git a/lib/fx2lp/src/fx2_startup.s51 b/lib/fx2lp/src/fx2_startup.s51 new file mode 100644 index 0000000..ec99b9e --- /dev/null +++ b/lib/fx2lp/src/fx2_startup.s51 @@ -0,0 +1,198 @@ +$NOMOD51 +;------------------------------------------------------------------------------ +; This file is part of the C51 Compiler package +; Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc. +; Version 8.01 +; +; *** <<< Use Configuration Wizard in Context Menu >>> *** +;------------------------------------------------------------------------------ +; STARTUP.A51: This code is executed after processor reset. +; +; To translate this file use A51 with the following invocation: +; +; A51 STARTUP.A51 +; +; To link the modified STARTUP.OBJ file to your application use the following +; Lx51 invocation: +; +; Lx51 your object file list, STARTUP.OBJ controls +; +;------------------------------------------------------------------------------ +; +; User-defined Power-On Initialization of Memory +; +; With the following EQU statements the initialization of memory +; at processor reset can be defined: +; +; IDATALEN: IDATA memory size <0x0-0x100> +; Note: The absolute start-address of IDATA memory is always 0 +; The IDATA space overlaps physically the DATA and BIT areas. +IDATALEN EQU 80H +; +; XDATASTART: XDATA memory start address <0x0-0xFFFF> +; The absolute start address of XDATA memory +XDATASTART EQU 0 +; +; XDATALEN: XDATA memory size <0x0-0xFFFF> +; The length of XDATA memory in bytes. +XDATALEN EQU 0 +; +; PDATASTART: PDATA memory start address <0x0-0xFFFF> +; The absolute start address of PDATA memory +PDATASTART EQU 0H +; +; PDATALEN: PDATA memory size <0x0-0xFF> +; The length of PDATA memory in bytes. +PDATALEN EQU 0H +; +; +;------------------------------------------------------------------------------ +; +; Reentrant Stack Initialization +; +; The following EQU statements define the stack pointer for reentrant +; functions and initialized it: +; +; Stack Space for reentrant functions in the SMALL model. +; IBPSTACK: Enable SMALL model reentrant stack +; Stack space for reentrant functions in the SMALL model. +IBPSTACK EQU 0 ; set to 1 if small reentrant is used. +; IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF> +; Set the top of the stack to the highest location. +IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 +; +; +; Stack Space for reentrant functions in the LARGE model. +; XBPSTACK: Enable LARGE model reentrant stack +; Stack space for reentrant functions in the LARGE model. +XBPSTACK EQU 0 ; set to 1 if large reentrant is used. +; XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF> +; Set the top of the stack to the highest location. +XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1 +; +; +; Stack Space for reentrant functions in the COMPACT model. +; PBPSTACK: Enable COMPACT model reentrant stack +; Stack space for reentrant functions in the COMPACT model. +PBPSTACK EQU 0 ; set to 1 if compact reentrant is used. +; +; PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF> +; Set the top of the stack to the highest location. +PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 +; +; +;------------------------------------------------------------------------------ +; +; Memory Page for Using the Compact Model with 64 KByte xdata RAM +; Compact Model Page Definition +; +; Define the XDATA page used for PDATA variables. +; PPAGE must conform with the PPAGE set in the linker invocation. +; +; Enable pdata memory page initalization +PPAGEENABLE EQU 0 ; set to 1 if pdata object are used. +; +; PPAGE number <0x0-0xFF> +; uppermost 256-byte address of the page used for PDATA variables. +PPAGE EQU 0 +; +; SFR address which supplies uppermost address byte <0x0-0xFF> +; most 8051 variants use P2 as uppermost address byte +PPAGE_SFR DATA 0A0H +; +; +;------------------------------------------------------------------------------ + +; Standard SFR Symbols +ACC DATA 0E0H +B DATA 0F0H +SP DATA 81H +DPL DATA 82H +DPH DATA 83H + + NAME ?C_STARTUP + + +?C_C51STARTUP SEGMENT CODE +?STACK SEGMENT IDATA + + RSEG ?STACK + DS 1 + + EXTRN CODE (?C_START) + PUBLIC ?C_STARTUP + + CSEG AT 0 +?C_STARTUP: LJMP STARTUP1 + + RSEG ?C_C51STARTUP + +STARTUP1: + +IF IDATALEN <> 0 + MOV R0,#IDATALEN - 1 + CLR A +IDATALOOP: MOV @R0,A + DJNZ R0,IDATALOOP +ENDIF + +IF XDATALEN <> 0 + MOV DPTR,#XDATASTART + MOV R7,#LOW (XDATALEN) + IF (LOW (XDATALEN)) <> 0 + MOV R6,#(HIGH (XDATALEN)) +1 + ELSE + MOV R6,#HIGH (XDATALEN) + ENDIF + CLR A +XDATALOOP: MOVX @DPTR,A + INC DPTR + DJNZ R7,XDATALOOP + DJNZ R6,XDATALOOP +ENDIF + +IF PPAGEENABLE <> 0 + MOV PPAGE_SFR,#PPAGE +ENDIF + +IF PDATALEN <> 0 + MOV R0,#LOW (PDATASTART) + MOV R7,#LOW (PDATALEN) + CLR A +PDATALOOP: MOVX @R0,A + INC R0 + DJNZ R7,PDATALOOP +ENDIF + +IF IBPSTACK <> 0 +EXTRN DATA (?C_IBP) + + MOV ?C_IBP,#LOW IBPSTACKTOP +ENDIF + +IF XBPSTACK <> 0 +EXTRN DATA (?C_XBP) + + MOV ?C_XBP,#HIGH XBPSTACKTOP + MOV ?C_XBP+1,#LOW XBPSTACKTOP +ENDIF + +IF PBPSTACK <> 0 +EXTRN DATA (?C_PBP) + MOV ?C_PBP,#LOW PBPSTACKTOP +ENDIF + + MOV SP,#?STACK-1 + +; This code is required if you use L51_BANK.A51 with Banking Mode 4 +; Code Banking +; Select Bank 0 for L51_BANK.A51 Mode 4 +#if 0 +; Initialize bank mechanism to code bank 0 when using L51_BANK.A51 with Banking Mode 4. +EXTRN CODE (?B_SWITCH0) + CALL ?B_SWITCH0 ; init bank mechanism to code bank 0 +#endif +; + LJMP ?C_START + + END diff --git a/lib/fx2lp/src/fx2_tmr.c b/lib/fx2lp/src/fx2_tmr.c new file mode 100644 index 0000000..f7a62c5 --- /dev/null +++ b/lib/fx2lp/src/fx2_tmr.c @@ -0,0 +1,51 @@ +#include +#include + +// ================================================================================================= +// init +// ================================================================================================= +//void fx2_tmr_init( void) +//{ + // --------------------------------------------------------------- + // timer 0: system tick (1 ms @ 48 MHz) + // --------------------------------------------------------------- + +// CT0 = 0; // souce = system clock +// T0M = 0; // freq. = 4 MHz (48 MHz / 12) + +// TL0 = 0x60; // divider +// TH0 = 0xF0; // + +// M10 = 0; // 16 bit counter mode +// M00 = 1; // + +// ET0 = 1; // enable interrupt +// TR0 = 1; // enable timer + +// PD7 = 1; + // --------------------------------------------------------------- + // timer 1: baud rate generator for serial ports (128 pin only) + // --------------------------------------------------------------- +//} + +// ================================================================================================= +// timer 0 interrupt service routine +// ================================================================================================= +void tmr_isr() interrupt 2 +{ + // --------------------------------------------------------------- + // update timer + // --------------------------------------------------------------- + TR0 = 0; // disable timer + // + TL0 = 0x60; // divider + TH0 = 0xF0; // + // + TR0 = 1; // enable timer + + // --------------------------------------------------------------- + // + // --------------------------------------------------------------- + PD7 = 1;//(PD7) ? 0 : 1; + +} diff --git a/lib/fx2lp/src/fx2_tmr.s51 b/lib/fx2lp/src/fx2_tmr.s51 new file mode 100644 index 0000000..90bdb9d --- /dev/null +++ b/lib/fx2lp/src/fx2_tmr.s51 @@ -0,0 +1,44 @@ + NAME FX2_TIMER + PUBLIC fx2_tmr_init + + ;; --------------------------------------------------- + ;; interrupt vectors + ;; --------------------------------------------------- + cseg at 0bh + ljmp isr_tm0 + + + + +TIMER segment code page + rseg TIMER + +fx2_tmr_init: +; clr CT0 +; clr T0M + + mov TL0, #060h + mov TH0, #0F0h + + orl TMOD,#01H ; Timer 0 Mode 1 + + setb TR0 + setb ET0 + +; setb PD7 + + ret + +isr_tm0: clr TR0 + + mov TL0, #060h + mov TH0, #0F0h + + setb TR0 + + + + + reti + + end \ No newline at end of file diff --git a/lib/fx2lp/src/fx2_usart.c b/lib/fx2lp/src/fx2_usart.c new file mode 100644 index 0000000..5f2277f --- /dev/null +++ b/lib/fx2lp/src/fx2_usart.c @@ -0,0 +1,228 @@ +#include +#include +#include +#include + + +typedef struct +{ + BYTE length; + BYTE count; + BYTE status; + BYTE xdata *dat; + BYTE xdata *pause; +} USART_PACKET; + +static USART_PACKET volatile UsartPacket; +/* + I2CPacket.length= 0; + I2CPacket.count = 0; + I2CPacket.status= I2C_IDLE; + + I2CTL &= ~bm400KHZ; // 100 kHz + + PI2C = 1; + EI2C = 1; // Enable I2C interrupt +*/ + +static bool usart_send( BYTE length, BYTE xdata *dat, BYTE xdata *pause); + +static unsigned short usart0_baud; +static usart_cfg usart0_cfg; + +// ================================================================================================= +// fx2_usart_init +// ================================================================================================= +void fx2_usart_init( unsigned short baud, usart_cfg cfg) +{ + usart0_baud = baud; + usart0_cfg = cfg; + + // --------------------------------------------------------------- + // Initialize packet + // --------------------------------------------------------------- + UsartPacket.dat = 0; + UsartPacket.length = 0; + UsartPacket.count = 0; + UsartPacket.status = USART_IDLE; + + // --------------------------------------------------------------- + // Setup TMR1 as a baudrate generator. Timer mode 2. + // + // Reload values (TH1) for 48 MHz CLKOUt: + // + // 57600 : 0xF3 ( 57692 +0.16%) + // 38400 : 0xEC ( 37500 -2.34%) + // 19200 : 0xD9 ( 19230 +0.16%) + // 9600 : 0xB2 ( 9615 +0.16%) + // 4800 : 0x64 ( 4807 +0.16%) + // --------------------------------------------------------------- +// CT1 = 0; SYNCDELAY; // source = system clock +// T1M = 0; SYNCDELAY; // freq. = 4 MHz (48 MHz / 12) +// T0M = 0; + +// M11 = 0; SYNCDELAY; // 8 bit mode with auto reload (mode 2) +// M01 = 1; SYNCDELAY; // + + + + switch( baud) + { + case 57600 : TH1 = 0xF3; break; + case 38400 : TH1 = 0xEC; break; + case 19200 : TH1 = 0xD9; break; + case 9600 : TH1 = 0xB2; break; + case 4800 : TH1 = 0x64; break; + + default : TH1 = 0xB2; break; + } + + SMOD1 = 1; + + CKCON = 0x38; SYNCDELAY; + TMOD = 0x20; SYNCDELAY; + + TR1 = 1; // enable timer + + // --------------------------------------------------------------- + // setup USART 0 + // --------------------------------------------------------------- +// TCLK = 0; SYNCDELAY; // use TMR1 as transmit clock +// RCLK = 0; SYNCDELAY; // use TMR1 as receive clock + + SCON1 = 0xC8; +// SCON0 = 0xD0; +// +// if( cfg == uc8n1) // 10 bit mode +// { +// SM0 = 0; // usart mode 1 +// SM1 = 1; +// } +// +// else // 11 bit modes +// { +// SM0 = 1; // usart mode 3 +// SM1 = 1; // +// +// SM2 = 0; // no multiprocessor communication +// } + +// if( cfg == uc8n1) // 10 bit mode +// { +// SM01 = 0; // usart mode 1 +// SM11 = 1; +// } +// +// else // 11 bit modes +// { +// SM01 = 1; // usart mode 3 +// SM11 = 1; // +// +// SM2 = 0; // no multiprocessor communication +// } + + ES1 = 1; // enable usart1 interrupt + //PS1 = 1; +} + + +static void usart_send_byte( BYTE byte, usart_cfg cfg) +{ + switch( cfg) + { + case uc8n2: + TB81 = 1; + break; + + case uc8e1: + ACC = byte; + TB81 = (P) ? 1 : 0; + break; + + case uc8o1: + ACC = byte; + TB81 = (P) ? 0 : 1; + break; + } + + SBUF1 = byte; +} + + +BYTE fx2_usart_send( BYTE length, BYTE xdata *dat, BYTE xdata *pause) +{ + BYTE rc = USART_ERROR; + + if( usart_send( length, dat, pause)) + while( UsartPacket.status != USART_IDLE) + ; + + return USART_ERROR; +} + +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +// INTERNAL ROUTINES +// +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + + +// ================================================================================================= +// usart_send +// ================================================================================================= +static bool usart_send( BYTE length, BYTE xdata *dat, BYTE xdata *pause) +{ + if( UsartPacket.status == USART_IDLE) + { + usart_send_byte( *dat++, usart0_cfg); + + UsartPacket.count = 0; + UsartPacket.length = length; + UsartPacket.dat = dat; + UsartPacket.pause = pause; + + UsartPacket.status = USART_SENDING; + + return true; + } + + return false; +} + +extern void FX2_Delay( WORD ms); + +// ================================================================================================= +// usart interrupt service routine +// ================================================================================================= +void usart_isr() interrupt 7 +{ + BYTE pause; + + if( UsartPacket.status == USART_SENDING) + { + if( UsartPacket.pause) + { + pause = *UsartPacket.pause++; + + if( pause) + FX2_Delay(pause); + } + + if( UsartPacket.length == 1) + UsartPacket.status = USART_IDLE; + + else + { + UsartPacket.length--; + usart_send_byte( *UsartPacket.dat++, usart0_cfg); + } + } + + TI1 = 0; + +} \ No newline at end of file diff --git a/lib/fx2lp/src/fx2_usb_isr.c b/lib/fx2lp/src/fx2_usb_isr.c new file mode 100644 index 0000000..5540d3e --- /dev/null +++ b/lib/fx2lp/src/fx2_usb_isr.c @@ -0,0 +1,263 @@ +#pragma NOIV // Do not generate interrupt vectors + +#include +#include +#include + +xdata CONFIG_DSCR xdata *pDscrMainConfig; +xdata CONFIG_DSCR xdata *pDscrOthrConfig; + +xdata CONFIG_DSCR xdata *pDscrFsConfig; +xdata CONFIG_DSCR xdata *pDscrHsConfig; + +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// +// USB Interrupt handler routines. +// +// These routines are used in AutoVector mode. Autovector mode is preferred. +// +// DO NOT HANDLE IMPORTANT USB REQUEST VIA TASKS ! +// IT TAKES TIME TO SIGNAL A TASK !!!! +// +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +// ============================================================================ +// USB interrupt hooks +// ============================================================================ +void (*sudav) (void) = 0; + +void (*ep0ack) (void) = 0; +void (*ep0out) (void) = 0; +void (*ep0in ) (void) = 0; + +void (*ep1out) (void) = 0; +void (*ep1in ) (void) = 0; + +void (*ep2inout)(void) = 0; +void (*ep4inout)(void) = 0; +void (*ep6inout)(void) = 0; +void (*ep8inout)(void) = 0; + +// ============================================================================ +// (00) Setup Data Available interrupt handler +// ============================================================================ +void ISR_sudav() interrupt 0 +{ + if( sudav) + sudav(); + + USB_IRQ_CLEAR(); + USBIRQ = bmSUDAV; +} + +// ============================================================================ +// (04) Start of Frame +// ============================================================================ +void ISR_sof() interrupt 0 +{ + USB_IRQ_CLEAR(); + USBIRQ = bmSOF; +} + +// ============================================================================ +// (08) Setup Token interrupt handler +// ============================================================================ +void ISR_sutok() interrupt 0 +{ + USB_IRQ_CLEAR(); + USBIRQ = bmSUTOK; +} + +// ============================================================================ +// (0C) Global Suspend +// ============================================================================ +void ISR_susp() interrupt 0 +{ + USB_IRQ_CLEAR(); + USBIRQ = bmSUSP; +} + +// ============================================================================ +// (10) USB Reset +// ============================================================================ +void ISR_ures() interrupt 0 +{ + // ---------------------------------------------------- + // Whenever we get a USB reset, we should revert to + // full speed mode. + // ---------------------------------------------------- + pDscrMainConfig = pDscrFsConfig; + pDscrOthrConfig = pDscrHsConfig; + + pDscrMainConfig->type = DSCR_CONFIG; + pDscrOthrConfig->type = DSCR_OTHERSPEED; + + USB_IRQ_CLEAR(); + USBIRQ = bmURES; +} + +// ============================================================================ +// (14) Entered High Speed +// ============================================================================ +void ISR_highspeed() interrupt 0 +{ + pDscrMainConfig = pDscrHsConfig; + pDscrOthrConfig = pDscrFsConfig; + + pDscrMainConfig->type = DSCR_CONFIG; + pDscrOthrConfig->type = DSCR_OTHERSPEED; + + USB_IRQ_CLEAR(); + USBIRQ = bmHSGRANT; +} + +// ============================================================================ +// (18) EP0ACK +// ============================================================================ +void ISR_ep0ack() interrupt 0 +{ + if( ep0ack) + ep0ack(); + + USB_IRQ_CLEAR(); + USBIRQ = bmEP0ACK; +} + +// ============================================================================ +// (20) EP0IN +// ============================================================================ +void ISR_ep0in() interrupt 0 +{ + if( ep0in) + ep0in(); + + USB_IRQ_CLEAR(); + EPIRQ = bmEP0IN; +} + +// ============================================================================ +// (24) EP0OUT +// ============================================================================ +void ISR_ep0out() interrupt 0 +{ + if( ep0out) + ep0out(); + + USB_IRQ_CLEAR(); + EPIRQ = bmEP0OUT; +} + +// ============================================================================ +// (28) EP1IN +// ============================================================================ +void ISR_ep1in() interrupt 0 +{ + if( ep1in) + ep1in(); + + USB_IRQ_CLEAR(); + EPIRQ = bmEP1IN; +} + +// ============================================================================ +// (2C) EP1OUT +// ============================================================================ +void ISR_ep1out() interrupt 0 +{ + if( ep1out) + ep1out(); + + USB_IRQ_CLEAR(); + EPIRQ = bmEP1OUT; +} + +// ============================================================================ +// (30) EP2 +// ============================================================================ +void ISR_ep2inout() interrupt 0 +{ + if( ep2inout) + ep2inout(); + + USB_IRQ_CLEAR(); + EPIRQ = bmEP2; +} + +// ============================================================================ +// (34) EP4 +// ============================================================================ +void ISR_ep4inout() interrupt 0 +{ + if( ep4inout) + ep4inout(); + + USB_IRQ_CLEAR(); + EPIRQ = bmEP4; +} + +// ============================================================================ +// (38) EP6 +// ============================================================================ +void ISR_ep6inout() interrupt 0 +{ + if( ep6inout) + ep6inout(); + + USB_IRQ_CLEAR(); + EPIRQ = bmEP6; +} + +// ============================================================================ +// (3C) EP8 +// ============================================================================ +void ISR_ep8inout() interrupt 0 +{ + if( ep8inout) + ep8inout(); + + USB_IRQ_CLEAR(); + EPIRQ = bmEP8; +} + +// ============================================================================ +// Dummy handlers +// ============================================================================ +void ISR_ep0pingnak() interrupt 0 {} +void ISR_ep1pingnak() interrupt 0 {} +void ISR_ep2pingnak() interrupt 0 {} +void ISR_ep4pingnak() interrupt 0 {} +void ISR_ep6pingnak() interrupt 0 {} +void ISR_ep8pingnak() interrupt 0 {} + + +void ISR_ep2piderror() interrupt 0 {} +void ISR_ep4piderror() interrupt 0 {} +void ISR_ep6piderror() interrupt 0 {} +void ISR_ep8piderror() interrupt 0 {} + +void ISR_ep2pflag() interrupt 0 {} +void ISR_ep4pflag() interrupt 0 {} +void ISR_ep6pflag() interrupt 0 {} +void ISR_ep8pflag() interrupt 0 {} + +void ISR_ep2eflag() interrupt 0 {} +void ISR_ep4eflag() interrupt 0 {} +void ISR_ep6eflag() interrupt 0 {} +void ISR_ep8eflag() interrupt 0 {} + +void ISR_ep2fflag() interrupt 0 {} +void ISR_ep4fflag() interrupt 0 {} +void ISR_ep6fflag() interrupt 0 {} +void ISR_ep8fflag() interrupt 0 {} + +void ISR_ibn() interrupt 0 {} +void ISR_errorlimit() interrupt 0 {} + +void ISR_gpifcomplete() interrupt 0 {} +void ISR_gpifwaveform() interrupt 0 {} + +void ISR_stub() interrupt 0 {} diff --git a/lib/fx2lp/src/fx2_usb_sleep.c b/lib/fx2lp/src/fx2_usb_sleep.c new file mode 100644 index 0000000..41d6508 --- /dev/null +++ b/lib/fx2lp/src/fx2_usb_sleep.c @@ -0,0 +1,6 @@ +#include +#include + +void job_sleep(void) +{ +} \ No newline at end of file diff --git a/lib/fx2lp/src/fx2_usb_sudav.c b/lib/fx2lp/src/fx2_usb_sudav.c new file mode 100644 index 0000000..da97415 --- /dev/null +++ b/lib/fx2lp/src/fx2_usb_sudav.c @@ -0,0 +1,171 @@ +// ============================================================================ +// IMPORTANT +// +// The project specific descriptor table must exist !!! +// It declares the following symbols: +// - DscrString +// - DscrDevice +// - DscrDeviceQual +// - DscrHsConfig +// - DscrFsConfig +// ============================================================================ +#include +#include + +xdata DEVICE_DSCR xdata *pDscrDevice; +xdata DEVICEQUAL_DSCR xdata *pDscrDeviceQual; + +extern xdata CONFIG_DSCR xdata *pDscrMainConfig; +extern xdata CONFIG_DSCR xdata *pDscrOthrConfig; +extern xdata CONFIG_DSCR xdata *pDscrFsConfig; +extern xdata CONFIG_DSCR xdata *pDscrHsConfig; + + +data STRING_DSCR xdata *pDscrString; + +STRING_DSCR xdata * GetStringDscr( BYTE index); + +bool (*DR_VendorCommand)() = 0; + +// ============================================================================ +// SUDAV (device request parser) +// +// The following commands have no default implementation: +// - SC_GET_INTERFACE +// - SC_SET_INTERFACE +// - SC_GET_CONFIGURATION +// - SC_SET_CONFIGURATION +// +// These commands usually result in changing the hardware configuration, which +// is different in most device. +// ============================================================================ +void tri_sudav() +{ + STRING_DSCR xdata *ptr; + BYTE xdata cfg; + + switch( SETUPDAT[1]) + { + // ------------------------------------------------ + // Get Descriptor + // ------------------------------------------------ + case SC_GET_DESCRIPTOR: + switch( SETUPDAT[3]) + { + case GD_DEVICE: + SUDPTRH = MSB(pDscrDevice); + SUDPTRL = LSB(pDscrDevice); + break; + + case GD_DEVICE_QUALIFIER: + // Only for HighSpeed capable devices + SUDPTRH = MSB(pDscrDeviceQual); + SUDPTRL = LSB(pDscrDeviceQual); + break; + + case GD_CONFIGURATION: + SUDPTRH = MSB(pDscrMainConfig); + SUDPTRL = LSB(pDscrMainConfig); + break; + + case GD_OTHER_SPEED_CONFIG: + SUDPTRH = MSB(pDscrOthrConfig); + SUDPTRL = LSB(pDscrOthrConfig); + break; + + case GD_STRING: + if( ptr = GetStringDscr(SETUPDAT[2])) + { + SUDPTRH = MSB(ptr); + SUDPTRL = LSB(ptr); + } + else + FX2_STALL_EP0(); + + break; + + default: + FX2_STALL_EP0(); + break; + } + break; + + // ------------------------------------------------ + // Get Status + // ------------------------------------------------ + case SC_GET_STATUS: + switch( SETUPDAT[0]) + { + case GS_DEVICE: +// EP0BUF[0] = ((BYTE)Rwuen << 1) | (BYTE)SelfPower; + EP0BUF[0] = 0; + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + break; + + case GS_INTERFACE: + EP0BUF[0] = 0; + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + break; + + case GS_ENDPOINT: +// EP0BUF[0] = (*(BYTE xdata *)epcs(SETUPDAT[4])) & bmEPSTALL; + EP0BUF[0] = 0; + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + break; + + default: + FX2_STALL_EP0(); + break; + } + break; + + + // ------------------------------------------------ + // Set Configuration + // ------------------------------------------------ + case SC_SET_CONFIGURATION: + cfg = SETUPDAT[2]; + break; + + // ------------------------------------------------ + // Vendor command + // ------------------------------------------------ + default: + if( !DR_VendorCommand) + { + } + + else if( !DR_VendorCommand()) + { + } + } + + // -------------------------------------------------------------- + // Acknowledge handshake phase of device request. + // -------------------------------------------------------------- + EP0CS |= bmHSNAK; +} + +// ============================================================================ +// GetStringDscr +// ============================================================================ +STRING_DSCR xdata * GetStringDscr( BYTE index) +{ + STRING_DSCR xdata * dscr = pDscrString; + + while( dscr->type == DSCR_STRING) + { + if( !index--) + return dscr; + + dscr = (STRING_DSCR xdata *)((WORD)dscr +dscr->length); + } + + return 0; +} diff --git a/lib/fx2mr/inc/lcd/lcd_44780.h b/lib/fx2mr/inc/lcd/lcd_44780.h new file mode 100644 index 0000000..054e451 --- /dev/null +++ b/lib/fx2mr/inc/lcd/lcd_44780.h @@ -0,0 +1,23 @@ +#ifndef __LCD_44780_H__ +#define __LCD_44780_H__ + +#include + +void lcd_44780_init(void); + +void lcd_44780_gotoxy( BYTE x, BYTE y); +void lcd_44780_putc( BYTE c); +void lcd_44780_putx2( BYTE c); +void lcd_44780_putled( BYTE n, BYTE value); + +extern void lcd_44780_puts( char *); + +#define lcd_init() lcd_44780_init() + +#define lcd_gotoxy(x,y) lcd_44780_gotoxy(x,y) +#define lcd_putc(c) lcd_44780_putc(c) +#define lcd_putx2(c) lcd_44780_putx2(c) +#define lcd_putled(n,v) lcd_44780_putled(n,v) +#define lcd_puts(s) lcd_44780_puts(s) + +#endif diff --git a/lib/fx2mr/inc/lcd/lcd_7565r.h b/lib/fx2mr/inc/lcd/lcd_7565r.h new file mode 100644 index 0000000..4146cb5 --- /dev/null +++ b/lib/fx2mr/inc/lcd/lcd_7565r.h @@ -0,0 +1,26 @@ +#ifndef LCD_ST7565R_H +#define LCD_ST7565R_H + +#include + + +void st7565r_init(); +void st7565r_cls(); +void st7565r_gotoxy( BYTE x, BYTE y); +void st7565r_putc( char c); +void st7565r_puts( char *s, BYTE len); +void st7565r_putx1( BYTE x); +void st7565r_putx2( BYTE x); +void st7565r_putg( BYTE *g, BYTE len); +void st7565r_putd( WORD number, BYTE length, bool showzero); + +#define lcd_init() st7565r_init() +#define lcd_cls() st7565r_cls() +#define lcd_gotoxy(x,y) st7565r_gotoxy(x,y) + +#define lcd_putc(c) st7565r_putc(c) +#define lcd_puts(s,n) st7565r_puts(s,n) +#define lcd_putx1(x) st7565r_putx1(x) +#define lcd_putx2(x) st7565r_putx2(x) + +#endif \ No newline at end of file diff --git a/lib/fx2mr/src/jtag/jtag.s51 b/lib/fx2mr/src/jtag/jtag.s51 new file mode 100644 index 0000000..c171db3 --- /dev/null +++ b/lib/fx2mr/src/jtag/jtag.s51 @@ -0,0 +1,552 @@ + PUBLIC jtag_init + + PUBLIC _jtag_set_state + + PUBLIC _jtag_set_enddr + PUBLIC _jtag_set_endir + + PUBLIC jtag_get_enddr + PUBLIC jtag_get_endir + + PUBLIC _jtag_tck + PUBLIC _jtag_xfer + +; PUBLIC _jtag_prgn + +; EXTRN code(_lcd_putx2) + + +JTAG_CODE SEGMENT CODE +JTAG_TABLES SEGMENT CODE +JTAG_FLAGS SEGMENT BIT +JTAG_DATA SEGMENT DATA + +; ----------------------------------------------------------------------------- +; LatticeVME TAP state values +; ----------------------------------------------------------------------------- +TS_RESET EQU 0 +TS_IDLE EQU 1 +TS_IRPAUSE EQU 2 +TS_DRPAUSE EQU 3 +TS_IRSHIFT EQU 4 +TS_DRSHIFT EQU 5 +TS_DRCAPT EQU 6 +TS_IREXIT1 EQU 7 +TS_DREXIT1 EQU 8 +; ----------------------------------------------------------------------------- + +$IF(BOARD_DSO) + IOA EQU 0x80 + + JTAG_TCK BIT IOA.0 + JTAG_TMS BIT IOA.1 + JTAG_TDI BIT IOA.3 + JTAG_TDO BIT IOA.7 + +$ELSEIF(BOARD_JTAG) + IOA EQU 0x80 + + JTAG_TCK BIT IOA.0 + JTAG_TMS BIT IOA.1 + JTAG_TDI BIT IOA.7 + JTAG_TDO BIT IOA.3 + JTAG_ENA BIT IOA.4 + +$ELSEIF(BOARD_CF1) + IOA EQU 0x80 + IOC EQU 0A0h + + JTAG_TCK BIT IOC.0 + JTAG_TMS BIT IOC.1 + JTAG_TDI BIT IOC.2 + JTAG_TDO BIT IOC.3 + + JTAG_PRGn BIT IOC.4 + +$ELSE + adad +$ENDIF + + RSEG JTAG_FLAGS +fl_last: DBIT 1 + + RSEG JTAG_DATA +tap_endir: DS 1 +tap_enddr: DS 1 +tap_state: DS 1 + + +; ============================================================================= +; void jtag_init(void) +; ============================================================================= + RSEG JTAG_CODE + $REGUSE jtag_init(R7) + +jtag_init: + mov tap_enddr,#TS_IDLE + mov tap_endir,#TS_IDLE + mov tap_state,#TS_DRSHIFT + + mov R7,#TS_RESET + ljmp _jtag_set_state + +; ============================================================================= +; void jtag_tck( WORD clk) +; +; input +; R7 = LSB(clk) +; R6 = MSB(clk) +; ============================================================================= + $REGUSE _jtag_tck(B,R6,R7) + + ; ----------------------------------------------------------------- + ; check parameters + ; ----------------------------------------------------------------- +_jtag_tck: cjne R7,#0,CK0 ; if length = 0 then + cjne R6,#0,CK0 ; return; + ret ; + + ; ----------------------------------------------------------------- + ; calculate pulse count + ; ----------------------------------------------------------------- +CK0: cjne R6,#0,CK1 ; if length < 256 then + ; begin + mov B,R7 ; count := R7; + mov R7,#0 ; length := 0; + sjmp CK2 ; end + ; + ; else begin +CK1: mov B,#0 ; count := 256; + dec R6 ; length := length -256 + ; end; + + ; ----------------------------------------------------------------- + ; generate pulses (max 256 in one chunk) with 1 MHz frequency. + ; ----------------------------------------------------------------- + ; do +CK2: + setb JTAG_TCK ; TCK 1->0 + +; nop ; for 500 kHz remove comment +; nop ; +; nop ; +; nop ; +; nop ; +; nop ; + + clr JTAG_TCK ; TCK 0 ->1 + +; nop ; for 500 kHz remove comment +; nop ; +; nop ; +; nop ; +; nop ; +; nop ; + + djnz B,CK2 ; count := count -1; + ; while count > 0; + + ; ----------------------------------------------------------------- + ; repeat until length = 0 + ; ----------------------------------------------------------------- + sjmp _jtag_tck + +; ============================================================================= +; The ENDDR and ENDIR commands specify the IEEE 1149.1 stable state that the +; IEEE 1149.1 bus will be forced to at the conclusion of a DR or IR scan, +; respectively. Once specified, the ENDDR/ENDIR commands remain in force until +; overriden by another ENDDR or ENDIR command. At startup, ENDDR and ENDIR are +; both set to IDLE. Valid states are IRPAUSE, DRPAUSE, RESET, and IDLE. +; ============================================================================= + +; ============================================================================= +; BYTE jtag_get_enddr(); +; ============================================================================= + $REGUSE jtag_get_enddr() + +jtag_get_enddr: + mov R7, tap_enddr + ret + +; ============================================================================= +; BYTE jtag_get_endir(); +; ============================================================================= + $REGUSE jtag_get_endir() + +jtag_get_endir: + mov R7, tap_endir + ret + +; ============================================================================= +; bit jtag_set_enddr(BYTE state); +; ============================================================================= + $REGUSE _jtag_set_enddr() + +_jtag_set_enddr: + lcall jtag_chk_endstate + jnc DRX + + mov tap_enddr,R7 + +DRX: ret + +; ============================================================================= +; bit jtag_set_endir(BYTE state); +; ============================================================================= + $REGUSE _jtag_set_endir() + +_jtag_set_endir: + lcall jtag_chk_endstate + jnc IRX + + mov tap_endir,R7 + +IRX: ret + +; ============================================================================= +; bit jtag_chk_endstate(BYTE state); +; ============================================================================= +jtag_chk_endstate: + clr C + + cjne R7,#TS_DRPAUSE,C0 + sjmp C8 + +C0: cjne R7,#TS_IRPAUSE,C1 + sjmp C8 + +C1: cjne R7,#TS_RESET,C2 + sjmp C8 + +C2: cjne R7,#TS_IDLE,C9 + +C8: setb C +C9: ret + +; ============================================================================= +; void jtag_xfer_chunk(BYTE length, BYTE last) +; +; input: +; R7 = length (bit count) 0 = 256 +; +; dptr = buffer +; +; used: +; A = data / tap_state +; B = bit counter +; C = temp bit +; ============================================================================= + + ; ----------------------------------------------------------------- + ; process length-1 bits + ; ----------------------------------------------------------------- +;X0: clr JTAG_TCK ; TCK 1->0 +; mov C,JTAG_TDO ; get TDO into C + +X0: + mov C,JTAG_TDO ; get TDO into C + rlc A ; + mov JTAG_TDI,C ; put TDI from C + + setb JTAG_TCK ; TCK 0->1 + nop ; + nop ; + clr JTAG_TCK ; TCK 1->0 + + + ; --------------------------------- + djnz B,X2 ; if bit_counter = 1 then + ; begin + movx @dptr,A ; dptr^ := a; + inc dptr ; inc(dptr); + +jtag_xfer_chunk: + movx A,@dptr ; a := dptr^; + mov B,#8 ; bit_counter := 8 + ; end; + +X2: djnz R7,X0 ; if length > 1 then + ; loop; + + ; ----------------------------------------------------------------- + ; process last bit + ; ----------------------------------------------------------------- + mov C,JTAG_TDO ; get TDO into C + rlc A ; + mov JTAG_TDI,C ; put TDI from C + + jnb fl_last,X3 ; if this is the last chunk + setb JTAG_TMS ; then exit from xxSHIFT + +X3: ;nop + setb JTAG_TCK ; TCK 0->1 + nop + clr JTAG_TCK ; TCK 1->0 + + ; ----------------------------------------------------------------- + ; if less then 8 bits has arrived, then fill the rest of A with + ; zero bits. + ; ----------------------------------------------------------------- + djnz B,X4 ; while bit_counter <> 1 then + ljmp X5 ; begin + ; C := 0; +X4: clr C ; A := (A::C shl 1); + rlc A ; dec(bit_counter); + djnz B,X4 ; end; + +X5: movx @dptr,A ; dptr^ := a; + inc dptr ; inc(dptr); + + ; ----------------------------------------------------------------- + ; move to state ENDIR/ENDDR if this was the last chunk + ; ----------------------------------------------------------------- + jnb fl_last,X9 ; if not the last chunk then + ; return + + mov A,tap_state ; get actual state which is + ; - DRSHIFT or + ; - IRSHIFT + + cjne A,#TS_DRSHIFT,X8 ; if it is DRSHIFT then + mov tap_state,#TS_DREXIT1 ; set actual state to DREXIT1 + mov R7,tap_enddr ; set target state to "ENDDR" + jmp _jtag_set_state ; execute transition + +X8: cjne A,#TS_IRSHIFT,X9 ; if it is IRSHIFT then + mov tap_state,#TS_IREXIT1 ; set actual state to IREXIT1 + mov R7,tap_endir ; set target state to "ENDIR" + jmp _jtag_set_state ; execute transition + +X9: ret + + +; ============================================================================= +; jtag_xfer( BYTE xdata *buffer, WORD length, BYTE last); +; +; R7 = LSB(buffer) +; R6 = MSB(buffer) +; +; R5 = LSB(length in bits); // length mod 256 +; R4 = MSB(length in bits); // length div 256 +; +; R3 = last +; +; ============================================================================= + $REGUSE _jtag_xfer(A,B,C,R4,R6,R7,DPTR) + + ; ----------------------------------------------------------------- + ; check parameters + ; ----------------------------------------------------------------- +_jtag_xfer: cjne R5,#0,RW ; if length = 0 then + cjne R4,#0,RW ; return; + ret ; + + ; ----------------------------------------------------------------- + ; initialize variables + ; ----------------------------------------------------------------- +RW: mov DPL,R7 ; dptr := @buffer; + mov DPH,R6 ; + ; + clr fl_last ; fl_last := false + + ; ----------------------------------------------------------------- + ; process data in 256 bit (32 bytes) chunks + ; ----------------------------------------------------------------- + ; while true do + ; begin +RW0: cjne R4,#0,RW2 ; if length div 256 = 0 then + ; begin + ; + mov A,R5 ; R7 := length mod 256; + mov R7,A ; + ; +RW1: mov A,R3 ; A := last + rrc A ; C := last + mov fl_last,C ; fl_last := C + ; + ljmp jtag_xfer_chunk ; jtag_rdwr_chunk(len,last); + ; break + ; end + ; + ; else begin +RW2: mov R7,#0 ; R7 := 256; + dec R4 ; dec(length,256); + ; + cjne R4,#0,RW3 ; if length div 256 = 0 then + cjne R5,#0,RW3 ; if length mod 256 = 0 then + sjmp RW1 ; goto RW1; + ; + ; +RW3: lcall jtag_xfer_chunk ; jtag_rdwr_chunk(256,false); + sjmp RW0 ; end + ; end; + +; ============================================================================= +; jtag_state( BYTE state) +; +; +; input +; R7 - new state +; +; note: +; Reset always does full 5 bits stream, because we cannot be sure the +; actual state. It will bring the JTAG state machine into a known state. +; ============================================================================= + $REGUSE _jtag_set_state(A,B,C,DPTR) + +_jtag_set_state: + setb JTAG_TDI + + ; ------------------------------------- + ; Get the pattern table for the current + ; tap state into DPTR. + ; ------------------------------------- + mov dptr,#x_table + + mov a,tap_state + rl a + movc a,@a+dptr + mov b,a + + mov a,tap_state + rl a + inc a + movc a,@a+dptr + + mov dpl,a + mov dph,b + ; ------------------------------------- + ; fetch the TMS pattern and pattern + ; length to move to new state. + ; ------------------------------------- + mov a,r7 ; get TMS pattern length into B + rl a ; + inc a ; + movc a,@a+dptr ; + mov b,a ; + + cjne A,#0,L101 ; if pattern length = 0 then + ret ; no new state is specified, so return + +L101: mov a,r7 ; get TMS pattern into A + rl a ; + movc a,@a+dptr ; + + + + ; ------------------------------------- + ; step out the TMS pattern + ; ------------------------------------- +loop: rlc a ; get TMS bit into C flag + + mov JTAG_TMS,C ; output TMS + setb JTAG_TCK ; set TCK + nop + + clr JTAG_TCK ; clear TCK + + djnz b,loop ; + + ; ------------------------------------- + ; set new state as current + ; ------------------------------------- + mov tap_state,r7 + ret + +; ============================================================================= +; tap state transition tables +; ============================================================================= + RSEG JTAG_TABLES + +x_table: DW x_reset + DW x_idle + DW x_irpause + DW x_drpause + DW x_irshift + DW x_drshift + DW x_drcapture + DW x_irexit1 + DW x_drexit1 + +x_reset: ; ------------------------------------------------------- + DB 11111000b,5 ; reset -> reset : 11111 + DB 00000000b,1 ; reset -> idle : 0 + DB 01101000b,6 ; reset -> irpause : 011010 + DB 01010000b,5 ; reset -> drpause : 01010 + DB 01100000b,5 ; reset -> irshift : 01100 + DB 01000000b,4 ; reset -> drshift : 0100 + DB 01000000b,3 ; reset -> drcapture : 010 + +x_idle: ; ------------------------------------------------------- + DB 11111000b,5 ; reset -> reset : 11111 + DB 00000000b,1 ; idle -> idle : 0 + DB 11010000b,5 ; idle -> irpause : 11010 + DB 10100000b,4 ; idle -> drpause : 1010 + DB 11000000b,4 ; idle -> irshift : 1100 + DB 10000000b,3 ; idle -> drshift : 100 + DB 10000000b,2 ; idle -> drcapture : 10 + +x_irpause: ; ------------------------------------------------------- + DB 11111000b,5 ; irpause -> reset : 11111 + DB 11000000b,3 ; irpause -> idle : 110 + DB 11110100b,7 ; irpause -> irpause : 1111010 + DB 11101000b,6 ; irpause -> drpause : 111010 + DB 10000000b,2 ; irpause -> irshift : 10 + DB 11100000b,5 ; irpause -> drshift : 11100 + DB 11100000b,4 ; irpause -> drcapture : 1110 + +x_drpause: ; ------------------------------------------------------- + DB 11111000b,5 ; drpause -> reset : 11111 + DB 11000000b,3 ; drpause -> idle : 110 + DB 11110100b,7 ; drpause -> irpause : 1111010 + DB 11101000b,6 ; drpause -> drpause : 111010 + DB 11110000b,6 ; drpause -> irshift : 111100 + DB 10000000b,2 ; drpause -> drshift : 10 + DB 11100000b,4 ; drpause -> drcapture : 1110 + +x_irshift: ; ------------------------------------------------------- + DB 11111000b,5 ; irshift -> reset : 11111 + DB 11000000b,3 ; irshift -> idle : 110 + DB 10000000b,2 ; irshift -> irpause : 10 + DB 11101000b,6 ; irshift -> drpause : 111010 + DB 00000000b,0 ; irshift -> irshift : - + DB 11100000b,5 ; irshift -> drshift : 11100 + DB 11100000b,4 ; irshift -> drcapture : 1110 + +x_drshift: ; ------------------------------------------------------- + DB 11111000b,5 ; drshift -> reset : 11111 + DB 11000000b,3 ; drshift -> idle : 110 + DB 11110100b,7 ; drshift -> irpause : 1111010 + DB 10000000b,2 ; drshift -> drpause : 10 + DB 11110000b,6 ; drshift -> irshift : 111100 + DB 00000000b,0 ; drshift -> drshift : - + DB 11100000b,4 ; drshift -> drcapture : 1110 + +x_drcapture:; ------------------------------------------------------- + DB 11111000b,5 ; drcapture -> reset : 11111 + DB 11000000b,3 ; drcapture -> idle : 110 + DB 11110100b,7 ; drcapture -> irpause : 1111010 + DB 10000000b,2 ; drcapture -> drpause : 10 + DB 11110000b,6 ; drcapture -> irshift : 111100 + DB 00000000b,1 ; drcapture -> drshift : 0 + DB 00000000b,0 ; drcapture -> drcapture: - + +x_irexit1: ; ------------------------------------------------------- + DB 11111000b,5 ; reset -> reset : 11111 + DB 10000000b,2 ; irexit1 -> idle : 10 + DB 00000000b,1 ; irexit1 -> irpause : 0 + DB 11010000b,5 ; irexit1 -> drpause : 11010 + DB 01000000b,3 ; irexit1 -> irshift : 010 + DB 11000000b,4 ; irexit1 -> drshift : 1100 + DB 11000000b,3 ; irexit1 -> drcapture : 110 + +x_drexit1: ; ------------------------------------------------------- + DB 11111000b,5 ; reset -> reset : 11111 + DB 10000000b,2 ; drexit1 -> idle : 10 + DB 11101000b,6 ; drexit1 -> irpause : 111010 + DB 00000000b,1 ; drexit1 -> drpause : 0 + DB 11100000b,5 ; drexit1 -> irshift : 11100 + DB 01000000b,3 ; drexit1 -> drshift : 010 + DB 11000000b,3 ; drexit1 -> drcapture : 110 + + END diff --git a/lib/fx2mr/src/lcd/44780/lcd_44780.c b/lib/fx2mr/src/lcd/44780/lcd_44780.c new file mode 100644 index 0000000..5603230 --- /dev/null +++ b/lib/fx2mr/src/lcd/44780/lcd_44780.c @@ -0,0 +1,65 @@ +#include +#include + +extern void FX2_Delay( WORD ms); + +extern void lcd_44780_write_ctrl( unsigned char value); +extern void lcd_44780_write_data( unsigned char value); +extern void lcd_44780_write_led( BYTE n, BYTE v); + +code BYTE bin2hex[16] = +{ + 0x30, 0x31, 0x32, 0x33, 0x34, // 0 - 4 + 0x35, 0x36, 0x37, 0x38, 0x39, // 5 - 9 + 0x41, 0x42, 0x43, 0x44, 0x45, 0x46 // A - F +}; + +void lcd_44780_init() +{ + lcd_44780_write_ctrl( 0x38); FX2_Delay(5); + lcd_44780_write_ctrl( 0x0F); FX2_Delay(5); + lcd_44780_write_ctrl( 0x01); FX2_Delay(5); + lcd_44780_write_ctrl( 0x06); FX2_Delay(5); + lcd_44780_write_ctrl( 0x0C); FX2_Delay(1); + + lcd_44780_write_ctrl( 0x40 | 0x80); FX2_Delay(1); +} + +void lcd_44780_gotoxy( BYTE x, BYTE y) +{ + BYTE cmd; + + cmd = 0x80; + cmd = cmd | ((y & 0x01) << 6); + cmd = cmd | ((x & 0x07)); + + lcd_44780_write_ctrl(cmd); + FX2_Delay(1); +} + +void lcd_44780_putled( BYTE n, BYTE v) +{ + lcd_44780_write_led(n,v); +} + +void lcd_44780_putc( char c) +{ + lcd_44780_write_data( c); + FX2_Delay(1); +} + +void lcd_44780_puts( char *s) +{ + if(s) + while( *s) + lcd_44780_putc(*s++); +} + +void lcd_44780_putx2( BYTE x) +{ + BYTE x1 = bin2hex[(x >> 4) & 0x0F]; + BYTE x2 = bin2hex[(x >> 0) & 0x0F]; + + lcd_44780_write_data(x1); FX2_Delay(2); + lcd_44780_write_data(x2); FX2_Delay(2); +} diff --git a/lib/fx2mr/src/lcd/7565r/lcd_7565r.c b/lib/fx2mr/src/lcd/7565r/lcd_7565r.c new file mode 100644 index 0000000..74b7dac --- /dev/null +++ b/lib/fx2mr/src/lcd/7565r/lcd_7565r.c @@ -0,0 +1,421 @@ +#include +#include + +#include + +extern void lcd_7565r_init(void); +extern void lcd_7565r_deactivate(void); +extern void lcd_7565r_send( BYTE, bit); + +static void st7565r_cmd_lcdbias( BYTE); +static void st7565r_cmd_adcsel( BYTE); +static void st7565r_cmd_coms( BYTE); +static void st7565r_cmd_v0reg( BYTE); +static void st7565r_cmd_evol( BYTE); +static void st7565r_cmd_boost( BYTE); +static void st7565r_cmd_power( BYTE); + +code BYTE bin2hex[16] = +{ + 0x10, 0x11, 0x12, 0x13, 0x14, // 0 - 4 + 0x15, 0x16, 0x17, 0x18, 0x19, // 5 - 9 + 0x21, 0x22, 0x23, 0x24, 0x25, 0x26 // A - F +}; + +code BYTE ascii[95][5] = +{ + {0x00, 0x00, 0x00, 0x00, 0x00}, //0x20 space + {0x00, 0x00, 0xbe, 0x00, 0x00}, //0x21 ! + {0x00, 0x0e, 0x00, 0x0e, 0x00}, //0x22 " + {0x28, 0xfe, 0x28, 0xfe, 0x28}, //0x23 # + {0x48, 0x54, 0xfe, 0x54, 0x24}, //0x24 $ + {0x46, 0x26, 0x10, 0xc8, 0xc4}, //0x25 % + {0x6c, 0x92, 0xaa, 0x44, 0xa0}, //0x26 & + {0x00, 0x0a, 0x06, 0x00, 0x00}, //0x27 ' + {0x00, 0x38, 0x44, 0x82, 0x00}, //0x28 ( + {0x00, 0x82, 0x44, 0x38, 0x00}, //0x29 ) + {0x28, 0x10, 0x7c, 0x10, 0x28}, //0x2a * + {0x10, 0x10, 0x7c, 0x10, 0x10}, //0x2b + + {0x00, 0xa0, 0x60, 0x00, 0x00}, //0x2c , + {0x10, 0x10, 0x10, 0x10, 0x10}, //0x2d - + {0x00, 0xc0, 0xc0, 0x00, 0x00}, //0x2e . + {0x40, 0x20, 0x10, 0x08, 0x04}, //0x2f / + {0x7c, 0xA2, 0x92, 0x8A, 0x7c}, //0x30 0 + {0x00, 0x84, 0xfe, 0x80, 0x00}, //0x31 1 + {0x84, 0xc2, 0xa2, 0x92, 0x8c}, //0x32 2 + {0x42, 0x82, 0x8a, 0x96, 0x62}, //0x33 3 + {0x30, 0x28, 0x24, 0xfe, 0x20}, //0x34 4 + {0x4e, 0x8a, 0x8a, 0x8a, 0x72}, //0x35 5 + {0x78, 0x94, 0x92, 0x92, 0x60}, //0x36 6 + {0x02, 0xe2, 0x12, 0x0a, 0x06}, //0x37 7 + {0x6c, 0x92, 0x92, 0x92, 0x6c}, //0x38 8 + {0x0c, 0x92, 0x92, 0x52, 0x3c}, //0x39 9 + {0x00, 0x6c, 0x6c, 0x00, 0x00}, //0x3a : + {0x00, 0xac, 0x6c, 0x00, 0x00}, //0x3b ; + {0x10, 0x28, 0x44, 0x82, 0x00}, //0x3c < + {0x28, 0x28, 0x28, 0x28, 0x28}, //0x3d = + {0x00, 0x82, 0x44, 0x28, 0x10}, //0x3e > + {0x04, 0x02, 0xa2, 0x12, 0x0c}, //0x3f ? + {0x74, 0x92, 0xf2, 0x82, 0x7c}, //0x40 @ + {0xfc, 0x12, 0x12, 0x12, 0xfc}, //0x41 A + {0xfe, 0x92, 0x92, 0x92, 0x6c}, //0x42 B + {0x7c, 0x82, 0x82, 0x82, 0x44}, //0x43 C + {0xfe, 0x82, 0x82, 0x44, 0x38}, //0x44 D + {0xfe, 0x92, 0x92, 0x92, 0x82}, //0x45 E + {0xfe, 0x12, 0x12, 0x12, 0x02}, //0x46 F + {0x7c, 0x82, 0x82, 0xa2, 0x64}, //0x47 G + {0xfe, 0x10, 0x10, 0x10, 0xfe}, //0x48 H + {0x00, 0x82, 0xfe, 0x82, 0x00}, //0x49 I + {0x40, 0x80, 0x82, 0x7e, 0x02}, //0x4a J + {0xfe, 0x10, 0x28, 0x44, 0x82}, //0x4b K + {0xfe, 0x80, 0x80, 0x80, 0x80}, //0x4c L + {0xfe, 0x04, 0x18, 0x04, 0xfe}, //0x4d M + {0xfe, 0x0c, 0x10, 0x60, 0xfe}, //0x4e N + {0x7c, 0x82, 0x82, 0x82, 0x7c}, //0x4f O + {0xfe, 0x12, 0x12, 0x12, 0x0c}, //0x50 P + {0x7c, 0x82, 0xa2, 0x42, 0xbc}, //0x51 Q + {0xfe, 0x12, 0x32, 0x52, 0x8c}, //0x52 R + {0x4c, 0x92, 0x92, 0x92, 0x64}, //0x53 S + {0x02, 0x02, 0xfe, 0x02, 0x02}, //0x54 T + {0x7e, 0x80, 0x80, 0x80, 0x7e}, //0x55 U + {0x3e, 0x40, 0x80, 0x40, 0x3e}, //0x56 V + {0x7e, 0x80, 0x70, 0x80, 0x7e}, //0x57 W + {0xc6, 0x28, 0x10, 0x28, 0xc6}, //0x58 X + {0x0e, 0x10, 0xe0, 0x10, 0x0e}, //0x59 Y + {0xc2, 0xa2, 0x92, 0x8a, 0x86}, //0x5a Z + {0x00, 0xfe, 0x82, 0x82, 0x00}, //0x5b [ + {0x04, 0x08, 0x10, 0x20, 0x40}, //0x5c backslash + {0x00, 0x82, 0x82, 0xfe, 0x00}, //0x5d ] + {0x08, 0x04, 0x02, 0x04, 0x08}, //0x5e ^ + {0x80, 0x80, 0x80, 0x80, 0x80}, //0x5f _ + {0x00, 0x02, 0x04, 0x08, 0x00}, //0x60 ` + {0x40, 0xa8, 0xa8, 0xa8, 0xf0}, //0x61 a + {0xfe, 0x88, 0x88, 0x88, 0x70}, //0x62 b + {0x70, 0x88, 0x88, 0x88, 0x50}, //0x63 c + {0x70, 0x88, 0x88, 0x88, 0xfe}, //0x64 d + {0x70, 0xa8, 0xa8, 0xa8, 0xb0}, //0x65 e + {0x10, 0xfc, 0x12, 0x02, 0x04}, //0x66 f + {0x10, 0xa8, 0xa8, 0xa8, 0x78}, //0x67 g + {0xfe, 0x08, 0x08, 0x08, 0xf0}, //0x68 h + {0x00, 0x08, 0xfa, 0x00, 0x00}, //0x69 i + {0x40, 0x80, 0x88, 0x7a, 0x00}, //0x6a j + {0xfe, 0x20, 0x50, 0x88, 0x00}, //0x6b k + {0x00, 0x82, 0xfe, 0x80, 0x00}, //0x6c l + {0xf8, 0x08, 0x70, 0x08, 0xf0}, //0x6d m + {0xf8, 0x10, 0x08, 0x08, 0xf0}, //0x6e n + {0x70, 0x88, 0x88, 0x88, 0x70}, //0x6f o + {0xf8, 0x48, 0x48, 0x48, 0x30}, //0x70 p + {0x30, 0x48, 0x48, 0x48, 0xf8}, //0x71 q + {0x00, 0xf8, 0x10, 0x08, 0x10}, //0x72 r + {0x90, 0xa8, 0xa8, 0xa8, 0x48}, //0x73 s + {0x08, 0x7e, 0x88, 0x80, 0x40}, //0x74 t + {0x78, 0x80, 0x80, 0x40, 0xf8}, //0x75 u + {0x38, 0x40, 0x80, 0x40, 0x38}, //0x76 v + {0x78, 0x80, 0x60, 0x80, 0x78}, //0x77 w + {0x88, 0x50, 0x20, 0x50, 0x88}, //0x78 x + {0x98, 0xa0, 0xa0, 0xa0, 0x78}, //0x79 y + {0x88, 0xc8, 0xa8, 0x98, 0x88}, //0x7a z + {0x00, 0x10, 0x6c, 0x82, 0x00}, //0x7b { + {0x00, 0x00, 0xfe, 0x00, 0x00}, //0x7c | + {0x00, 0x82, 0x6c, 0x10, 0x00}, //0x7d } + {0x04, 0x02, 0x04, 0x08, 0x04} //0x7e ~ +}; + + +// ============================================================================ +// init +// ============================================================================ +void st7565r_init() +{ +// OED = 0xFF; + + // ---------------------------------------------------- + // initialization sequence + // + // note: - The circut must have a pulldown resistor + // for the RST line, because the controller + // pins in HiZ state on startup. + // ---------------------------------------------------- + lcd_7565r_init(); + + st7565r_cmd_lcdbias(0); // LCD bias + st7565r_cmd_adcsel(1); // ADC + st7565r_cmd_coms(0); // Common Ouput Mode + +// st7565r_cmd_v0reg( 0x03); // v0reg = 4.5 (0x03) + lcd_7565r_send( 0x25, 0); + + + +// st7565r_cmd_evol( 0x12); // evol = 31 (0x1F) + st7565r_cmd_evol( 0x1F); // 38 + + + st7565r_cmd_power(0x07); // + st7565r_cmd_boost(0x00); // boost = 3x,4x + + lcd_7565r_send( 0x40, 0); + +// lcd_7565r_send( 0xa7, 0); // inverse + +// lcd_7565r_send( 0xac, 0); +// lcd_7565r_send( 0x00, 0); + + lcd_7565r_send( 0xaf, 0); + + + st7565r_cls(); + +// st7565r_gotoxy(0,0); st7565r_puts("ABCDEFGHIJKLMNOPQRSTUV",22); +// st7565r_gotoxy(0,1); st7565r_puts("abcdefghijklmnopqrstuv",22); +// st7565r_gotoxy(0,2); st7565r_puts("0123456789WXYZwxyz()[]",22); +// st7565r_gotoxy(0,3); st7565r_puts("{}!\"#$\%&'*/+-._~^`<=>?",22); + + // ---------------------------------------------------- + // deactivate + // ---------------------------------------------------- + lcd_7565r_deactivate(); +} + +// ============================================================================ +// Display Normal/Reverse (means: inverse) +// ============================================================================ +void st7565r_cmd_reverse( BYTE rev) +{ + rev &= 0x01; + lcd_7565r_send( 0xA6 | rev, 0); +} + +// ============================================================================ +// Display All Points ON/OFF +// ============================================================================ +void st7565r_cmd_dispall( BYTE disp) +{ + disp &= 0x01; + lcd_7565r_send( 0xA4 | disp, 0); +} + +// ============================================================================ +// LCD Bias Set +// ============================================================================ +void st7565r_cmd_lcdbias( BYTE bias) +{ + bias &= 0x01; + lcd_7565r_send( 0xA2 | bias, 0); +} + +// ============================================================================ +// ADC select (means: right to left) +// ============================================================================ +void st7565r_cmd_adcsel( BYTE sel) +{ + sel &= 0x01; + lcd_7565r_send( 0xA0 | sel, 0); +} + +// ============================================================================ +// Common Output Mode Select +// ============================================================================ +void st7565r_cmd_coms( BYTE coms) +{ + coms = (coms & 0x01) << 3; + lcd_7565r_send( 0xC0 | coms, 0); +} + +// ============================================================================ +// V0 Voltage Regulator Internal Resistor Ratio Set (1+Rb/Ra) +// +// 0 0 0 - 3.0 +// 0 0 1 - 3.5 +// 0 1 0 - 4.0 +// 0 1 1 - 4.5 +// 1 0 0 - 5.0 +// 1 0 1 - 5.5 +// 1 1 0 - 6.0 +// 1 1 1 - 6.5 +// ============================================================================ +void st7565r_cmd_v0reg( BYTE reg) +{ + reg &= 0x07; + lcd_7565r_send( 0x20 | reg, 0); +} + +// ============================================================================ +// Electronic Volume Mode Set +// ============================================================================ +void st7565r_cmd_evol( BYTE vol) +{ + vol &= 0x3F; + lcd_7565r_send( 0x81, 0); + lcd_7565r_send( vol, 0); +} + +// ============================================================================ +// The Booster Ratio +// +// 0 0 - 2x,3x,4x +// 0 1 - 5x +// 1 1 - 6x +// ============================================================================ +void st7565r_cmd_boost( BYTE boost) +{ + boost &= 0x03; + lcd_7565r_send( 0xF8, 0); + lcd_7565r_send( boost,0); +} + +// ============================================================================ +// Power Constrol Set +// +// x x 1 - Voltage Follower On/Off +// x 1 x - Voltage Regulator On/Off +// 1 x x - Bosster Circuit On/Off +// ============================================================================ +void st7565r_cmd_power( BYTE power) +{ + power &= 0x07; + lcd_7565r_send( 0x28 | power, 0); +} + + +// ============================================================================ +// Clear Screen +// ============================================================================ +void st7565r_cls() +{ + BYTE i; + BYTE j; + + for( i=0; i<8; i++) + { + st7565r_gotoxy(0,i); // select page + + for( j=0; j< 0x84; j++) // clear line + lcd_7565r_send( 0x00, 1); + } + + st7565r_gotoxy(0,0); +} + +void st7565r_putc( char c) +{ + int i; + + c -= 32; + for(i=0;i<5;i++) + lcd_7565r_send( ascii[c][i],1); + + lcd_7565r_send( 0x00, 1); +} + +void st7565r_puts( char *s, BYTE len) +{ + BYTE i; + + for(i=0;i> 4) & 0x0F]; + BYTE x2 = bin2hex[(x >> 0) & 0x0F]; + + for(i=0;i<5;i++) lcd_7565r_send( ascii[x1][i],1); lcd_7565r_send( 0x00, 1); + for(i=0;i<5;i++) lcd_7565r_send( ascii[x2][i],1); lcd_7565r_send( 0x00, 1); +} + +void st7565r_gotoxy( BYTE x, BYTE y) +{ + BYTE hi; + BYTE lo; + + if( (x < 22) && (y < 8)) + { + x = x * 6; + hi = x >> 4; + lo = x & 0x0F; + + lcd_7565r_send( 0xB0 | y, 0); // set page address (line) + + lcd_7565r_send( 0x10 | hi, 0); // set column address to 0 + lcd_7565r_send( 0x00 | lo, 0); + } +} + +// ============================================================================ +// Put raw graphic data +// ============================================================================ +void st7565r_putg( BYTE *g, BYTE len) +{ + BYTE i; + + for(i=0; i7) { for(i=0;i<5;i++) lcd_7565r_send( ascii[x0][i],1); lcd_7565r_send( 0x00, 1); } + if(l>6) { for(i=0;i<5;i++) lcd_7565r_send( ascii[x1][i],1); lcd_7565r_send( 0x00, 1); } + if(l>5) { for(i=0;i<5;i++) lcd_7565r_send( ascii[x2][i],1); lcd_7565r_send( 0x00, 1); } + if(l>4) { for(i=0;i<5;i++) lcd_7565r_send( ascii[x3][i],1); lcd_7565r_send( 0x00, 1); } + if(l>3) { for(i=0;i<5;i++) lcd_7565r_send( ascii[x4][i],1); lcd_7565r_send( 0x00, 1); } + if(l>2) { for(i=0;i<5;i++) lcd_7565r_send( ascii[x5][i],1); lcd_7565r_send( 0x00, 1); } + if(l>1) { for(i=0;i<5;i++) lcd_7565r_send( ascii[x6][i],1); lcd_7565r_send( 0x00, 1); } + if(l>0) { for(i=0;i<5;i++) lcd_7565r_send( ascii[x7][i],1); lcd_7565r_send( 0x00, 1); } +} diff --git a/prj/tri.base/inc/tri.h b/prj/tri.base/inc/tri.h new file mode 100644 index 0000000..3a2b942 --- /dev/null +++ b/prj/tri.base/inc/tri.h @@ -0,0 +1,191 @@ +#ifndef TRI_H +#define TRI_H + +// trinity specific (must be moved somewhere else) +#define bmCap0_I2C 0x01 // has I2C bus +#define bmCap0_SER 0x02 // has serial ports (2) +#define bmCap0_EPR 0x04 // has flash EEPROM +#define bmCap0_RAM 0x08 // has 32k SRAM +#define bmCap0_JTG 0x10 // has standard JTAG + +#define bmCap1_LED 0x01 +#define bmCap1_LCD 0x02 +#define bmCap1_EXP 0x04 +#define bmCap1_LXP 0x08 +#define bmCap1_SDR 0x10 + +// ================================================================================================ +// LCD stuff +// ================================================================================================ +#ifdef LCD_7565 +#include +#endif + +#ifdef LCD_44780 +#include +#endif + +// ================================================================================================ +// USB interrupt hooks +// ================================================================================================ +extern void (*sudav) (void); + +extern void (*ep0ack) (void); // sudav used instead +extern void (*ep0out) (void); // sudav used instead +extern void (*ep0in ) (void); // sudav used instead + +extern void (*ep1out) (void); +extern void (*ep1in ) (void); + +extern void (*ep2inout) (void); // JTAG host->device +extern void (*ep4inout) (void); // JTAG device->host + +extern void (*ep6inout) (void); // for slave fifo or gpif highspeed transfer +extern void (*ep8inout) (void); // for slave fifo or gpif highspeed transfer + +extern bool (*DR_VendorCommand)(); + +// ================================================================================================ +// global variables +// ================================================================================================ +extern xdata BYTE devSerialNumber [8]; +extern xdata BYTE devCapabilities [8]; +extern xdata BYTE devIdentifier [8]; + +extern BYTE xdata sig[2]; +extern BYTE xdata crc[2]; + +extern xdata DEVICE_DSCR xdata *pDscrDevice; +extern xdata DEVICEQUAL_DSCR xdata *pDscrDeviceQual; + +extern xdata CONFIG_DSCR xdata *pDscrMainConfig; +extern xdata CONFIG_DSCR xdata *pDscrOthrConfig; +extern xdata CONFIG_DSCR xdata *pDscrFsConfig; +extern xdata CONFIG_DSCR xdata *pDscrHsConfig; + +extern data STRING_DSCR xdata *pDscrString; + + +// ============================================================================ +// ============================================================================ +// ============================================================================ +// +// IMPORTANT !!!! +// +// Keep this include file synchronized with jtag_state.s51 and Delphi +// sources !!! +// +// ============================================================================ +// ============================================================================ +// ============================================================================ + +// ============================================================================ +// JTAG states (Lattice VME values) +// ============================================================================ +#define TS_RESET 0 +#define TS_IDLE 1 +#define TS_IRPAUSE 2 +#define TS_DRPAUSE 3 +#define TS_IRSHIFT 4 +#define TS_DRSHIFT 5 +#define TS_DRCAPT 6 +#define TS_IREXIT1 7 +#define TS_DREXIT1 8 + +// ============================================================================ +// +// ENDPOINT 0 request codes +// +// reserved by cypress: +// 0x00 - 0x0C +// 0xA0 - 0xAF +// +// ============================================================================ + +// ---------------------------------------------------------------------------- +// JTAG commands 0xC0 - 0xCF +// ---------------------------------------------------------------------------- + + // interface commands + // ------------------------------- +#define CMD_JTAG_INIT 0xC0 // initialize JTAG interface +#define CMD_JTAG_RESET 0xC1 // reset JTAG interface +#define CMD_JTAG_ENABLE 0xC2 // enable physical I/O +#define CMD_JTAG_STATUS 0xC3 // get JTAG status + + // SVF,VME,... commands + // ------------------------------- +#define CMD_JTAG_ENDIR 0xC8 // +#define CMD_JTAG_ENDDR 0xC9 // +#define CMD_JTAG_STATE 0xCA // +#define CMD_JTAG_TRST 0xCB // + + // ------------------------------- +#define CMD_JTAG_TEST 0xCF // + +// ---------------------------------------------------------------------------- +// Trinity configuration commands 0xE0 - 0xE7 +// ---------------------------------------------------------------------------- +#define CMD_TRI_CAPS 0xE0 // get/set trinity board capabilities +#define CMD_TRI_SERIAL 0xE1 // get/set trinity board serial +#define CMD_TRI_IDENTIFIER 0xE2 // get/set trinity board identifier + +// ---------------------------------------------------------------------------- +// Trinity base peripheral commands 0xD0 - 0xDF +// ---------------------------------------------------------------------------- +#define CMD_TRI_IIC 0xD0 // IIC read/write +#define CMD_TRI_SER 0xD8 // serial read/write + +// ---------------------------------------------------------------------------- +// LCD/LED commands +// ---------------------------------------------------------------------------- +#define CMD_LCD_LED 0x40 // + +#define CMD_LCD_CLS 0x50 // +#define CMD_LCD_GOTOXY 0x51 // +#define CMD_LCD_PUTC 0x52 // +#define CMD_LCD_PUTS 0x53 // + +// ============================================================================= +// +// ENDPOINT 1 request codes +// +// +// ============================================================================= +#define CMD_IIC_WRITE 0x00 // IIC write + +#define CMD_IIC_READ 0x00 // IIC read +#define CMD_IIC_READ_RSW 0x01 // IIC read w/ repeated start cond. 16 +#define CMD_IIC_READ_RSB 0x02 // IIC read w/ repeated start cond. 8 + +#define CMD_IIC_WAIT 0x1F // wait for a device + // (e.g: wait for eeprom write finish) + +#define CMD_EEP_WRITE 0x20 // EEPROM write +#define CMD_EEP_READ 0x20 // EEPROM read + + +// ============================================================================= +// +// ENDPOINT 2 request codes +// +// ============================================================================= +// ----------------------------------------------------------------------------- +// JTAG commands 0xC0 - 0xCF +// +// These commands may transfer huge amount of data or take long time to run, +// so they are implemented as EP2 commands. +// ---------------------------------------------------------------------------- + + // interface commands + // ------------------------------- +#define CMD_JTAG_SCAN 0xC0 // scan JTAG chain + + // SVF,VME,... commands + // ------------------------------- +#define CMD_JTAG_SIR 0xC1 // write/read +#define CMD_JTAG_SDR 0xC2 // write/read +#define CMD_JTAG_RUN 0xC3 // +#define CMD_JTAG_SDW 0xC4 // write only + +#endif diff --git a/prj/tri.base/src/tri_boot.c b/prj/tri.base/src/tri_boot.c new file mode 100644 index 0000000..163adcf --- /dev/null +++ b/prj/tri.base/src/tri_boot.c @@ -0,0 +1,9 @@ +#include +#include + +extern bool tri_command(void); + +void tri_boot(void) +{ + DR_VendorCommand = tri_command; +} diff --git a/prj/tri.base/src/tri_cmd.c b/prj/tri.base/src/tri_cmd.c new file mode 100644 index 0000000..0f09d97 --- /dev/null +++ b/prj/tri.base/src/tri_cmd.c @@ -0,0 +1,113 @@ +#include +#include +#include + +#include + +extern xdata BYTE devSerialNumber []; +extern xdata BYTE devCapabilities []; +extern xdata BYTE devIdentifier []; + +xdata i2c_buffer[64]; + +// ================================================================================================ +// tri_command +// +// Common trinity commands implementation. The functions are: +// +// - read serial number +// - read capabilities +// - read identifier +// - iic read +// - eeprom read (todo) +// +// - write identifier +// - iic write +// - eeprom write (todo) +// +// ================================================================================================ +bool tri_command() +{ + bool result = true; + + bit dir = (SETUPDAT[0] & 0x80) ? 1 : 0; + BYTE cmd = SETUPDAT[1]; // (SETUPDAT[1] & 0x7F); + + PSUDAV sud = (PSUDAV)SETUPDAT; + + + // ---------------------------------------------------- + // IN command device -> host + // ---------------------------------------------------- + if(dir) + { + switch(sud->Request) + { + // -------------------------------------------- + // Get Serial Number + // -------------------------------------------- + case CMD_TRI_SERIAL: + SUDPTRH = MSB(devSerialNumber); + SUDPTRL = LSB(devSerialNumber); + + break; + + // -------------------------------------------- + // Get Capabilities + // -------------------------------------------- + case CMD_TRI_CAPS: + SUDPTRH = MSB(devCapabilities); + SUDPTRL = LSB(devCapabilities); + + break; + + // -------------------------------------------- + // Get Identifier + // -------------------------------------------- + case CMD_TRI_IDENTIFIER: + SUDPTRH = MSB(devIdentifier); + SUDPTRL = LSB(devIdentifier); + + break; + + // -------------------------------------------- + // I2C read + // -------------------------------------------- + case CMD_TRI_IIC: + break; + + // -------------------------------------------- + // default (invalid command) + // -------------------------------------------- + default: +// result = false; + + break; + } + } + + // ---------------------------------------------------- + // OUT command host -> device + // ---------------------------------------------------- + else + { + switch(cmd) + { + // -------------------------------------------- + // Set Identifier + // -------------------------------------------- + case CMD_TRI_IDENTIFIER: + break; + + // -------------------------------------------- + // default (invalid command) + // -------------------------------------------- + default: +// result = false; + + break; + } + } + + return result; +} diff --git a/prj/tri.base/src/tri_conf.c b/prj/tri.base/src/tri_conf.c new file mode 100644 index 0000000..993192c --- /dev/null +++ b/prj/tri.base/src/tri_conf.c @@ -0,0 +1,349 @@ +#include +#include +#include +#include +#include +#include + +#include + +STRING_DSCR xdata * GetStringDscr( BYTE index); + +extern void tri_sudav( void); +extern void tri_ep1out( void); + +// ================================================================================================ +// tri_conf +// ================================================================================================ +void tri_conf() +{ + int i; + +#ifdef LCD_7565 + // ------------------------------------------------------------------------ + // For LCD (7565r), the following pins are used for LCD interface: + // + // RST - PD.6 + // CS - PD.5 + // A0 - PD.4 + // SCL - PD.3 + // SI - PD.1 + // ------------------------------------------------------------------------ + IOD = 0x00; + OED = 0xFF; +#endif + +#ifdef LCD_44780 + // ------------------------------------------------------------------------ + // LED and LCD display + // + // bit dir init function + // ------------------------------------------ + // PD.0 - - (FPGA) + // + // PD.1 out 0 LCD R/W + // PD.2 out 0 LCD R/S + // PD.3 out 0 LCD E + // + // PD.4 out 0 LED 0 + // PD.5 out 0 LED 1 + // PD.6 out 0 LED 2 + // PD.7 out 0 LED 3 + // + // PE.0 out 0 LCD D0 + // PE.1 out 0 LCD D1 + // PE.2 out 0 LCD D2 + // PE.3 out 0 LCD D3 + // PE.4 out 0 LCD D4 + // PE.5 out 0 LCD D5 + // PE.6 out 0 LCD D6 + // PE.7 out 0 LCD D7 + // + // ------------------------------------------------------------------------ + IOD = 0x00; // PD[1,2,3] lcd 44780 ctrl PD[4,5,6,7] leds + IOE = 0x00; // lcd 44780 data + + OEE = 0xFF; // + OED = 0xFE; // +#endif + +#ifdef DEBUG + lcd_init(); + lcd_cls(); + lcd_gotoxy(1,1); + lcd_putc('X'); + lcd_gotoxy(0,0); +#endif + + // ======================================================================== + // + // USB Descriptor Tables + // + // ======================================================================== + pDscrString = (STRING_DSCR xdata *)&DscrString; + pDscrDevice = (DEVICE_DSCR xdata *)&DscrDevice; + pDscrDeviceQual = (DEVICEQUAL_DSCR xdata *)&DscrDeviceQual; + + pDscrHsConfig = (CONFIG_DSCR xdata *)&DscrHsConfig; + pDscrFsConfig = (CONFIG_DSCR xdata *)&DscrFsConfig; + + pDscrMainConfig = pDscrHsConfig; + pDscrOthrConfig = pDscrFsConfig; + + pDscrMainConfig->type = DSCR_CONFIG; + pDscrOthrConfig->type = DSCR_OTHERSPEED; + + // ======================================================================== + // + // EP1 + // + // ======================================================================== + EP1OUTCFG = 0xB0; SYNCDELAY; // valid, out, bulk, 64, 1x + EP1INCFG = 0xB0; SYNCDELAY; // valid, in, bulk, 64, 1x + + // ------------------------------------------------------------------------ + // EP1 usb interrupt handlers + // ------------------------------------------------------------------------ + ep1out = tri_ep1out; + ep1in = 0; // not needed + + // -------------------------------------------------------------- + // Out endpoints do not come up armed. + // Arm the EP1OUT endpoint by writing the byte count. + // -------------------------------------------------------------- + EP1OUTBC = 0x40; SYNCDELAY; // arm EP1 output endpoint + + // -------------------------------------------------------------- + // Enable EP1 interrupts + // -------------------------------------------------------------- + EPIE |= (bmEP1IN | bmEP1OUT); + + // ======================================================================== + // Enable INT2 and INT4 autovectoring + // ------------------------------------------------------------------------ + INTSETUP |= (bmAV2EN | bmAV4EN); + + // ------------------------------------------------------------------------ + // EP0 USB interrupt handlers + // ------------------------------------------------------------------------ + sudav = tri_sudav; + + // ------------------------------------------------------------------------ + // Enable interrupts + // ------------------------------------------------------------------------ + USB_IRQ_ENABLE(); // Enable USB interrupts + RSM_IRQ_ENABLE(); // Enable Wake-up/resume interrupt + + // ------------------------------------------------------------------------ + // Enable USB interrupts + // ------------------------------------------------------------------------ + USBIE |= bmSUDAV | + bmSUTOK | + bmSUSP | + bmURES | + bmHSGRANT; + + // ======================================================================== + // + // I2C + // + // ======================================================================== + fx2_i2c_init(); + + // ======================================================================== + // + // Read configuration data from eeprom + // + // ======================================================================== + EA = 1; + +// FX2_EEPROM_Read( 511, 0, 2, sig ); +// FX2_EEPROM_Read( 511, 2, 8, devSerialNumber ); +// FX2_EEPROM_Read( 511, 10, 8, devCapabilities ); +// FX2_EEPROM_Read( 511, 18, 8, devIdentifier ); +// FX2_EEPROM_Read( 511, 30, 2, crc ); + + // ------------------------------------------------------------------------ + // check data + // ------------------------------------------------------------------------ + + + // ------------------------------------------------------------------------ + // if data is corrupt, clear the configuration variables. + // ------------------------------------------------------------------------ + for( i=0; i<8; i++) + { + devCapabilities [i] = 0; + devSerialNumber [i] = 0; + devIdentifier [i] = 0; + } + + devSerialNumber[0] = 'T'; + devSerialNumber[1] = '1'; + + devCapabilities[0] |= bmCap0_I2C; + devCapabilities[0] |= bmCap0_EPR; + +/* + buf[0] = 0x33; + buf[1] = 0x75; + buf[2] = 0xEF; + buf[3] = 0xAA; + buf[4] = 0x30; + buf[5] = 0x31; + buf[6] = 0x32; + buf[7] = 0x33; + + dly[0] = 1; + dly[1] = 0; + dly[2] = 0; + dly[3] = 0; + dly[4] = 1; + dly[5] = 0; + dly[6] = 4; + dly[7] = 0; + + + + fx2_usart_init( 9600, uc8e1); + fx2_usart_send( 4, buf, dly); + + fx2_usart_send( 4, &buf[4], &dly[4]); +// SBUF0 = 0xaa; +// SBUF1 = 0x31; + +// fx2_i2c_read( 0x55, 3, buf); +// fx2_i2c_write( 0x55, 5, buf); +*/ +} + +// ================================================================================================ +// ================================================================================================ +// ================================================================================================ +// +// LCD 7565r support +// +// ================================================================================================ +// ================================================================================================ +// ================================================================================================ +#ifdef LCD_7565 + +#define PIN_RST PD6 +#define PIN_CS PD5 +#define PIN_A0 PD4 +#define PIN_SCL PD3 +#define PIN_SI PD1 + +// ------------------------------------------------------------------------------------------------ +// lcd init +// ------------------------------------------------------------------------------------------------ +void lcd_7565r_init(void) +{ + PIN_CS = 1; // unselect the chip + PIN_RST = 0; // RST + FX2_Delay(10); // delay 10 ms + + PIN_RST = 1; // release RST line + FX2_Delay(1); // delay 1 ms + PIN_CS = 0; // select the chip +} + +// ------------------------------------------------------------------------------------------------ +// lcd deactivate +// ------------------------------------------------------------------------------------------------ +void lcd_7565r_deactivate(void) +{ + PIN_RST = 1; // make sure reset line is released + PIN_CS = 0; // unselect display + + PIN_A0 = 0; // + PIN_SI = 0; // + PIN_SCL = 0; // +} + +// ------------------------------------------------------------------------------------------------ +// lcd send +// ------------------------------------------------------------------------------------------------ +void lcd_7565r_send( BYTE d, bit a0) +{ + BYTE i; + + PIN_A0 = 0; + + for( i=0; i<8; i++) + { + PIN_SI = (d & (1 << (7-i))) ? 1 : 0; + PIN_A0 = (i == 7) ? a0 : 0; + PIN_SCL = 1; + PIN_SCL = 0; + } +} + +#endif + +// ================================================================================================ +// ================================================================================================ +// ================================================================================================ +// +// LCD 44780 support +// +// ================================================================================================ +// ================================================================================================ +// ================================================================================================ +#ifdef LCD_44780 + +#define LED_3 PD7 +#define LED_2 PD6 +#define LED_1 PD5 +#define LED_0 PD4 + +#define LCD_E PD3 +#define LCD_RS PD2 +#define LCD_RW PD1 + +#define LCD_DATA IOE + +// ------------------------------------------------------------------------------------------------ +// lcd_4478_write_led +// ------------------------------------------------------------------------------------------------ +void lcd_44780_write_led( BYTE n, BYTE v) +{ + switch(n) + { + case 0: LED_0 = (v) ? 1 : 0; break; + case 1: LED_1 = (v) ? 1 : 0; break; + case 2: LED_2 = (v) ? 1 : 0; break; + case 3: LED_3 = (v) ? 1 : 0; break; + } +} + +// ------------------------------------------------------------------------------------------------ +// lcd_44780_write_ctrl +// ------------------------------------------------------------------------------------------------ +void lcd_44780_write_ctrl( unsigned char value) +{ + LCD_E = 1; + LCD_DATA = value; + LCD_E = 0; + + LCD_RW = 0; + LCD_RS = 0; +} + +// ------------------------------------------------------------------------------------------------ +// lcd_44780_write_data +// ------------------------------------------------------------------------------------------------ +void lcd_44780_write_data( unsigned char value) +{ + LCD_RW = 0; + LCD_RS = 1; + + LCD_E = 1; + LCD_DATA = value; + LCD_E = 0; + + LCD_RW = 0; + LCD_RS = 0; +} + +#endif diff --git a/prj/tri.base/src/tri_dscr.s51 b/prj/tri.base/src/tri_dscr.s51 new file mode 100644 index 0000000..8912a84 --- /dev/null +++ b/prj/tri.base/src/tri_dscr.s51 @@ -0,0 +1,309 @@ +;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +;; +;; File : fx2_dscr.asm +;; Contents : This file contains descriptor data tables. +;; +;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +DSCR_DEVICE equ 1 ;; Descriptor type: Device +DSCR_CONFIG equ 2 ;; Descriptor type: Configuration +DSCR_STRING equ 3 ;; Descriptor type: String +DSCR_INTRFC equ 4 ;; Descriptor type: Interface +DSCR_ENDPNT equ 5 ;; Descriptor type: Endpoint +DSCR_DEVQUAL equ 6 ;; Descriptor type: Device Qualifier + +ET_CONTROL equ 0 ;; Endpoint type: Control +ET_ISO equ 1 ;; Endpoint type: Isochronous +ET_BULK equ 2 ;; Endpoint type: Bulk +ET_INT equ 3 ;; Endpoint type: Interrupt + +DSCR_DEVICE_LEN equ 18 +DSCR_CONFIG_LEN equ 9 +DSCR_INTRFC_LEN equ 9 +DSCR_ENDPNT_LEN equ 7 +DSCR_DEVQUAL_LEN equ 10 + +DIR_OUT equ 0 +DIR_IN equ 080H + + + PUBLIC DscrDevice + PUBLIC DscrDeviceQual + PUBLIC DscrHsConfig + PUBLIC DscrFsConfig + PUBLIC DscrString + + DSCR SEGMENT CODE PAGE + rseg DSCR + + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; + ;; Device Descriptor + ;; + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +DscrDevice: + db DSCR_DEVICE_LEN ;; Descriptor length + db DSCR_DEVICE ;; Decriptor type + db 00 ;; Specification Version (BCD) (L) + db 02 ;; Specification Version (BCD) (H) + db 0FFH ;; Device class + db 0FFH ;; Device sub-class + db 0FFH ;; Device sub-sub-class + db 64 ;; Maximum packet size for EP0 + + db 0D0h ;; Vendor ID (L) + db 016h ;; Vendor ID (H) + db 012h ;; Product ID (L) + db 007h ;; Product ID (H) + + db 00h ;; Product version ID (L) + db 00h ;; Product version ID (H) + db 1 ;; Manufacturer string index + db 2 ;; Product string index + db 0 ;; Serial number string index + db 1 ;; Number of configurations + +DscrDeviceQual: + db DSCR_DEVQUAL_LEN ;; Descriptor length + db DSCR_DEVQUAL ;; Decriptor type + dw 0002H ;; Specification Version (BCD) + db 0FFH ;; Device class + db 0FFH ;; Device sub-class + db 0FFH ;; Device sub-sub-class + db 64 ;; Maximum packet size for other speed + db 1 ;; Number of configurations + db 0 ;; Reserved + + + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; + ;; Full Speed Configuration (DEFAULT) + ;; + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + DSCR_FS SEGMENT CODE PAGE + rseg DSCR_FS + +DscrFsConfig: + ;; ==================================================================== + ;; Configuration Descriptor + ;; ==================================================================== + db DSCR_CONFIG_LEN ;; Descriptor length + db DSCR_CONFIG ;; Descriptor type + + db (DscrFsConfigEnd-DscrFsConfig) mod 256 ;; Total Length (LSB) + db (DscrFsConfigEnd-DscrFsConfig) / 256 ;; Total Length (MSB) + + db 1 ;; Number of interfaces + db 9 ;; Configuration number + db 0 ;; Configuration string + db 01000000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu) + db 50 ;; Power requirement (div 2 ma) + + ;; ==================================================================== + ;; Interface 0, Alternate Setting 0 + ;; ==================================================================== + db DSCR_INTRFC_LEN ;; Descriptor length + db DSCR_INTRFC ;; Descriptor type + db 0 ;; Zero-based index of this interface + db 0 ;; Alternate setting + db 2 ;; Number of end points + db 0ffH ;; Interface class + db 0ffH ;; Interface sub class + db 0ffH ;; Interface sub sub class + db 0 ;; Interface descriptor string index + + ;; -------------------------------------------------------------------- + ;; Endpoint Descriptor 01 (64 bytes bulk mode) + ;; -------------------------------------------------------------------- + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 01H + DIR_OUT ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 40H ;; Maximum packet size (LSB) + db 00H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + + ;; -------------------------------------------------------------------- + ;; Endpoint Descriptor 81 (64 bytes bulk mode) + ;; -------------------------------------------------------------------- + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 01H + DIR_IN ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 40H ;; Maximum packet size (LSB) + db 00H ;; Maximum packet size (MSB) + db 00H ;; Polling interval +DscrFsConfigEnd: + + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; + ;; High Speed Configuration + ;; + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + DSCR_HS SEGMENT CODE PAGE + rseg DSCR_HS + +DscrHsConfig: + ;; ==================================================================== + ;; Configuration Descriptor + ;; ==================================================================== + db DSCR_CONFIG_LEN ;; Descriptor length + db DSCR_CONFIG ;; Descriptor type + + db (DscrHsConfigEnd-DscrHsConfig) mod 256 ;; Total Length (LSB) + db (DscrHsConfigEnd-DscrHsConfig) / 256 ;; Total Length (MSB) + + db 1 ;; Number of interfaces + db 1 ;; Configuration number + db 0 ;; Configuration string + db 10000000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu) + db 45 ;; Power requirement (div 2 mA) + + ;; ==================================================================== + ;; Interface Descriptor + ;; ==================================================================== + db DSCR_INTRFC_LEN ;; Descriptor length + db DSCR_INTRFC ;; Descriptor type + db 0 ;; Zero-based index of this interface + db 0 ;; Alternate setting + db 4 ;; Number of end points + db 0ffH ;; Interface class + db 00H ;; Interface sub class + db 00H ;; Interface sub sub class + db 0 ;; Interface descriptor string index + + ;; ==================================================================== + ;; Endpoint Descriptor 01 (out, interrupt, 1x, 64) 01 + ;; ==================================================================== + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 01H + DIR_OUT ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 40H ;; Maximum packet size (LSB) + db 00H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + + ;; ==================================================================== + ;; Endpoint Descriptor 01 (in, interrupt, 1x, 64) 81 + ;; ==================================================================== + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 01H + DIR_IN ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 40H ;; Maximum packet size (LSB) + db 00H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + + ;; ==================================================================== + ;; Endpoint Descriptor 02 (out, bulk, 2x, 512) 02 + ;; ==================================================================== + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 02H + DIR_OUT ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 00H ;; Maximum packet size (LSB) + db 02H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + + ;; ==================================================================== + ;; Endpoint Descriptor 04 (in, bulk, 2x, 512) 84 + ;; ==================================================================== + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 04H + DIR_IN ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 00H ;; Maximum packet size (LSB) + db 02H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + + ;; ==================================================================== + ;; Endpoint Descriptor 06 (out, bulk, 2x, 512) 06 + ;; ==================================================================== + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 06H + DIR_OUT ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 00H ;; Maximum packet size (LSB) + db 02H ;; Maximum packet size (MSB) + db 00H ;; Polling interval + + ;; ==================================================================== + ;; Endpoint Descriptor 08 (in, bulk, 2x, 512) 88 + ;; ==================================================================== + db DSCR_ENDPNT_LEN ;; Descriptor length + db DSCR_ENDPNT ;; Descriptor type + db 08H + DIR_IN ;; Endpoint number, and direction + db ET_BULK ;; Endpoint type + db 00H ;; Maximum packet size (LSB) + db 02H ;; Maximum packet size (MSB) + db 00H ;; Polling interval +DscrHsConfigEnd: + + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; + ;; String Descriptors + ;; + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + ;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + DSCR_ST SEGMENT CODE PAGE + rseg DSCR_ST + +DscrString: + +String0: + db String0End-String0 + db DSCR_STRING + db ' ',00 +String0End: + +String1: + db String1End-String1 + db DSCR_STRING + db 'M', 00 + db 'R', 00 + db ' ', 00 + db 'D', 00 + db 'e', 00 + db 'v', 00 + db 'i', 00 + db 'c', 00 + db 'e', 00 + db 's', 00 + db 00, 00 +String1End: + +String2: + db String2End-String2 + db DSCR_STRING + db 'T', 00 + db 'r', 00 + db 'i', 00 + db 'n', 00 + db 'i', 00 + db 't', 00 + db 'y', 00 + db 00, 00 +String2End: + +UserDscr: + dw 0000H + + END \ No newline at end of file diff --git a/prj/tri.base/src/tri_glb.c b/prj/tri.base/src/tri_glb.c new file mode 100644 index 0000000..39e094d --- /dev/null +++ b/prj/tri.base/src/tri_glb.c @@ -0,0 +1,19 @@ +#include +#include +#include +#include +#include +#include + +void (*main_hook)() = 0; +void (*idle_hook)() = 0; + +// ================================================================================================ +// global variables +// ================================================================================================ +xdata BYTE devSerialNumber [8] _at_ 0xE000; +xdata BYTE devCapabilities [8] _at_ 0xE008; +xdata BYTE devIdentifier [8] _at_ 0xE010; + +BYTE xdata sig[2]; +BYTE xdata crc[2]; diff --git a/prj/tri.base/src/tri_main.c b/prj/tri.base/src/tri_main.c new file mode 100644 index 0000000..42f2c6c --- /dev/null +++ b/prj/tri.base/src/tri_main.c @@ -0,0 +1,73 @@ +// ================================================================================================ +// CY_TRINITY +// +// CY_TRINITY boards built on Cypress' FX2LP chip, CY7C68013A. +// The firmware assumes that, the boards have a 16 kB I2C EEPROM memory at address 0x51. +// The last page (32 byte) of the EEPROM is reserved for board identification. +// The rest of the EEPROM is reserved for permanent firmware. +// +// ================================================================================================ +#include +#include + +#ifdef RTX51TNY +#include +#endif + +extern void tri_conf(); +extern void tri_boot(); + +extern void (*main_hook)(); +extern void (*idle_hook)(); + +// ================================================================================================ +// main() +// ================================================================================================ +#ifdef RTX51TNY +void tri_main(void) _task_ 0 +#else +void main(void) +#endif + +{ + // ------------------------------------------------------------------- + // + // INITIALIZE BASE HARDWARE/ENDPOINTS + // + // ------------------------------------------------------------------- + FX2_Init(); + + tri_conf(); + tri_boot(); + + // ------------------------------------------------------------------- + // Renumerate if necessary. Do this by checking the renum bit. If it + // is already set, no need to renumerate. The renum bit will already + // set if this firmware was loaded from eeprom. + // ------------------------------------------------------------------- + if( !(USBCS & bmRENUM)) + FX2_Disconnect(true); + + // ------------------------------------------------------------------- + // Unconditionally re-connect. If we loaded from eeprom we are + // disconnected and need to connect. If we just renumerated, this is + // not necessary but doesn't hurt anything. + // ------------------------------------------------------------------- + USBCS &= ~bmDISCON; + + // ------------------------------------------------------------------- + // call main hook for starting board specific tasks, e.g.: jtag + // ------------------------------------------------------------------- + if( main_hook) + main_hook(); + + // ------------------------------------------------------------------- + // idle + // ------------------------------------------------------------------- + while(1) + { + if( idle_hook) + idle_hook(); + } +} + diff --git a/prj/tri.base/src/tri_usb_ep1.c b/prj/tri.base/src/tri_usb_ep1.c new file mode 100644 index 0000000..029f953 --- /dev/null +++ b/prj/tri.base/src/tri_usb_ep1.c @@ -0,0 +1,131 @@ +#include +#include +#include +#include +#include +//#include + +#define DATAINPTR ((BYTE xdata *)&EP1INBUF [8]) +#define DATAOUTPTR ((BYTE xdata *)&EP1OUTBUF[8]) + + +//extern BYTE fx2_i2c_read( BYTE, BYTE, BYTE xdata *); + + +// ================================================================================================ +// EP1 +// +// Default processing of I2C and EEPROM packets. Inherited EP1 packet handlers normally +// don't override I2C and EEPROM packet processing. They implement (most of the time) new +// features, which have simple data transfer only. EP1 is not intented to use for transfering +// large amount of data, e.g.: jtag, or LA stream. +// +// BUF[0] : dir[7] + command[6..0] +// BUF[1] : address +// BUF[2] : address ext +// BUF[3] : subaddress[lo]/eeprom page address[lo] +// BUF[4] : subaddress[hi]/eeprom page address[lo] +// BUF[5] : length (max 32) +// BUF[6] : offset +// BUF[7] : timeout in ms +// ================================================================================================ +void tri_ep1out( void) +{ + bool rd; // true if eeprom/i2c xfer operation is read + BYTE cmd; // the actual command + + WORD address; // device address + address extension + WORD subaddr; // sub address for repeated start read + WORD page; // eeprom page number + BYTE length; // data length + BYTE offset; // offset in eeprom page + BYTE tmo; // timeout + + // ------------------------------------------------------ + // parse command + // ------------------------------------------------------ + rd = EP1OUTBUF[0] & 0x80; + cmd = EP1OUTBUF[0] & 0x7F; + + address = *(WORD*)&EP1OUTBUF[1]; // I2C address + subaddr = *(WORD*)&EP1OUTBUF[3]; // sub address for RS + page = *(WORD*)&EP1OUTBUF[3]; // page number + length = *(BYTE*)&EP1OUTBUF[5]; // data length + offset = *(BYTE*)&EP1OUTBUF[6]; // offset in page + tmo = *(BYTE*)&EP1OUTBUF[7]; // timeout + + if( length > 132) + length = 132; + + // ------------------------------------------------------ + // prepare status block + // ------------------------------------------------------ + EP1INBUF[0] = EP1OUTBUF[0]; + EP1INBUF[1] = EP1OUTBUF[1]; + EP1INBUF[2] = EP1OUTBUF[2]; + EP1INBUF[3] = EP1OUTBUF[3]; + EP1INBUF[4] = EP1OUTBUF[4]; + EP1INBUF[5] = EP1OUTBUF[5]; + EP1INBUF[6] = EP1OUTBUF[6]; + EP1INBUF[7] = I2C_OK; + + if(rd) + { + switch(cmd) + { + case CMD_IIC_READ: + EP1INBUF[7] = fx2_i2c_read( address, length, DATAINPTR); + EP1INBC = 8 +length; + break; + + case CMD_IIC_READ_RSW: + EP1INBUF[7] = fx2_i2c_read_rsw( address, subaddr, length, DATAINPTR); + EP1INBC = 8 +length; + break; +/* + case 1://CMD_EEPROM_BOOT: + EP1INBUF[7] = FX2_EEPROM_ReadPage0( 0,8, DATAINPTR); + EP1INBC = 8 +8; + break; + + case 2://CMD_EEPROM_RAW: + EP1INBUF[7] = FX2_EEPROM_ReadPage( page, 32, DATAINPTR); + EP1INBC = 8 +32; + break; +*/ + default: + EP1INBC = 8; + } + } + + else + { +// *(WORD*)&EP1INBUF[6] = length; + + switch(cmd) + { + case CMD_IIC_WRITE: + EP1INBUF[7] = fx2_i2c_write( address, length, DATAOUTPTR); +/* + lcd_gotoxy( 0, 1); + lcd_putx2(EP1OUTBUF[0]); + lcd_putx2(EP1OUTBUF[1]); + lcd_putx2(EP1OUTBUF[2]); + lcd_putx2(EP1OUTBUF[3]); + lcd_putx2(EP1OUTBUF[4]); + lcd_putx2(EP1OUTBUF[5]); + lcd_putx2(EP1OUTBUF[6]); + lcd_putx2(EP1OUTBUF[7]); +*/ + break; + + case 1://CMD_EEPROM_RAW: + EP1INBUF[7] = FX2_EEPROM_WritePage( page, 32, DATAOUTPTR); + break; + } + + EP1INBC = 8; + } + + EP1OUTBC = 0x40; // re-arm EP1OUT +} diff --git a/prj/tri.base/tri_base.uvgui.roka b/prj/tri.base/tri_base.uvgui.roka new file mode 100644 index 0000000..0955c72 --- /dev/null +++ b/prj/tri.base/tri_base.uvgui.roka @@ -0,0 +1,1860 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + release + 0x0 + MCS-51 + + 48000000 + + 1 + 0 + 1 + 0 + 0 + + + 0 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\lst\release\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 255 + + + 0 + Data Sheet + DATASHTS\CYPRESS\CY7C68XXX_DS.PDF + + + 1 + Technical Reference Manual + DATASHTS\CYPRESS\FX2_TRM.PDF + + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + -1 + + + + + + + + + + + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + debug + 0x0 + MCS-51 + + 48000000 + + 1 + 0 + 1 + 0 + 0 + + + 0 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\lst\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Data Sheet + DATASHTS\CYPRESS\CY7C68XXX_DS.PDF + + + 1 + Technical Reference Manual + DATASHTS\CYPRESS\FX2_TRM.PDF + + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\MON51.DLL + + + + 0 + DLGTP51 + (98=-1,-1,-1,-1,0)(82=-1,-1,-1,-1,0)(83=-1,-1,-1,-1,0)(84=-1,-1,-1,-1,0)(85=-1,-1,-1,-1,0)(99=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(91=-1,-1,-1,-1,0)(92=-1,-1,-1,-1,0)(94=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(5065=-1,-1,-1,-1,0) + + + 0 + MON51 + -S5 -B38400 -O1311 + + + 0 + DLGDP51 + (98=-1,-1,-1,-1,0)(82=-1,-1,-1,-1,0)(83=-1,-1,-1,-1,0)(84=-1,-1,-1,-1,0)(85=-1,-1,-1,-1,0)(99=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(91=-1,-1,-1,-1,0)(92=-1,-1,-1,-1,0)(94=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(5065=-1,-1,-1,-1,0) + + + + + + 1 + 0 + 0 + 0 + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + fx2lp - startup + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_startup.s51 + fx2_startup.s51 + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_conf.s51 + fx2_conf.s51 + 0 + 0 + + + + + fx2lp - init + 1 + 0 + 0 + 0 + + 2 + 3 + 2 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_delay1ms.s51 + fx2_delay1ms.s51 + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_delay.c + fx2_delay.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_globals.c + fx2_globals.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_init.c + fx2_init.c + 0 + 0 + + + + + fx2lp - iic + 0 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_i2c.c + fx2_i2c.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_eeprom.c + fx2_eeprom.c + 0 + 0 + + + + + fx2lp - timer + 0 + 0 + 0 + 0 + + 4 + 9 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_tmr.c + fx2_tmr.c + 0 + 0 + + + + + fx2lp - serial + 0 + 0 + 0 + 0 + + 5 + 10 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_usart.c + fx2_usart.c + 0 + 0 + + + + + fx2lp - usb + 0 + 0 + 0 + 0 + + 6 + 11 + 2 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_jmptbl.s51 + fx2_jmptbl.s51 + 0 + 0 + + + 6 + 12 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_disconnect.c + fx2_disconnect.c + 0 + 0 + + + 6 + 13 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_usb_isr.c + fx2_usb_isr.c + 0 + 0 + + + 6 + 14 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_usb_sleep.c + fx2_usb_sleep.c + 0 + 0 + + + 6 + 15 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_usb_sudav.c + fx2_usb_sudav.c + 0 + 0 + + + + + fx2mr - lcd + 0 + 0 + 0 + 0 + + 7 + 16 + 1 + 1 + 0 + 0 + ..\..\lib\fx2mr\src\lcd\7565r\lcd_7565r.c + lcd_7565r.c + 0 + 0 + + + + + tri - base + 1 + 0 + 0 + 0 + + 8 + 17 + 2 + 0 + 0 + 0 + .\src\tri_dscr.s51 + tri_dscr.s51 + 0 + 0 + + + 8 + 18 + 1 + 0 + 0 + 0 + .\src\tri_main.c + tri_main.c + 0 + 0 + + + 8 + 19 + 1 + 1 + 0 + 0 + .\src\tri_boot.c + tri_boot.c + 0 + 0 + + + 8 + 20 + 1 + 0 + 0 + 0 + .\src\tri_conf.c + tri_conf.c + 0 + 0 + + + 8 + 21 + 1 + 0 + 0 + 0 + .\src\tri_glb.c + tri_glb.c + 0 + 0 + + + 8 + 22 + 1 + 0 + 0 + 0 + .\src\tri_cmd.c + tri_cmd.c + 0 + 0 + + + 8 + 23 + 1 + 0 + 0 + 0 + .\src\tri_usb_ep1.c + tri_usb_ep1.c + 0 + 0 + + + + diff --git a/prj/tri.base/tri_base.uvproj b/prj/tri.base/tri_base.uvproj new file mode 100644 index 0000000..5939277 --- /dev/null +++ b/prj/tri.base/tri_base.uvproj @@ -0,0 +1,1219 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + release + 0x0 + MCS-51 + 0 + + + EZ-USB FX2LP (CY7C68XXX-X) + Cypress + IRAM(0-0xFF) IROM(0-0x3FFF) XRAM(0xE000-0xE1FF) CLOCK(48000000) MODDP2 + + "LIB\STARTUP.A51" ("Standard 8051 Startup Code") + + 3787 + FX2REGS.H + + + + + + + + + + + 0 + 1 + C:\Tools\mcu\Keil\C51\BIN\ + C:\Tools\mcu\Keil\C51\INC;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\lib\fx2lp\inc;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\lib\fx2mr\inc;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\prj\tri.base\inc + + + Cypress\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\release\ + tri_base + 1 + 0 + 1 + 1 + 1 + .\lst\release\ + 0 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd /c md bin\release + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd /c move obj\release\*.hex bin\release\ + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + 65535 + + + S8051.DLL + + DP51.DLL + -pFX2 + S8051.DLL + + TP51.DLL + -pFX2 + + + + 0 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 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+ + + + + + + + + + + + + + fx2lp - init + + + fx2_delay1ms.s51 + 2 + ..\..\lib\fx2lp\src\fx2_delay1ms.s51 + + + fx2_delay.c + 1 + ..\..\lib\fx2lp\src\fx2_delay.c + + + fx2_globals.c + 1 + ..\..\lib\fx2lp\src\fx2_globals.c + + + fx2_init.c + 1 + ..\..\lib\fx2lp\src\fx2_init.c + + + + + fx2lp - iic + + + fx2_i2c.c + 1 + ..\..\lib\fx2lp\src\fx2_i2c.c + + + fx2_eeprom.c + 1 + ..\..\lib\fx2lp\src\fx2_eeprom.c + + + + + fx2lp - timer + + + fx2_tmr.c + 1 + ..\..\lib\fx2lp\src\fx2_tmr.c + + + + + fx2lp - serial + + + fx2_usart.c + 1 + ..\..\lib\fx2lp\src\fx2_usart.c + + + + + fx2lp - usb + + + fx2_jmptbl.s51 + 2 + ..\..\lib\fx2lp\src\fx2_jmptbl.s51 + + + fx2_disconnect.c + 1 + ..\..\lib\fx2lp\src\fx2_disconnect.c + + + fx2_usb_isr.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_isr.c + + + fx2_usb_sleep.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_sleep.c + + + fx2_usb_sudav.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_sudav.c + + + + + fx2mr - lcd + + + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 0 + 65535 + + + + 2 + 2 + 2 + 2 + 2 + 8 + 10 + 3 + 2 + 2 + 2 + 0 + + + + + + + + + 2 + 2 + 2 + 2 + + + + + + + + + + + + lcd_7565r.c + 1 + ..\..\lib\fx2mr\src\lcd\7565r\lcd_7565r.c + + + + + tri - base + + + tri_dscr.s51 + 2 + .\src\tri_dscr.s51 + + + tri_main.c + 1 + .\src\tri_main.c + + + tri_boot.c + 1 + .\src\tri_boot.c + + + tri_conf.c + 1 + .\src\tri_conf.c + + + tri_glb.c + 1 + .\src\tri_glb.c + + + tri_cmd.c + 1 + .\src\tri_cmd.c + + + tri_usb_ep1.c + 1 + .\src\tri_usb_ep1.c + + + + + + + debug + 0x0 + MCS-51 + 0 + + + EZ-USB FX2LP (CY7C68XXX-X) + Cypress + IRAM(0-0xFF) IROM(0-0x3FFF) XRAM(0xE000-0xE1FF) CLOCK(48000000) MODDP2 + + "LIB\STARTUP.A51" ("Standard 8051 Startup Code") + + 3787 + FX2REGS.H + + + + + + + + + + + 0 + 1 + C:\Tools\mcu\Keil\C51\BIN\ + C:\Tools\mcu\Keil\C51\INC;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\lib\fx2lp\inc;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\lib\fx2mr\inc;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\prj\tri.base\inc + + + Cypress\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\debug\ + tri_base + 1 + 0 + 1 + 1 + 1 + .\lst\debug\ + 0 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd /c md bin\debug + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd /c move obj\debug\*.hex bin\debug + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + 65535 + + + S8051.DLL + + DP51.DLL + -pFX2 + S8051.DLL + + TP51.DLL + -pFX2 + + + + 0 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 0 + + + + + + + + + + + + + + BIN\MON51.DLL + + + + + 0 + 0 + 0 + 0 + 0 + -1 + + 0 + + "" () + + + + + 0 + + + + 2 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0xffff + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x4000 + + + 0 + 0x0 + 0x100 + + + 0 + 0xe000 + 0x200 + + + 0 + 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fx2lp - serial + + + fx2_usart.c + 1 + ..\..\lib\fx2lp\src\fx2_usart.c + + + 2 + 0 + 0 + 0 + 0 + 2 + 2 + 1 + 1 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + 2 + 8 + 10 + 3 + 2 + 2 + 2 + 0 + + + + + + + + + + + + + + fx2lp - usb + + + fx2_jmptbl.s51 + 2 + ..\..\lib\fx2lp\src\fx2_jmptbl.s51 + + + fx2_disconnect.c + 1 + ..\..\lib\fx2lp\src\fx2_disconnect.c + + + fx2_usb_isr.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_isr.c + + + fx2_usb_sleep.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_sleep.c + + + fx2_usb_sudav.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_sudav.c + + + + + fx2mr - lcd + + + lcd_7565r.c + 1 + ..\..\lib\fx2mr\src\lcd\7565r\lcd_7565r.c + + + + + tri - base + + + tri_dscr.s51 + 2 + .\src\tri_dscr.s51 + + + tri_main.c + 1 + .\src\tri_main.c + + + tri_boot.c + 1 + .\src\tri_boot.c + + + tri_conf.c + 1 + .\src\tri_conf.c + + + tri_glb.c + 1 + .\src\tri_glb.c + + + tri_cmd.c + 1 + .\src\tri_cmd.c + + + tri_usb_ep1.c + 1 + .\src\tri_usb_ep1.c + + + + + + + + diff --git a/prj/tri.cf1/src/cf1_boot.c b/prj/tri.cf1/src/cf1_boot.c new file mode 100644 index 0000000..c1bbe2e --- /dev/null +++ b/prj/tri.cf1/src/cf1_boot.c @@ -0,0 +1,16 @@ +#include + +extern bool (*DR_VendorCommand)(void); +extern void (*main_hook)(void); + +extern void cf1_conf(void); +extern void cf1_main(void); +extern bool cf1_command(void); + +void TRI_Boot(void) +{ + cf1_conf(); + + main_hook = cf1_main; + DR_VendorCommand = cf1_command; +} \ No newline at end of file diff --git a/prj/tri.cf1/src/cf1_cmd.c b/prj/tri.cf1/src/cf1_cmd.c new file mode 100644 index 0000000..1cb542e --- /dev/null +++ b/prj/tri.cf1/src/cf1_cmd.c @@ -0,0 +1,92 @@ +#include +#include + +#include +#include + +extern bool jtag_command(void); + +// ============================================================================ +// command +// ============================================================================ +bool cf1_command(void) +{ + bool result = true; + + bit dir = (SETUPDAT[0] & 0x80) ? 1 : 0; + BYTE cmd = SETUPDAT[1]; // (SETUPDAT[1] & 0x7F); + PSUDAV sud = (PSUDAV)SETUPDAT; + + BYTE X = SETUPDAT[2]; + BYTE Y = SETUPDAT[3]; + BYTE C = SETUPDAT[3]; + + BYTE LED = SETUPDAT[2]; + BYTE VAL = SETUPDAT[3]; + +//#ifdef DEBUG +// lcd_gotoxy(0,0); +// lcd_putx2(cmd); +// lcd_putx2(X); +// lcd_putx2(Y); +// lcd_putled( 3, 1); +//#endif + + // ---------------------------------------------------- + // IN command device -> host + // ---------------------------------------------------- + if(dir) + { + switch(sud->Request) + { + // -------------------------------------------- + // default + // -------------------------------------------- + default: + result = jtag_command(); + break; + } + } + + // ---------------------------------------------------- + // OUT command host -> device + // ---------------------------------------------------- + else + { + switch(sud->Request) + { + // -------------------------------------------- + // display commands + // -------------------------------------------- + case CMD_LCD_LED: + lcd_putled( LED, VAL); + break; + + case CMD_LCD_CLS: + lcd_gotoxy(0,0); lcd_puts(" "); + lcd_gotoxy(0,1); lcd_puts(" "); + break; + + case CMD_LCD_GOTOXY: + lcd_gotoxy(X,Y); + break; + + case CMD_LCD_PUTC: + lcd_putc(C); + break; + + case CMD_LCD_PUTS: + lcd_putc(EP0BUF[0]); + break; + + // -------------------------------------------- + // default + // -------------------------------------------- + default: + result = jtag_command(); + break; + } + } + + return result; +} diff --git a/prj/tri.cf1/src/cf1_conf.c b/prj/tri.cf1/src/cf1_conf.c new file mode 100644 index 0000000..113ba9e --- /dev/null +++ b/prj/tri.cf1/src/cf1_conf.c @@ -0,0 +1,185 @@ +#include +#include +#include + +#include +#include + +#include + +extern xdata BYTE devSerialNumber []; +extern xdata BYTE devCapabilities []; +extern xdata BYTE devIdentifier []; + +extern void FX2_Delay(WORD); + +// inherited object routines +extern void jtag_main(void); +extern void jtag_conf(void); + +// ================================================================================================ +// main +// +// This routine is the place to start tasks ! +// ================================================================================================ +void cf1_main(void) +{ + // ------------------------------------------------------------------- + // call "inherited" main() + // ------------------------------------------------------------------- + jtag_main(); +} + +// ================================================================================================ +// configure board +// ================================================================================================ +void cf1_conf() +{ + // ------------------------------------------------------------------------ + // call "inherited" config() + // ------------------------------------------------------------------------ + jtag_conf(); + + // ------------------------------------------------------------------------ + // set IFCLK to 30 MHz + // + // with 30 MHz the on-board SDRAM can run on 120 MHz + // with 48 MHz the on-board SDRAM can run on 144 or 96 MHz + // ------------------------------------------------------------------------ + IFCONFIG &= ~bm3048MHZ; SYNCDELAY; // 30 MHz + + // ------------------------------------------------------------------------ + // add capabilities + // ------------------------------------------------------------------------ + devCapabilities[1] |= bmCap1_LCD; + + // ------------------------------------------------------------------------ + // Board specific initialization + // + // TRINITY_2: + // - 4 layers board + // - 128 pin mcu + // - 32k SRAM for mcu + // - Lattice FPGA + // - 32M SDRAM for FPGA + // - LCD (44780) & LED port + // - 8 bit expansion port + // + // Not USB powered device. It must monitor USB power for + // correct working. Port C bit 5 is the monitoring bit. + // + // GPIF is not implemented in this firmware. It is just + // a suggestion. + // + // FPGA - programming + // + // bit dir init function + // ------------------------------------------ + // PC.0 out 0 TCK + // PC.1 out 1 TMS + // PC.2 out 1 TDI + // PC.3 in - TDO + // PC.4 out 1 PRGn + // + // FPGA - GPIF + // + // bit/pin dir init function + // ------------------------------------------ + // PC.6 out 0 GA[0] + // PC.7 out 0 GA[1] + // + // PB.0 in/out - GP[0] + // PB.1 in/out - GP[1] + // PB.2 in/out - GP[2] + // PB.3 in/out - GP[3] + // PB.4 in/out - GP[4] + // PB.5 in/out - GP[5] + // PB.6 in/out - GP[6] + // PB.7 in/out - GP[7] + // + // CTL0 out 0 CTL0 + // CTL1 out 0 CTL1 + // CTL2 out 0 CTL2 + // CTL3 out 0 CTL3 + // CTL4 out 0 CTL4 + // CTL5 out 0 CTL5 + // + // RDY0 in - RDY0 + // RDY1 in - RDY1 + // RDY2 in - RDY2 + // RDY3 in - RDY3 + // + // FPGA - MISC + // + // bit dir init function + // ------------------------------------------ + // PD.0 out (0) RESET + // IFCK out - CLK + // INT5 in (1) INT + // + // + // LED and LCD display + // + // bit dir init function + // ------------------------------------------ + // PD.0 - - (FPGA) + // + // PD.1 out 0 LCD R/W + // PD.2 out 0 LCD R/S + // PD.3 out 0 LCD E + // + // PD.4 out 0 LED 0 + // PD.5 out 0 LED 1 + // PD.6 out 0 LED 2 + // PD.7 out 0 LED 3 + // + // PE.0 out 0 LCD D0 + // PE.1 out 0 LCD D1 + // PE.2 out 0 LCD D2 + // PE.3 out 0 LCD D3 + // PE.4 out 0 LCD D4 + // PE.5 out 0 LCD D5 + // PE.6 out 0 LCD D6 + // PE.7 out 0 LCD D7 + // ------------------------------------------ + // + // Expansion Port + // + // bit dir init function + // ------------------------------------------ + // PA.0 i/o - PA.0 + // PA.1 out 0 PA.1 + // PA.2 out 0 PA.2 + // PA.3 out 0 PA.3 + // PA.4 out 0 PA.4 + // PA.5 out 0 PA.5 + // PA.6 out 0 PA.6 + // PA.7 out 0 PA.7 + // ------------------------------------------ + // + // MISC + // + // bit dir init function + // ------------------------------------------ + // PC.5 in (1) VMON + // PA.0 out 0 debug trigger 1 + // + // ------------------------------------------------------------------------ + PORTCCFG = 0x00; SYNCDELAY; // port C is I/O, not GPIFADDR + + IOC = 0xFE; // set default values + OEC = 0x17; // set port directions + + IOA = 0x00; // expansion port + OEA = 0x01; // + + devSerialNumber[0] = 'C'; + devSerialNumber[1] = '5'; + + EP0BCL = 0x40; SYNCDELAY; + + // ------------------------------------------------------------------- + // INITIALIZE LCD + // ------------------------------------------------------------------- + lcd_init(); +} diff --git a/prj/tri.cf1/src/cnc1/cnc1_boot.c b/prj/tri.cf1/src/cnc1/cnc1_boot.c new file mode 100644 index 0000000..dfd0e21 --- /dev/null +++ b/prj/tri.cf1/src/cnc1/cnc1_boot.c @@ -0,0 +1,17 @@ +#include + +extern bool (*DR_VendorCommand)(void); +extern void (*main_hook)(void); + +extern void cnc1_conf(void); +extern void cnc1_main(void); +extern bool cnc1_command(void); + +void tri_boot(void) +{ + cnc1_conf(); + + main_hook = cnc1_main; + DR_VendorCommand = cnc1_command; +} + diff --git a/prj/tri.cf1/src/cnc1/cnc1_cmd.c b/prj/tri.cf1/src/cnc1/cnc1_cmd.c new file mode 100644 index 0000000..432a89a --- /dev/null +++ b/prj/tri.cf1/src/cnc1/cnc1_cmd.c @@ -0,0 +1,51 @@ +#include +#include + +extern bool cf1_command(void); + +// ================================================================================================ +// Command +// ================================================================================================ +bool cnc1_command(void) +{ + bool result = true; + + bit dir = (SETUPDAT[0] & 0x80) ? 1 : 0; + BYTE cmd = SETUPDAT[1]; + PSUDAV sud = (PSUDAV)SETUPDAT; + + // ---------------------------------------------------- + // IN command device -> host + // ---------------------------------------------------- + if(dir) + { + switch(sud->Request) + { + // -------------------------------------------- + // default + // -------------------------------------------- + default: + result = cf1_command(); + break; + } + } + + // ---------------------------------------------------- + // OUT command host -> device + // ---------------------------------------------------- + else + { + switch(sud->Request) + { + // -------------------------------------------- + // default + // -------------------------------------------- + default: + result = cf1_command(); + break; + } + } + + return result; +} + diff --git a/prj/tri.cf1/src/cnc1/cnc1_conf.c b/prj/tri.cf1/src/cnc1/cnc1_conf.c new file mode 100644 index 0000000..3c63a20 --- /dev/null +++ b/prj/tri.cf1/src/cnc1/cnc1_conf.c @@ -0,0 +1,104 @@ +#include +#include +#include +#include + +#include + +#include + +extern xdata BYTE devSerialNumber []; +extern xdata BYTE devCapabilities []; +extern xdata BYTE devIdentifier []; + +extern void cf1_main(void); +extern void cf1_conf(void); + +extern void cnc1_ep6out(void); + +xdata BYTE buf[30]; + +// ================================================================================================ +// main +// ================================================================================================ +void cnc1_main(void) +{ + // ------------------------------------------------------------------------ + // call *inherited* main() + // ------------------------------------------------------------------------ + cf1_main(); + + // ------------------------------------------------------------------------ + // *cf1* specific main() + // ------------------------------------------------------------------------ + lcd_gotoxy(0,0); lcd_puts("X CNC1 X"); + lcd_gotoxy(0,1); lcd_puts("M M"); + + PD7 = 0; + PD6 = 1; + PD5 = 0; + PD4 = 1; + + buf[0] = 0; + buf[1] = 0x61; + buf[2] = 0x39; + + +// fx2_i2c_write( 0x10, 4, buf); + + + + fx2_i2c_write( 0x10, 1, buf); + fx2_i2c_read( 0x10, 4, buf); + + lcd_gotoxy( 2, 1); + lcd_putc(buf[0] & 0xDF); + lcd_putc(buf[1] & 0xDF); + lcd_putc(buf[2] & 0xDF); + lcd_putc(buf[3] & 0xDF); +} + +// ================================================================================================ +// configure +// ================================================================================================ +void cnc1_conf(void) +{ + // ------------------------------------------------------------------------ + // call *inherited* config() + // ------------------------------------------------------------------------ + cf1_conf(); + + // ------------------------------------------------------------------------ + // temp serial number + // ------------------------------------------------------------------------ + devSerialNumber[0] = 'N'; + devSerialNumber[1] = '5'; + + // ------------------------------------------------------------------------ + // Configure EP6/EP8 + // + // Endpoint 6 is the OUT endpoint for FPGA communication. + // Endpoint 8 is the IN endpoint for FPGA communication. + // ------------------------------------------------------------------------ + EP6CFG = EP_VALID | EP_OUT | EP_BULK | EP_512 | EP_2x; SYNCDELAY; + EP8CFG = EP_VALID | EP_IN | EP_BULK | EP_512 | EP_2x; SYNCDELAY; + + // ------------------------------------------------------------------------ + // Out endpoints do not come up armed. + // Since the EP6 is double buffered we must write dummy byte + // count twice. Arm EP6 by writing byte count w/skip flag. + // ------------------------------------------------------------------------ + EP6BCL = 0x80; SYNCDELAY; + EP6BCL = 0x80; SYNCDELAY; + + // ------------------------------------------------------------------------ + // Enable EP6/EP8 interrupts + // ------------------------------------------------------------------------ + EPIE |= (bmEP6 | bmEP8); + + // ------------------------------------------------------------------------ + // usb interrupt handler hooks + // ------------------------------------------------------------------------ + ep6inout = cnc1_ep6out; +} + diff --git a/prj/tri.cf1/src/cnc1/cnc1_ep6.c b/prj/tri.cf1/src/cnc1/cnc1_ep6.c new file mode 100644 index 0000000..c7b7e12 --- /dev/null +++ b/prj/tri.cf1/src/cnc1/cnc1_ep6.c @@ -0,0 +1,19 @@ +#include +#include + +#include + +// ================================================================================================ +// EP6OUT +// +// ================================================================================================ +void cnc1_ep6out(void) +{ + + + // ---------------------------------------------------------- + // Re-arm output endpoint EP6 + // ---------------------------------------------------------- + EP6BCL = 0x80; + +} diff --git a/prj/tri.cf1/src/modbus/mb_boot.c b/prj/tri.cf1/src/modbus/mb_boot.c new file mode 100644 index 0000000..3d7cb22 --- /dev/null +++ b/prj/tri.cf1/src/modbus/mb_boot.c @@ -0,0 +1,17 @@ +#include + +extern bool (*DR_VendorCommand)(void); +extern void (*main_hook)(void); + +extern void mb_conf(void); +extern void mb_main(void); +extern bool mb_command(void); + +void tri_boot(void) +{ + mb_conf(); + + main_hook = mb_main; + DR_VendorCommand = mb_command; +} + diff --git a/prj/tri.cf1/src/modbus/mb_cmd.c b/prj/tri.cf1/src/modbus/mb_cmd.c new file mode 100644 index 0000000..67d4d54 --- /dev/null +++ b/prj/tri.cf1/src/modbus/mb_cmd.c @@ -0,0 +1,48 @@ +#include +#include + +extern bool cf1_command(void); + +bool mb_command( void) +{ + bool result = true; + + bit dir = (SETUPDAT[0] & 0x80) ? 1 : 0; + BYTE cmd = SETUPDAT[1]; + PSUDAV sud = (PSUDAV)SETUPDAT; + + + // ---------------------------------------------------- + // IN command device -> host + // ---------------------------------------------------- + if(dir) + { + switch( sud->Request) + { + // -------------------------------------------- + // default + // -------------------------------------------- + default: + result = cf1_command(); + break; + } + } + + // ---------------------------------------------------- + // OUT command host -> device + // ---------------------------------------------------- + else + { + switch( sud->Request) + { + // -------------------------------------------- + // default + // -------------------------------------------- + default: + result = cf1_command(); + break; + } + } + + return result; +} diff --git a/prj/tri.cf1/src/modbus/mb_conf.c b/prj/tri.cf1/src/modbus/mb_conf.c new file mode 100644 index 0000000..78bf523 --- /dev/null +++ b/prj/tri.cf1/src/modbus/mb_conf.c @@ -0,0 +1,162 @@ +#include +#include +#include +#include + +#include + +#include +#include + +extern void cf1_main(void); +extern void cf1_conf(void); + + +BYTE xdata buf[10]; +BYTE xdata dly[10]; + + +// ================================================================================================= +// configure +// ================================================================================================= +void mb_conf( void) +{ + // ------------------------------------------------------------------------ + // call *inherited* config() + // ------------------------------------------------------------------------ + cf1_conf(); + + // ------------------------------------------------------------------------ + // temp serial number + // ------------------------------------------------------------------------ + devSerialNumber[0] = 'M'; + devSerialNumber[1] = 'B'; + devSerialNumber[2] = '1'; + + + devCapabilities[0] |= bmCap0_MBRTU; + devCapabilities[0] |= bmCap0_MBASC; + + // TEST only !!! + // ------------------------------------------------------------------------ + // initialize serial port + // ------------------------------------------------------------------------ + + //fx2_usart_init( 9600, uc8e1); + lcd_putled(3,1); + + mb_init( mbChannel1, mbRTU, 10, 9600, mbParityEven); + + + + + + +} + + +void FX2_Delay( WORD ms); + + + +// ================================================================================================= +// main +// ================================================================================================= +void mb_main( void) +{ + int i; + + // ------------------------------------------------------------------------ + // call *inherited* main() + // ------------------------------------------------------------------------ + cf1_main(); + + // ------------------------------------------------------------------------ + // TEST only !!! + // ------------------------------------------------------------------------ + // ------------------------------------------------------------------------ + // *modbus* specific main() + // ------------------------------------------------------------------------ + lcd_gotoxy(0,0); lcd_puts(" MODBUS "); + lcd_gotoxy(0,1); lcd_puts("> -- <"); + + + buf[0] = 0x10; + buf[0] = 0x3; + buf[1] = 40001 >> 8; + buf[2] = 40001 & 0xFF; + buf[3] = 0x00; + buf[4] = 0x01; + + buf[5] = 0x11; + buf[6] = 0x22; + buf[7] = 0x33; + + dly[0] = 0; + dly[1] = 0; + dly[2] = 0; + dly[3] = 0; + dly[4] = 0; + dly[5] = 0; + dly[6] = 0; + dly[7] = 0; + + + buf[0] = 31001 >> 8; + buf[1] = 31001; + buf[2] = 0; + buf[3] = 1; + buf[4] = 5; + buf[5] = 5; + +// fx2_i2c_write( 0x55, 6, buf); +// fx2_i2c_read( 0x55, 2, buf); + + buf[0] = 4; + buf[1] = 31001 >> 8; + buf[2] = 31001; + buf[3] = 0; + buf[4] = 1; + + + +// fx2_usart_send( 4, buf, dly); +// fx2_usart_send( 4, &buf[4], &dly[4]); + + +// for( i=0; i<35; i++) +// { +// lcd_putled(0,1); +// mb_send( mbChannel1, 2, 5, buf, 0); +// lcd_putled(0,0); +// +// FX2_Delay(100); +// +// } + + + + // -------------------------------------------------------------- + // set plc portparameters + // -------------------------------------------------------------- + buf[0] = 40006 >> 8; // register address + buf[1] = 40006; // + + buf[2] = 0; // number of words + buf[3] = 3; // number of words + + buf[4] = 0; // modbus address + buf[5] = 1; // + + buf[6] = 0; // speed + buf[7] = 48; // + + buf[8] = 0; // config + buf[9] = 1; + + fx2_i2c_write( 0x55, 10, buf); + + + + +} diff --git a/prj/tri.cf1/src_gpf/cnc1/cnc1.gpf b/prj/tri.cf1/src_gpf/cnc1/cnc1.gpf new file mode 100644 index 0000000..adc8f90 Binary files /dev/null and b/prj/tri.cf1/src_gpf/cnc1/cnc1.gpf differ diff --git a/prj/tri.cf1/tri_cf1.uvgui.roka b/prj/tri.cf1/tri_cf1.uvgui.roka new file mode 100644 index 0000000..81b2f9b --- /dev/null +++ b/prj/tri.cf1/tri_cf1.uvgui.roka @@ -0,0 +1,119 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + release + 0x0 + MCS-51 + 0 + + + EZ-USB FX2LP (CY7C68XXX-X) + Cypress + IRAM(0-0xFF) IROM(0-0x3FFF) XRAM(0xE000-0xE1FF) CLOCK(48000000) MODDP2 + + "LIB\STARTUP.A51" ("Standard 8051 Startup Code") + + 3787 + FX2REGS.H + + + + + + + + + + + 0 + 1 + C:\Tools\mcu\Keil\C51\BIN\ + C:\Tools\mcu\Keil\C51\INC;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\lib\fx2lp\inc;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\lib\fx2mr\inc;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\prj\tri.base\inc + + + Cypress\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\release\ + tri_cf1 + 1 + 0 + 1 + 1 + 1 + .\lst\release\ + 0 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd /c md bin\release + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd /c move obj\release\*.hex bin\release + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + 65535 + + + S8051.DLL + + DP51.DLL + -pFX2 + S8051.DLL + + TP51.DLL + -pFX2 + + + + 0 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + -1 + + + + + + + + + + + + + + + + + + + 0 + 0 + 0 + 0 + 0 + -1 + + 0 + + + + + + + 0 + + + + 2 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0xffff + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x4000 + + + 0 + 0x0 + 0x100 + + + 0 + 0xe000 + 0x200 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 1 + 0 + 1 + 3 + 8 + 2 + 1 + 1 + 0 + 0 + + + LCD_44780 + + + + + + 0 + 1 + 0 + 0 + + + BOARD_CF1 + + + + + + 0 + 0 + 0 + 0 + 2 + 1 + + + 15,16 + + + + + + + + + + + + + + + + 0X0000-0X3FFF + 0x4000-0x7FFF, 0xE000-0xE1FF + + + + + + + + + fx2lp - startup + + + fx2_startup.s51 + 2 + ..\..\lib\fx2lp\src\fx2_startup.s51 + + + fx2_conf.s51 + 2 + ..\..\lib\fx2lp\src\fx2_conf.s51 + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + fx2lp - init + + + fx2_delay1ms.s51 + 2 + ..\..\lib\fx2lp\src\fx2_delay1ms.s51 + + + fx2_delay.c + 1 + ..\..\lib\fx2lp\src\fx2_delay.c + + + fx2_globals.c + 1 + ..\..\lib\fx2lp\src\fx2_globals.c + + + fx2_init.c + 1 + ..\..\lib\fx2lp\src\fx2_init.c + + + + + fx2lp - iic + + + fx2_i2c.c + 1 + ..\..\lib\fx2lp\src\fx2_i2c.c + + + fx2_eeprom.c + 1 + ..\..\lib\fx2lp\src\fx2_eeprom.c + + + + + fx2lp - serial + + + fx2_usart.c + 1 + ..\..\lib\fx2lp\src\fx2_usart.c + + + + + fx2lp - usb + + + fx2_jmptbl.s51 + 2 + ..\..\lib\fx2lp\src\fx2_jmptbl.s51 + + + fx2_disconnect.c + 1 + ..\..\lib\fx2lp\src\fx2_disconnect.c + + + fx2_usb_isr.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_isr.c + + + fx2_usb_sleep.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_sleep.c + + + fx2_usb_sudav.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_sudav.c + + + + + fx2mr - jtag + + + jtag.s51 + 2 + ..\..\lib\fx2mr\src\jtag\jtag.s51 + + + + + fx2mr - lcd + + + lcd_44780.c + 1 + ..\..\lib\fx2mr\src\lcd\44780\lcd_44780.c + + + + + fx2mr - modbus + + + mb_crc.c + 1 + ..\..\lib\fx2mr\src\modbus\mb_crc.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + 2 + 8 + 10 + 3 + 2 + 2 + 2 + 0 + + + + + + + + + + + + mb.c + 1 + ..\..\lib\fx2mr\src\modbus\mb.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + 2 + 8 + 10 + 3 + 2 + 2 + 2 + 0 + + + + + + + + + + + + + + tri - base + + + tri_dscr.s51 + 2 + ..\tri.base\src\tri_dscr.s51 + + + tri_main.c + 1 + ..\tri.base\src\tri_main.c + + + tri_conf.c + 1 + ..\tri.base\src\tri_conf.c + + + tri_glb.c + 1 + ..\tri.base\src\tri_glb.c + + + tri_cmd.c + 1 + ..\tri.base\src\tri_cmd.c + + + tri_usb_ep1.c + 1 + ..\tri.base\src\tri_usb_ep1.c + + + + + tri - jtag + + + jtag_conf.c + 1 + ..\tri.jtag\src\jtag_conf.c + + + jtag_cmd.c + 1 + ..\tri.jtag\src\jtag_cmd.c + + + jtag_ep2.c + 1 + ..\tri.jtag\src\jtag_ep2.c + + + + + tri - cf1 + + + cf1_boot.c + 1 + .\src\cf1_boot.c + + + cf1_conf.c + 1 + .\src\cf1_conf.c + + + cf1_cmd.c + 1 + .\src\cf1_cmd.c + + + + + tri - cf1 - cnc1 + + + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + 2 + 8 + 10 + 3 + 2 + 2 + 2 + 0 + + + + + + + + + 2 + 2 + 2 + 2 + + + + + + + + + + + + cnc1_boot.c + 1 + .\src\cnc1\cnc1_boot.c + + + cnc1_conf.c + 1 + .\src\cnc1\cnc1_conf.c + + + cnc1_cmd.c + 1 + .\src\cnc1\cnc1_cmd.c + + + cnc1_ep6.c + 1 + .\src\cnc1\cnc1_ep6.c + + + + + + + cnc1 + 0x0 + MCS-51 + 0 + + + EZ-USB FX2LP (CY7C68XXX-X) + Cypress + IRAM(0-0xFF) IROM(0-0x3FFF) XRAM(0xE000-0xE1FF) CLOCK(48000000) MODDP2 + + "LIB\STARTUP.A51" ("Standard 8051 Startup Code") + + 3787 + FX2REGS.H + + + + + + + + + + + 0 + 1 + C:\Tools\mcu\Keil\C51\BIN\ + C:\Tools\mcu\Keil\C51\INC;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\lib\fx2lp\inc;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\lib\fx2mr\inc;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\prj\tri.base\inc + + + Cypress\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\cnc1\ + tri_cnc1 + 1 + 0 + 1 + 1 + 1 + .\lst\cnc1\ + 0 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd /c md bin\cnc1 + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd /c move obj\cnc1\*.hex bin\cnc1 + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + 65535 + + + S8051.DLL + + DP51.DLL + -pFX2 + S8051.DLL + + TP51.DLL + -pFX2 + + + + 0 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + -1 + + + + + + + + + + + + + + + + + + + 0 + 0 + 0 + 0 + 0 + -1 + + 0 + + + + + + + 0 + + + + 2 + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0xffff + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x4000 + + + 0 + 0x0 + 0x100 + + + 0 + 0xe000 + 0x200 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 1 + 0 + 1 + 3 + 8 + 2 + 1 + 1 + 0 + 0 + + + LCD_44780 + + + + + + 0 + 1 + 0 + 0 + + + BOARD_CF1 + + + + + + 0 + 0 + 1 + 0 + 2 + 1 + + + 15,16 + + + + + + + + 0X0000-0X3FFF + 0XE000-0XE1FF + + + + + + + + + + + + + + + + + fx2lp - startup + + + fx2_startup.s51 + 2 + ..\..\lib\fx2lp\src\fx2_startup.s51 + + + fx2_conf.s51 + 2 + ..\..\lib\fx2lp\src\fx2_conf.s51 + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + fx2lp - init + + + fx2_delay1ms.s51 + 2 + ..\..\lib\fx2lp\src\fx2_delay1ms.s51 + + + fx2_delay.c + 1 + ..\..\lib\fx2lp\src\fx2_delay.c + + + fx2_globals.c + 1 + ..\..\lib\fx2lp\src\fx2_globals.c + + + fx2_init.c + 1 + ..\..\lib\fx2lp\src\fx2_init.c + + + + + fx2lp - iic + + + fx2_i2c.c + 1 + ..\..\lib\fx2lp\src\fx2_i2c.c + + + fx2_eeprom.c + 1 + ..\..\lib\fx2lp\src\fx2_eeprom.c + + + + + fx2lp - serial + + + fx2_usart.c + 1 + ..\..\lib\fx2lp\src\fx2_usart.c + + + + + fx2lp - usb + + + fx2_jmptbl.s51 + 2 + ..\..\lib\fx2lp\src\fx2_jmptbl.s51 + + + fx2_disconnect.c + 1 + ..\..\lib\fx2lp\src\fx2_disconnect.c + + + fx2_usb_isr.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_isr.c + + + fx2_usb_sleep.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_sleep.c + + + fx2_usb_sudav.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_sudav.c + + + + + fx2mr - jtag + + + jtag.s51 + 2 + ..\..\lib\fx2mr\src\jtag\jtag.s51 + + + + + fx2mr - lcd + + + lcd_44780.c + 1 + ..\..\lib\fx2mr\src\lcd\44780\lcd_44780.c + + + + + fx2mr - modbus + + + mb_crc.c + 1 + ..\..\lib\fx2mr\src\modbus\mb_crc.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + 2 + 8 + 10 + 3 + 2 + 2 + 2 + 0 + + + + + + + + + + + + mb.c + 1 + ..\..\lib\fx2mr\src\modbus\mb.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + 2 + 8 + 10 + 3 + 2 + 2 + 2 + 0 + + + + + + + + + + + + + + tri - base + + + tri_dscr.s51 + 2 + ..\tri.base\src\tri_dscr.s51 + + + tri_main.c + 1 + ..\tri.base\src\tri_main.c + + + tri_conf.c + 1 + ..\tri.base\src\tri_conf.c + + + tri_glb.c + 1 + ..\tri.base\src\tri_glb.c + + + tri_cmd.c + 1 + ..\tri.base\src\tri_cmd.c + + + tri_usb_ep1.c + 1 + ..\tri.base\src\tri_usb_ep1.c + + + + + tri - jtag + + + jtag_conf.c + 1 + ..\tri.jtag\src\jtag_conf.c + + + jtag_cmd.c + 1 + ..\tri.jtag\src\jtag_cmd.c + + + jtag_ep2.c + 1 + ..\tri.jtag\src\jtag_ep2.c + + + + + tri - cf1 + + + cf1_boot.c + 1 + .\src\cf1_boot.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + 2 + 8 + 10 + 3 + 2 + 2 + 2 + 0 + + + + + + + + + + + + cf1_conf.c + 1 + .\src\cf1_conf.c + + + cf1_cmd.c + 1 + .\src\cf1_cmd.c + + + + + tri - cf1 - cnc1 + + + cnc1_boot.c + 1 + .\src\cnc1\cnc1_boot.c + + + cnc1_conf.c + 1 + .\src\cnc1\cnc1_conf.c + + + cnc1_cmd.c + 1 + .\src\cnc1\cnc1_cmd.c + + + cnc1_ep6.c + 1 + .\src\cnc1\cnc1_ep6.c + + + + + + + + diff --git a/prj/tri.jtag/src/jtag_boot.c b/prj/tri.jtag/src/jtag_boot.c new file mode 100644 index 0000000..ea4b57a --- /dev/null +++ b/prj/tri.jtag/src/jtag_boot.c @@ -0,0 +1,16 @@ +#include + +extern bool (*DR_VendorCommand)(void); +extern void (*main_hook)(void); + +extern void jtag_conf(void); +extern void jtag_main(void); +extern bool jtag_command(void); + +void TRI_Boot(void) +{ + jtag_conf(); + + main_hook = jtag_main; + DR_VendorCommand = jtag_command; +} diff --git a/prj/tri.jtag/src/jtag_cmd.c b/prj/tri.jtag/src/jtag_cmd.c new file mode 100644 index 0000000..1682578 --- /dev/null +++ b/prj/tri.jtag/src/jtag_cmd.c @@ -0,0 +1,96 @@ +#include +#include + +#include "..\tri.base\inc\tri.h" + +extern void jtag_init(void); +extern void jtag_tck(WORD); + +extern void jtag_set_endir(BYTE); +extern void jtag_set_enddr(BYTE); +extern void jtag_set_state(BYTE); +extern void jtag_xfer( BYTE xdata *buffer, WORD length, BYTE last); + +extern void FX2_Delay(WORD); +extern bool TRI_Command(void); + +// ================================================================================================ +// jtag_command +// ================================================================================================ +bool jtag_command(void) +{ + bool result = true; + + bit dir = (SETUPDAT[0] & 0x80) ? 1 : 0; + BYTE cmd = SETUPDAT[1]; // (SETUPDAT[1] & 0x7F); + PSUDAV sud = (PSUDAV)SETUPDAT; + + // ---------------------------------------------------- + // IN command device -> host + // ---------------------------------------------------- + if(dir) + { + result = TRI_Command(); + } + + // ---------------------------------------------------- + // OUT command host -> device + // ---------------------------------------------------- + else + { + switch(sud->Request) + { + // -------------------------------------------- + // JTAG INIT + // -------------------------------------------- + case CMD_JTAG_INIT: + jtag_init(); + break; + + // -------------------------------------------- + // JTAG ENDIR + // -------------------------------------------- + case CMD_JTAG_ENDIR: + jtag_set_endir(sud->Value.Byte.Lo); + break; + + // -------------------------------------------- + // JTAG ENDDR + // -------------------------------------------- + case CMD_JTAG_ENDDR: + jtag_set_enddr(sud->Value.Byte.Lo); + break; + + // -------------------------------------------- + // JTAG STATE + // -------------------------------------------- + case CMD_JTAG_STATE: + jtag_set_state(sud->Value.Byte.Lo); + break; + + // -------------------------------------------- + // JTAG RUNTEST + // -------------------------------------------- + case CMD_JTAG_RUN: + jtag_set_state(sud->Value.Byte.Lo); + jtag_tck( sud->Index.Word); + + break; + + // -------------------------------------------- + // JTAG TEST + // -------------------------------------------- + case CMD_JTAG_TEST: + break; + + // -------------------------------------------- + // default + // -------------------------------------------- + default: + result = TRI_Command(); + break; + } + } + + return result; +} diff --git a/prj/tri.jtag/src/jtag_conf.c b/prj/tri.jtag/src/jtag_conf.c new file mode 100644 index 0000000..a966493 --- /dev/null +++ b/prj/tri.jtag/src/jtag_conf.c @@ -0,0 +1,143 @@ +#include +#include +#include + +#include + +extern void jtag_init(void); +extern void jtag_ep2out(void); + +extern WORD sir; +extern WORD sdr; + +// inherited object routines +extern void tri_main(void); +extern void tri_conf(void); + +// ================================================================================================ +// main +// ================================================================================================ +void jtag_main(void) +{ + sir = 0; +} + +// ================================================================================================ +// configure +// ================================================================================================ +void jtag_conf() +{ + // ------------------------------------------------------------------------ + // call "inherited" config() + // ------------------------------------------------------------------------ + tri_conf(); + + // ------------------------------------------------------------------------ + // add capabilities + // ------------------------------------------------------------------------ + devCapabilities[0] |= bmCap0_JTG; + + // ------------------------------------------------------------------------ + // temp serial number + // ------------------------------------------------------------------------ + devSerialNumber[0] = 'Y'; + devSerialNumber[1] = '5'; + + // ======================================================================== + // USB configuration + // ======================================================================== + // ------------------------------------------------------------------------ + // Configure EP2/EP4 + // + // Endpoint 2 is the OUT endpoint for JTAG2 communication. + // Endpoint 4 is the IN endpoint for JTAG2 communication. + // ------------------------------------------------------------------------ + EP2CFG = EP_VALID | EP_OUT | EP_BULK | EP_512 | EP_2x; SYNCDELAY; + EP4CFG = EP_VALID | EP_IN | EP_BULK | EP_512 | EP_2x; SYNCDELAY; + + // ------------------------------------------------------------------------ + // Out endpoints do not come up armed. + // Since the EP2 is double buffered we must write dummy byte + // count twice. Arm EP2 by writing byte count w/skip flag. + // ------------------------------------------------------------------------ + EP2BCL = 0x80; SYNCDELAY; + EP2BCL = 0x80; SYNCDELAY; + + // ------------------------------------------------------------------------ + // Enable EP2/EP4 interrupts + // ------------------------------------------------------------------------ + EPIE |= (bmEP2 | bmEP4); + + // ------------------------------------------------------------------------ + // usb interrupt handler hooks + // ------------------------------------------------------------------------ + ep2inout = jtag_ep2out; + + // ======================================================================== + // Board specific initialization + // + // TRINITY_1: + // + // - 2 layers board + // - 56 pin mcu + // - 16 kB flash EEPROM + // + // J1 J2 + // -------------------------- -------------------------- + // GND - 1 2 - 5.0V SLWR - 1 2 - SLRD + // GND - 3 4 - 5.0V CLKOUT - 3 4 - GND + // PB.2 - 5 6 - PB.3 PD.5 - 5 6 - GND + // PB.1 - 7 8 - PB.0 PD.6 - 7 8 - PD.7 + // SCL - 9 10 - SDA 3.3V - 9 10 - 3.3V + // PB.6 - 11 12 - PB.7 3.3V - 11 12 - 3.3V + // PB.5 - 13 14 - PB.4 PD.4 - 13 14 - GND + // FLAG.B - 15 16 - FLAG.A PD.3 - 15 16 - PD.2 + // PA.2 - 17 18 - FLAG.C PD.1 - 17 18 - PD.0 + // PA.1 - 19 20 - PA.0 GND - 19 20 - GND + // PA.7 - 21 22 - PA.3 GND - 21 22 - GND + // PA.4 - 23 24 - GND GND - 23 24 - GND + // PA.5 - 25 26 - PA.5 RESET - 25 26 - WU + // + // + // JTAG TOP + // ---------------- + // T T G G P + // D C N N W + // I K D D R + // + // 9 7 5 3 1 + // 10 8 6 4 2 + // + // T T G G T + // R M N N D + // S S D D O + // T + // + // For JTAG function, the following pins are used for JTAG interface: + // + // TCK - PA.0 out + // TMS - PA.1 out + // TDI - PA.7 out + // TDO - PA.3 in + // ena - PA.4 out + // + // Keep it in sync with 'jtag_state.s51' !!! + // + // ======================================================================== + PORTCCFG = 0x00; // port C is I/O, not GPIFADDR + SYNCDELAY; + + IOA = 0x80; + OEA = 0x93; + + // ------------------------------------------------------------------------ + // INITIALZE PERIPHERALS (JTAG) + // ------------------------------------------------------------------------ + jtag_init(); + +#ifdef DEBUG + lcd_init(); + lcd_gotoxy(0,0); + lcd_puts("JTAG",4); +#endif +} diff --git a/prj/tri.jtag/src/jtag_ep2.c b/prj/tri.jtag/src/jtag_ep2.c new file mode 100644 index 0000000..a71795f --- /dev/null +++ b/prj/tri.jtag/src/jtag_ep2.c @@ -0,0 +1,182 @@ +#include +#include + +#include + +extern void jtag_set_state(BYTE); +extern void jtag_xfer( BYTE xdata *, WORD, BYTE); + +WORD sir = 0; +WORD sdr = 0; + +void reverse_id( BYTE xdata * id) +{ + int i; + BYTE tmp; + + for(i=0; i<4; i++) + { + tmp = id[i]; + id[i] = 0; + + if( tmp & 0x01) id[i] |= 0x80; + if( tmp & 0x02) id[i] |= 0x40; + if( tmp & 0x04) id[i] |= 0x20; + if( tmp & 0x08) id[i] |= 0x10; + if( tmp & 0x10) id[i] |= 0x08; + if( tmp & 0x20) id[i] |= 0x04; + if( tmp & 0x40) id[i] |= 0x02; + if( tmp & 0x80) id[i] |= 0x01; + } +} + + +// ================================================================================================ +// EP2OUT +// +// Default processing of JTAG output packets. This task will also enable EP4 to handle +// JTAG 'in' requests. But because there is nothing to do after a packet sent to the host, +// the default interrupt handler will do just fine. No special handling is necessary. +// +// Note: +// Because the jtag commands, SCAN,SDR,SIR always prepare data for the host, +// it must be read by the host even if it doesn't need the data !!!! +// ================================================================================================ +void jtag_ep2out(void) +{ + BYTE fin = 0; + BYTE cmd = 0; + BYTE idx = 0; + WORD len = 0; + WORD adr = 0; + + int i; + + // ---------------------------------------------------------- + // check for hook + // ---------------------------------------------------------- +// if( fx2_ep2_hook && fx2_ep2_hook()) +// continue; + + // ---------------------------------------------------------- + // if no hook defined or the hook didn't process the packet, + // then process it here. + // ---------------------------------------------------------- + cmd = EP2FIFOBUF[0]; + fin = EP2FIFOBUF[1]; + idx = EP2FIFOBUF[2]; + len = EP2FIFOBUF[3] + EP2FIFOBUF[2] * 256; + adr = EP2FIFOBUF[5] + EP2FIFOBUF[4] * 256; + + EP4FIFOBUF[0] = EP2FIFOBUF[0]; + EP4FIFOBUF[1] = 0; + EP4FIFOBUF[2] = EP2FIFOBUF[2]; + EP4FIFOBUF[3] = EP2FIFOBUF[3]; + EP4FIFOBUF[4] = EP2FIFOBUF[4]; + EP4FIFOBUF[5] = EP2FIFOBUF[5]; + EP4FIFOBUF[6] = EP2FIFOBUF[6]; + EP4FIFOBUF[7] = EP2FIFOBUF[7]; + + switch(cmd) + { + // ------------------------------------------------------ + // JTAG: SCAN + // ------------------------------------------------------ + case CMD_JTAG_SCAN: + jtag_set_state(TS_RESET); + jtag_set_state(TS_DRSHIFT); + + for(i=0; i<4*8; i++) + EP4FIFOBUF[12+i] = 0x00; + + jtag_xfer( &EP4FIFOBUF[12], 4*8, 1); + + for(i=0; i<4; i++) + { + reverse_id( &EP4FIFOBUF[12+i*8]); + + if( EP4FIFOBUF[12+i*8] == 0) + break; + } + + EP4FIFOBUF[ 8] = i; + EP4FIFOBUF[ 9] = 0; + EP4FIFOBUF[10] = 0; + EP4FIFOBUF[11] = 0; + + EP4BCH = 1; + EP4BCL = 0; + + break; + + // ------------------------------------------------------ + // JTAG: SIR + // ------------------------------------------------------ + case CMD_JTAG_SIR: + jtag_set_state(TS_IRSHIFT); + jtag_xfer(&EP2FIFOBUF[8], len, fin); + + len = (len + 7) / 8; + + for(idx=8; idx<8+len; idx++) + EP4FIFOBUF[idx] = EP2FIFOBUF[idx]; + +#ifdef DEBUG + sir++; + lcd_gotoxy(0,0); + st7565r_putd( sir, 4, false); +#endif + + EP4BCH = MSB(8+len); + EP4BCL = LSB(8+len); + + break; + + // ------------------------------------------------------ + // JTAG: SDR + // + // write/read data shift + // ------------------------------------------------------ + case CMD_JTAG_SDR: + jtag_set_state(TS_DRSHIFT); + jtag_xfer(&EP2FIFOBUF[8], len, fin); + + len = (len + 7) / 8; + + for(idx=8; idx<8+len; idx++) + EP4FIFOBUF[idx] = EP2FIFOBUF[idx]; + +#ifdef DEBUG + sdr++; + lcd_gotoxy(0,1); + st7565r_putd( sdr, 4, false); +#endif + + EP4BCH = MSB(8+len); + EP4BCL = LSB(8+len); + + break; + + // ------------------------------------------------------ + // JTAG: SDW + // + // writeonly data shift + // ------------------------------------------------------ + case CMD_JTAG_SDW: + jtag_set_state(TS_DRSHIFT); + jtag_xfer(&EP2FIFOBUF[8], len, fin); + +#ifdef DEBUG + sdr++; + lcd_gotoxy(0,1); + st7565r_putd( sdr, 4, false); +#endif + break; + } + + + // ---------------------------------------------------------- + // Re-arm output endpoint EP2 + // ---------------------------------------------------------- + EP2BCL = 0x80; +} diff --git a/prj/tri.jtag/tri_jtag.uvgui.roka b/prj/tri.jtag/tri_jtag.uvgui.roka new file mode 100644 index 0000000..81b2f9b --- /dev/null +++ b/prj/tri.jtag/tri_jtag.uvgui.roka @@ -0,0 +1,119 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
+ + + + + + + + + + 38003 + Registers + 228 229 + + + 346 + Code Coverage + 293 160 + + + 204 + Performance Analyzer + 453 + + + + + + 35141 + Event Statistics + + 200 50 700 + + + 1506 + Symbols + + 106 106 106 + + + 1936 + Watch 1 + + 200 133 133 + + + 1937 + Watch 2 + + 200 133 133 + + + 1935 + Call Stack + Locals + + 200 133 133 + + + 2506 + Trace Data + + 75 135 130 95 70 230 200 150 + + + 466 + Source Browser + 500 + 300 + + + + + + + + 1 + 1 + 0 + 0 + -1 + + + + + + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 228 + 231 + 1892 + 1333 + + + + 0 + + 366 + 01000000040000000100000001000000010000000100000000000000020000000000000001000000010000000000000028000000280000000100000002000000010000000100000043433A5C576F726B5C6D722E73775C73772E6D63755C6D63752E6678325C6678322E7472695C70726A5C7472692E70726F746F5C7372635C70726F746F5F626F6F742E63000000000C70726F746F5F626F6F742E6300000000C5D4F200FFFFFFFF43433A5C576F726B5C6D722E73775C73772E6D63755C6D63752E6678325C6678322E7472695C70726A5C7472692E70726F746F5C7372635C70726F746F5F636F6E662E63000000000C70726F746F5F636F6E662E6300000000FFDC7800FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD500010000000000000002000000C6020000520100005C0700009A030000 + + + + + diff --git a/prj/tri.jtag/tri_jtag.uvopt b/prj/tri.jtag/tri_jtag.uvopt new file mode 100644 index 0000000..9cedb18 --- /dev/null +++ b/prj/tri.jtag/tri_jtag.uvopt @@ -0,0 +1,722 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + release + 0x0 + MCS-51 + + 48000000 + + 1 + 1 + 1 + 0 + 0 + + + 0 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\lst\release\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 0 + + 255 + + + 0 + Data Sheet + DATASHTS\CYPRESS\CY7C68XXX_DS.PDF + + + 1 + Technical Reference Manual + DATASHTS\CYPRESS\FX2_TRM.PDF + + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + -1 + + + + + + + + + + + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + debug + 0x0 + MCS-51 + + 48000000 + + 1 + 1 + 1 + 0 + 0 + + + 0 + 65535 + 0 + 0 + 0 + + + 120 + 65 + 8 + .\lst\debug\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Data Sheet + DATASHTS\CYPRESS\CY7C68XXX_DS.PDF + + + 1 + Technical Reference Manual + DATASHTS\CYPRESS\FX2_TRM.PDF + + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + -1 + + + + + + + + + + + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + fx2lp - startup + 0 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_startup.s51 + fx2_startup.s51 + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_conf.s51 + fx2_conf.s51 + 0 + 0 + + + + + fx2lp - init + 0 + 0 + 0 + 0 + + 2 + 3 + 2 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_delay1ms.s51 + fx2_delay1ms.s51 + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_delay.c + fx2_delay.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_globals.c + fx2_globals.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_init.c + fx2_init.c + 0 + 0 + + + + + fx2lp - iic + 0 + 0 + 0 + 0 + + 3 + 7 + 1 + 1 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_i2c.c + fx2_i2c.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_eeprom.c + fx2_eeprom.c + 0 + 0 + + + + + fx2lp - timer + 0 + 0 + 0 + 0 + + 4 + 9 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_tmr.c + fx2_tmr.c + 0 + 0 + + + + + fx2lp - serial + 0 + 0 + 0 + 0 + + + + fx2lp - usb + 0 + 0 + 0 + 0 + + 6 + 10 + 2 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_jmptbl.s51 + fx2_jmptbl.s51 + 0 + 0 + + + 6 + 11 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_disconnect.c + fx2_disconnect.c + 0 + 0 + + + 6 + 12 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_usb_isr.c + fx2_usb_isr.c + 0 + 0 + + + 6 + 13 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_usb_sleep.c + fx2_usb_sleep.c + 0 + 0 + + + 6 + 14 + 1 + 0 + 0 + 0 + ..\..\lib\fx2lp\src\fx2_usb_sudav.c + fx2_usb_sudav.c + 0 + 0 + + + + + fx2mr - jtag + 1 + 0 + 0 + 0 + + 7 + 15 + 2 + 0 + 0 + 0 + ..\..\lib\fx2mr\src\jtag\jtag.s51 + jtag.s51 + 0 + 0 + + + + + fx2mr - lcd + 0 + 0 + 0 + 0 + + 8 + 16 + 1 + 0 + 0 + 0 + ..\..\lib\fx2mr\src\lcd\7565r\lcd_7565r.c + lcd_7565r.c + 0 + 0 + + + + + tri - base + 0 + 0 + 0 + 0 + + 9 + 17 + 2 + 0 + 0 + 0 + ..\tri.base\src\tri_dscr.s51 + tri_dscr.s51 + 0 + 0 + + + 9 + 18 + 1 + 0 + 0 + 0 + ..\tri.base\src\tri_main.c + tri_main.c + 0 + 0 + + + 9 + 19 + 1 + 0 + 0 + 0 + ..\tri.base\src\tri_conf.c + tri_conf.c + 0 + 0 + + + 9 + 20 + 1 + 0 + 0 + 0 + ..\tri.base\src\tri_glb.c + tri_glb.c + 0 + 0 + + + 9 + 21 + 1 + 0 + 0 + 0 + ..\tri.base\src\tri_cmd.c + tri_cmd.c + 0 + 0 + + + 9 + 22 + 1 + 0 + 0 + 0 + ..\tri.base\src\tri_usb_ep1.c + tri_usb_ep1.c + 0 + 0 + + + + + tri - jtag + 0 + 0 + 0 + 0 + + 10 + 23 + 1 + 0 + 0 + 0 + .\src\jtag_boot.c + jtag_boot.c + 0 + 0 + + + 10 + 24 + 1 + 0 + 0 + 0 + .\src\jtag_conf.c + jtag_conf.c + 0 + 0 + + + 10 + 25 + 1 + 0 + 0 + 0 + .\src\jtag_cmd.c + jtag_cmd.c + 0 + 0 + + + 10 + 26 + 1 + 0 + 0 + 0 + .\src\jtag_ep2.c + jtag_ep2.c + 0 + 0 + + + + diff --git a/prj/tri.jtag/tri_jtag.uvproj b/prj/tri.jtag/tri_jtag.uvproj new file mode 100644 index 0000000..7156aa6 --- /dev/null +++ b/prj/tri.jtag/tri_jtag.uvproj @@ -0,0 +1,1224 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + release + 0x0 + MCS-51 + 0 + + + EZ-USB FX2LP (CY7C68XXX-X) + Cypress + IRAM(0-0xFF) IROM(0-0x3FFF) XRAM(0xE000-0xE1FF) CLOCK(48000000) MODDP2 + + "LIB\STARTUP.A51" ("Standard 8051 Startup Code") + + 3787 + FX2REGS.H + + + + + + + + + + + 0 + 1 + C:\Tools\mcu\Keil\C51\BIN\ + C:\Tools\mcu\Keil\C51\INC;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\lib\fx2lp\inc;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\lib\fx2mr\inc;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\prj\tri.base\inc + + + Cypress\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\release\ + tri_jtag + 1 + 0 + 1 + 1 + 1 + .\lst\release\ + 0 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd /c md bin\release + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd /c move obj\release\*.hex bin\release\ + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + 65535 + + + S8051.DLL + + DP51.DLL + -pFX2 + S8051.DLL + + TP51.DLL + -pFX2 + + + + 0 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + -1 + + + + + + + + + + + + + + + + + + + 0 + 0 + 0 + 0 + 0 + -1 + + 0 + + + + + + + 0 + + + + 2 + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0xffff + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x4000 + + + 0 + 0x0 + 0x100 + + + 0 + 0xe000 + 0x200 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 1 + 0 + 1 + 3 + 8 + 2 + 1 + 1 + 0 + 0 + + + + + + + + + 0 + 1 + 0 + 0 + + + BOARD_JTAG + + + + + + 0 + 0 + 1 + 0 + 2 + 1 + + + 15,16 + + + + + + + + 0X0000-0X3FFF + 0XE000-0XE1FF + + + + + + + + + + + + + + + + + fx2lp - startup + + + fx2_startup.s51 + 2 + ..\..\lib\fx2lp\src\fx2_startup.s51 + + + fx2_conf.s51 + 2 + ..\..\lib\fx2lp\src\fx2_conf.s51 + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + fx2lp - init + + + fx2_delay1ms.s51 + 2 + ..\..\lib\fx2lp\src\fx2_delay1ms.s51 + + + fx2_delay.c + 1 + ..\..\lib\fx2lp\src\fx2_delay.c + + + fx2_globals.c + 1 + ..\..\lib\fx2lp\src\fx2_globals.c + + + fx2_init.c + 1 + ..\..\lib\fx2lp\src\fx2_init.c + + + + + fx2lp - iic + + + fx2_i2c.c + 1 + ..\..\lib\fx2lp\src\fx2_i2c.c + + + fx2_eeprom.c + 1 + ..\..\lib\fx2lp\src\fx2_eeprom.c + + + + + fx2lp - timer + + + fx2_tmr.c + 1 + ..\..\lib\fx2lp\src\fx2_tmr.c + + + + + fx2lp - serial + + + fx2lp - usb + + + fx2_jmptbl.s51 + 2 + ..\..\lib\fx2lp\src\fx2_jmptbl.s51 + + + fx2_disconnect.c + 1 + ..\..\lib\fx2lp\src\fx2_disconnect.c + + + fx2_usb_isr.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_isr.c + + + fx2_usb_sleep.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_sleep.c + + + fx2_usb_sudav.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_sudav.c + + + + + fx2mr - jtag + + + jtag.s51 + 2 + ..\..\lib\fx2mr\src\jtag\jtag.s51 + + + + + fx2mr - lcd + + + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 0 + 65535 + + + + 2 + 2 + 2 + 2 + 2 + 8 + 10 + 3 + 2 + 2 + 2 + 0 + + + + + + + + + 2 + 2 + 2 + 2 + + + + + + + + + + + + lcd_7565r.c + 1 + ..\..\lib\fx2mr\src\lcd\7565r\lcd_7565r.c + + + + + tri - base + + + tri_dscr.s51 + 2 + ..\tri.base\src\tri_dscr.s51 + + + tri_main.c + 1 + ..\tri.base\src\tri_main.c + + + tri_conf.c + 1 + ..\tri.base\src\tri_conf.c + + + tri_glb.c + 1 + ..\tri.base\src\tri_glb.c + + + tri_cmd.c + 1 + ..\tri.base\src\tri_cmd.c + + + tri_usb_ep1.c + 1 + ..\tri.base\src\tri_usb_ep1.c + + + + + tri - jtag + + + jtag_boot.c + 1 + .\src\jtag_boot.c + + + jtag_conf.c + 1 + .\src\jtag_conf.c + + + jtag_cmd.c + 1 + .\src\jtag_cmd.c + + + jtag_ep2.c + 1 + .\src\jtag_ep2.c + + + + + + + debug + 0x0 + MCS-51 + 0 + + + EZ-USB FX2LP (CY7C68XXX-X) + Cypress + IRAM(0-0xFF) IROM(0-0x3FFF) XRAM(0xE000-0xE1FF) CLOCK(48000000) MODDP2 + + "LIB\STARTUP.A51" ("Standard 8051 Startup Code") + + 3787 + FX2REGS.H + + + + + + + + + + + 0 + 1 + C:\Tools\mcu\Keil\C51\BIN\ + C:\Tools\mcu\Keil\C51\INC;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\lib\fx2lp\inc;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\lib\fx2mr\inc;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\prj\tri.base\inc + + + Cypress\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\debug\ + tri_jtag + 1 + 0 + 1 + 1 + 1 + .\lst\debug\ + 0 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd /c md bin\debug + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd /c move obj\debug\*.hex bin\debug\ + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + 65535 + + + S8051.DLL + + DP51.DLL + -pFX2 + S8051.DLL + + TP51.DLL + -pFX2 + + + + 0 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + -1 + + + + + + + + + + + + + + + + + + + 0 + 0 + 0 + 0 + 0 + -1 + + 0 + + + + + + + 0 + + + + 2 + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0xffff + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x4000 + + + 0 + 0x0 + 0x100 + + + 0 + 0xe000 + 0x200 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 1 + 0 + 1 + 3 + 8 + 2 + 1 + 1 + 0 + 0 + + + LCD_7565,DEBUG + + + + + + 0 + 1 + 0 + 0 + + + DEBUG,BOARD_JTAG + + + + + + 0 + 0 + 1 + 0 + 2 + 1 + + + 15,16 + + + + + + + + + + + + + + + + + + + + + + + + + + fx2lp - startup + + + fx2_startup.s51 + 2 + ..\..\lib\fx2lp\src\fx2_startup.s51 + + + fx2_conf.s51 + 2 + ..\..\lib\fx2lp\src\fx2_conf.s51 + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + fx2lp - init + + + fx2_delay1ms.s51 + 2 + ..\..\lib\fx2lp\src\fx2_delay1ms.s51 + + + fx2_delay.c + 1 + ..\..\lib\fx2lp\src\fx2_delay.c + + + fx2_globals.c + 1 + ..\..\lib\fx2lp\src\fx2_globals.c + + + fx2_init.c + 1 + ..\..\lib\fx2lp\src\fx2_init.c + + + + + fx2lp - iic + + + fx2_i2c.c + 1 + ..\..\lib\fx2lp\src\fx2_i2c.c + + + fx2_eeprom.c + 1 + ..\..\lib\fx2lp\src\fx2_eeprom.c + + + + + fx2lp - timer + + + fx2_tmr.c + 1 + ..\..\lib\fx2lp\src\fx2_tmr.c + + + + + fx2lp - serial + + + fx2lp - usb + + + fx2_jmptbl.s51 + 2 + ..\..\lib\fx2lp\src\fx2_jmptbl.s51 + + + fx2_disconnect.c + 1 + ..\..\lib\fx2lp\src\fx2_disconnect.c + + + fx2_usb_isr.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_isr.c + + + fx2_usb_sleep.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_sleep.c + + + fx2_usb_sudav.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_sudav.c + + + + + fx2mr - jtag + + + jtag.s51 + 2 + ..\..\lib\fx2mr\src\jtag\jtag.s51 + + + + + fx2mr - lcd + + + lcd_7565r.c + 1 + ..\..\lib\fx2mr\src\lcd\7565r\lcd_7565r.c + + + + + tri - base + + + tri_dscr.s51 + 2 + ..\tri.base\src\tri_dscr.s51 + + + tri_main.c + 1 + ..\tri.base\src\tri_main.c + + + tri_conf.c + 1 + ..\tri.base\src\tri_conf.c + + + tri_glb.c + 1 + ..\tri.base\src\tri_glb.c + + + tri_cmd.c + 1 + ..\tri.base\src\tri_cmd.c + + + tri_usb_ep1.c + 1 + ..\tri.base\src\tri_usb_ep1.c + + + + + tri - jtag + + + jtag_boot.c + 1 + .\src\jtag_boot.c + + + jtag_conf.c + 1 + .\src\jtag_conf.c + + + jtag_cmd.c + 1 + .\src\jtag_cmd.c + + + jtag_ep2.c + 1 + .\src\jtag_ep2.c + + + + + + + + diff --git a/prj/tri.proto/src/proto_boot.c b/prj/tri.proto/src/proto_boot.c new file mode 100644 index 0000000..06e26a6 --- /dev/null +++ b/prj/tri.proto/src/proto_boot.c @@ -0,0 +1,16 @@ +#include + +extern bool (*DR_VendorCommand)(void); +extern void (*main_hook)(void); + +extern void proto_conf(void); +extern void proto_main(void); +extern bool proto_command(void); + +void tri_boot(void) +{ + proto_conf(); + + main_hook = proto_main; + DR_VendorCommand = proto_command; +} diff --git a/prj/tri.proto/src/proto_cmd.c b/prj/tri.proto/src/proto_cmd.c new file mode 100644 index 0000000..b3613e4 --- /dev/null +++ b/prj/tri.proto/src/proto_cmd.c @@ -0,0 +1,55 @@ +#include +#include +#include + +extern bool jtag_command(void); + +// ================================================================================================ +// Command +// ================================================================================================ +bool proto_command(void) +{ + bool result = true; + + bit dir = (SETUPDAT[0] & 0x80) ? 1 : 0; + BYTE cmd = SETUPDAT[1]; // (SETUPDAT[1] & 0x7F); + PSUDAV sud = (PSUDAV)SETUPDAT; + + + lcd_gotoxy(0,7); + lcd_putx2(cmd); + + // ---------------------------------------------------- + // IN command device -> host + // ---------------------------------------------------- + if(dir) + { + switch(sud->Request) + { + // -------------------------------------------- + // default + // -------------------------------------------- + default: + result = jtag_command(); + break; + } + } + + // ---------------------------------------------------- + // OUT command host -> device + // ---------------------------------------------------- + else + { + switch(sud->Request) + { + // -------------------------------------------- + // default + // -------------------------------------------- + default: + result = jtag_command(); + break; + } + } + + return result; +} diff --git a/prj/tri.proto/src/proto_conf.c b/prj/tri.proto/src/proto_conf.c new file mode 100644 index 0000000..80b09d2 --- /dev/null +++ b/prj/tri.proto/src/proto_conf.c @@ -0,0 +1,147 @@ +#include +#include +#include + +#include + +#include + +extern void FX2_Delay( WORD); +extern void fx2_tmr_init(void); + +extern xdata BYTE devSerialNumber []; +extern xdata BYTE devCapabilities []; +extern xdata BYTE devIdentifier []; + +extern void jtag_main(void); +extern void jtag_conf(void); + +extern void tri_conf(); + +xdata char b[100]; + +// ================================================================================================ +// main +// ================================================================================================ +void proto_main(void) +{ + int i; + + // ------------------------------------------------------------------------ + // call "inherited" main() + // ------------------------------------------------------------------------ + jtag_main(); + + // ------------------------------------------------------------------------ + // "proto" specific main() + // ------------------------------------------------------------------------ + lcd_gotoxy(0,0); + lcd_puts("PROTO",5); + +/* + ADAU1701 + + PD7 = 1; + FX2_Delay(100); + PD7 = 0; + FX2_Delay(100); + PD7 = 1; + FX2_Delay(100); + + b[0] = 0x00; + b[1] = 0x00; + b[2] = 0x00; + b[3] = 0x22; + b[4] = 0x33; + b[5] = 0x44; + +// for(i=0; i<0x28; i++) +// b[i+2] = 0; + +// fx2_i2c_read( 0x34, 1, b); + fx2_i2c_write( 0x34, 6, b); + fx2_i2c_read_rs( 0x34, 0x00, 4, b); +*/ +} + +// ================================================================================================ +// configure +// ================================================================================================ +void proto_conf() +{ + // ------------------------------------------------------------------------ + // call "inherited" config() + // ------------------------------------------------------------------------ + jtag_conf(); +// tri_conf(); + + // ------------------------------------------------------------------------ + // temp serial number + // ------------------------------------------------------------------------ + devSerialNumber[0] = 'P'; + devSerialNumber[1] = '5'; + + // ------------------------------------------------------------------------ + // Board specific initialization + // + // TRINITY_1: + // + // - 2 layers board + // - 56 pin mcu + // - 16 kB flash EEPROM + // + // J1 J2 + // -------------------------- -------------------------- + // GND - 1 2 - 5.0V SLWR - 1 2 - SLRD + // GND - 3 4 - 5.0V CLKOUT - 3 4 - GND + // PB.2 - 5 6 - PB.3 PD.5 - 5 6 - GND + // PB.1 - 7 8 - PB.0 PD.6 - 7 8 - PD.7 + // SCL - 9 10 - SDA 3.3V - 9 10 - 3.3V + // PB.6 - 11 12 - PB.7 3.3V - 11 12 - 3.3V + // PB.5 - 13 14 - PB.4 PD.4 - 13 14 - GND + // FLAG.B - 15 16 - FLAG.A PD.3 - 15 16 - PD.2 + // PA.2 - 17 18 - FLAG.C PD.1 - 17 18 - PD.0 + // PA.1 - 19 20 - PA.0 GND - 19 20 - GND + // PA.7 - 21 22 - PA.3 GND - 21 22 - GND + // PA.4 - 23 24 - GND GND - 23 24 - GND + // PA.5 - 25 26 - PA.5 RESET - 25 26 - WU + // + // + // JTAG TOP + // ---------------- + // T T G G P + // D C N N W + // I K D D R + // + // 9 7 5 3 1 + // 10 8 6 4 2 + // + // T T G G T + // R M N N D + // S S D D O + // T + // + // In case if JTAG is used, the following pins are used for JTAG interface: + // + // TCK - PA.0 out + // TMS - PA.1 out + // TDI - PA.7 out + // TDO - PA.3 in + // ena - PA.4 out + // + // + // In case the DOG LCD is used, the following pins are used for LCD interface. + // + // RST - PD.6 out + // CS - PD.5 out + // A0 - PD.4 out + // SCL - PD.3 out + // SI - PD.1 out + // + // ------------------------------------------------------------------------ + + // ------------------------------------------------------------------------ + // INITIALIZE LCD + // ------------------------------------------------------------------------ + lcd_init(); +} diff --git a/prj/tri.proto/src/uvna/uvna.c b/prj/tri.proto/src/uvna/uvna.c new file mode 100644 index 0000000..b4c3887 --- /dev/null +++ b/prj/tri.proto/src/uvna/uvna.c @@ -0,0 +1,39 @@ +#include "uvna.h" + +// ============================================================================ +// uvna_spi() +// ============================================================================ +static void uvna_spi(BYTE d) +{ + PIN_SS = 1; + + // -------------------------------------------------------------- + // Shift out bit 7 and bit 6. These values are not used anyway... + // -------------------------------------------------------------- + PIN_SDI = (d & 0x80) ? 1 : 0; PIN_SCK = 1; PIN_SCK = 0; + PIN_SDI = (d & 0x40) ? 1 : 0; PIN_SCK = 1; PIN_SCK = 0; + + // -------------------------------------------------------------- + // Shift out A1 and A0 address bits. + // -------------------------------------------------------------- + PIN_SDI = (d & 0x20) ? 1 : 0; PIN_SCK = 1; PIN_SCK = 0; + PIN_SDI = (d & 0x10) ? 1 : 0; PIN_SCK = 1; PIN_SCK = 0; + + // -------------------------------------------------------------- + // Shift out D3..D0 data bits. + // -------------------------------------------------------------- + PIN_SDI = (d & 0x08) ? 1 : 0; PIN_SCK = 1; PIN_SCK = 0; + PIN_SDI = (d & 0x04) ? 1 : 0; PIN_SCK = 1; PIN_SCK = 0; + PIN_SDI = (d & 0x02) ? 1 : 0; PIN_SCK = 1; PIN_SCK = 0; + PIN_SDI = (d & 0x01) ? 1 : 0; PIN_SCK = 1; PIN_SCK = 0; + + PIN_SS = 0; +} + +// ============================================================================ +// xclock +// ============================================================================ +void uvna_xclock(BYTE clk) +{ + uvna_spi(clk & 0x0F); +} diff --git a/prj/tri.proto/src/uvna/uvna.h b/prj/tri.proto/src/uvna/uvna.h new file mode 100644 index 0000000..8c9e145 --- /dev/null +++ b/prj/tri.proto/src/uvna/uvna.h @@ -0,0 +1,13 @@ +#ifndef __UVNA_H__ +#define __UVNA_H__ + +#include +#include + +#define PIN_SS PB0 +#define PIN_SCK PB1 +#define PIN_SDI PB2 + +extern void uvna_xclock( BYTE clock); + +#endif diff --git a/prj/tri.proto/src/uvna/uvna_boot.c b/prj/tri.proto/src/uvna/uvna_boot.c new file mode 100644 index 0000000..09eb613 --- /dev/null +++ b/prj/tri.proto/src/uvna/uvna_boot.c @@ -0,0 +1,16 @@ +#include + +extern bool (*DR_VendorCommand)(void); +extern void (*main_hook)(void); + +extern void uvna_conf(void); +extern void uvna_main(void); +extern bool uvna_command(void); + +void TRI_Boot(void) +{ + uvna_conf(); + + main_hook = uvna_main; + DR_VendorCommand = uvna_command; +} diff --git a/prj/tri.proto/src/uvna/uvna_cmd.c b/prj/tri.proto/src/uvna/uvna_cmd.c new file mode 100644 index 0000000..4268686 --- /dev/null +++ b/prj/tri.proto/src/uvna/uvna_cmd.c @@ -0,0 +1,54 @@ +#include +#include +#include + +extern bool proto_command(void); + +// ================================================================================================ +// Command +// ================================================================================================ +bool uvna_command(void) +{ + bool result = true; + + bit dir = (SETUPDAT[0] & 0x80) ? 1 : 0; + BYTE cmd = SETUPDAT[1]; // (SETUPDAT[1] & 0x7F); + PSUDAV sud = (PSUDAV)SETUPDAT; + + lcd_gotoxy(0,7); + lcd_putx2(cmd); + + // ---------------------------------------------------- + // IN command device -> host + // ---------------------------------------------------- + if(dir) + { + switch(sud->Request) + { + // -------------------------------------------- + // default + // -------------------------------------------- + default: + result = proto_command(); + break; + } + } + + // ---------------------------------------------------- + // OUT command host -> device + // ---------------------------------------------------- + else + { + switch(sud->Request) + { + // -------------------------------------------- + // default + // -------------------------------------------- + default: + result = proto_command(); + break; + } + } + + return result; +} diff --git a/prj/tri.proto/src/uvna/uvna_conf.c b/prj/tri.proto/src/uvna/uvna_conf.c new file mode 100644 index 0000000..78e6222 --- /dev/null +++ b/prj/tri.proto/src/uvna/uvna_conf.c @@ -0,0 +1,443 @@ +#include +#include +#include + +#include +#include "uvna.h" + +extern xdata BYTE devSerialNumber []; +extern xdata BYTE devCapabilities []; +extern xdata BYTE devIdentifier []; + +extern bool fx2_i2c_read( BYTE addr, BYTE length, BYTE xdata *dat); +extern bool fx2_i2c_write( BYTE addr, BYTE length, BYTE xdata *dat); + +xdata BYTE volatile vna_buffer[4]; + +extern void proto_main(void); +extern void proto_conf(void); + +void dump(void); + +// ================================================================================================ +// main +// ================================================================================================ +void uvna_main(void) +{ + // ------------------------------------------------------------------------ + // call "inherited" main() + // ------------------------------------------------------------------------ + proto_main(); + + // ------------------------------------------------------------------------ + // "uVNA" specific main() + // ------------------------------------------------------------------------ + lcd_gotoxy(0,0); + lcd_puts("uVNA",4); +} + +// ================================================================================================ +// configure +// ================================================================================================ +void uvna_conf() +{ + char rc; + + // ------------------------------------------------------------------------ + // call "inherited" config() + // ------------------------------------------------------------------------ + proto_conf(); + + // ------------------------------------------------------------------------ + // temp serial number + // ------------------------------------------------------------------------ + devSerialNumber[0] = 'U'; + devSerialNumber[1] = '5'; + + // ------------------------------------------------------------------------ + // Board specific initialization + // + // TRINITY_1: + // + // - 2 layers board + // - 56 pin mcu + // - 16 kB flash EEPROM + // + // J1 J2 + // -------------------------- -------------------------- + // GND - 1 2 - 5.0V SLWR - 1 2 - SLRD + // GND - 3 4 - 5.0V CLKOUT - 3 4 - GND + // PB.2 - 5 6 - PB.3 PD.5 - 5 6 - GND + // PB.1 - 7 8 - PB.0 PD.6 - 7 8 - PD.7 + // SCL - 9 10 - SDA 3.3V - 9 10 - 3.3V + // PB.6 - 11 12 - PB.7 3.3V - 11 12 - 3.3V + // PB.5 - 13 14 - PB.4 PD.4 - 13 14 - GND + // FLAG.B - 15 16 - FLAG.A PD.3 - 15 16 - PD.2 + // PA.2 - 17 18 - FLAG.C PD.1 - 17 18 - PD.0 + // PA.1 - 19 20 - PA.0 GND - 19 20 - GND + // PA.7 - 21 22 - PA.3 GND - 21 22 - GND + // PA.4 - 23 24 - GND GND - 23 24 - GND + // PA.5 - 25 26 - PA.5 RESET - 25 26 - WU + // + // + // JTAG TOP + // ---------------- + // T T G G P + // D C N N W + // I K D D R + // + // 9 7 5 3 1 + // 10 8 6 4 2 + // + // T T G G T + // R M N N D + // S S D D O + // T + // + // If JTAG is used, the following pins are used for JTAG interface: + // (implemented in JTAG) + // + // TCK - PA.0 out + // TMS - PA.1 out + // TDI - PA.7 out + // TDO - PA.3 in + // ena - PA.4 out + // + // + // If DOG LCD is used, the following pins are used for LCD interface. + // (implemented in PROTO) + // + // RST - PD.6 out + // CS - PD.5 out + // A0 - PD.4 out + // SCL - PD.3 out + // SI - PD.1 out + // + // uVNA specific: + // + // - I2C for programming the AD5933 (at address of 0x0D) + // - SPI for programming Xilinx CPLD clock divider + // + // SDI - PB.2 + // SCK - PB.1 + // SS - PB.0 + // ------------------------------------------------------------------------ + IOB &= 0xF8; // clear SPI bits + OEB |= 0x07; // enable SPI bits (out) + + rc = fx2_i2c_read( 0x08, 4, vna_buffer); + + switch(rc) + { + case I2C_BERROR: + lcd_gotoxy(0,6); + lcd_putc('B'); + + break; + + case I2C_NACK: + lcd_gotoxy(0,6); + lcd_putc('N'); + + break; + } + + //fx2_i2c_read( 0x10, 2, vna_buffer); + return; + + // ------------------------------------------------------------------- + // initialize uVNA + // ------------------------------------------------------------------- + uvna_xclock(12); + + lcd_gotoxy(0,6); + + + // + return; + + + + // start freq + + vna_buffer[0] = 0x82; + vna_buffer[1] = 0x0F; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + vna_buffer[0] = 0x83; + vna_buffer[1] = 0x5C; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + vna_buffer[0] = 0x84; + vna_buffer[1] = 0x28; + + // freq increments + + vna_buffer[0] = 0x85; + vna_buffer[1] = 0x00; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + vna_buffer[0] = 0x86; + vna_buffer[1] = 0x20; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + vna_buffer[0] = 0x87; + vna_buffer[1] = 0x4F; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + // number steps + vna_buffer[0] = 0x88; + vna_buffer[1] = 0x00; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + vna_buffer[0] = 0x89; + vna_buffer[1] = 99; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + // settling cycles + vna_buffer[0] = 0x8A; + vna_buffer[1] = 0x00; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + vna_buffer[0] = 0x8B; + vna_buffer[1] = 0x0A; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + + + // standby + // ----------------------------------------- + vna_buffer[0] = 0x80; + vna_buffer[1] = 0xB0; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + vna_buffer[0] = 0x81; + vna_buffer[1] = 0x00; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + + // ini with start freq + + vna_buffer[0] = 0x80; + vna_buffer[1] = 0x10; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + +// return; + +// dump(); + + // start sweep + vna_buffer[0] = 0x80; + vna_buffer[1] = 0x20; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + + vna_buffer[0] = 0xB0; + vna_buffer[1] = 0x8F; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + fx2_i2c_read( 0x0D, 1, vna_buffer); + + while(1) + { + while( (vna_buffer[0] & 0x02) == 0) + { + vna_buffer[0] = 0xB0; + vna_buffer[1] = 0x8F; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + fx2_i2c_read( 0x0D, 1, vna_buffer); + +// lcd_gotoxy(19,1); +// lcd_putx2(vna_buffer[0] & 0x0F | 0x80); + } + + if( vna_buffer[0] & 0x04) + break; + + // read values + + // step sweep + + vna_buffer[0] = 0x80; + vna_buffer[1] = 0x30; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + vna_buffer[0] = 0xB0; + vna_buffer[1] = 0x8F; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + fx2_i2c_read( 0x0D, 1, vna_buffer); + +// lcd_gotoxy(19,2); +// lcd_putx2(vna_buffer[0] & 0x0F | 0x40); + } + + + + + dump(); + + + + + return; +/* + vna_buffer[0] = 0xAA; + FX2_Delay(150); i2c_write( 0x0D, 1, vna_buffer); + FX2_Delay(150); i2c_write( 0x0D, 1, vna_buffer); + FX2_Delay(150); i2c_write( 0x0D, 1, vna_buffer); + + vna_buffer[0] = 0xB0; + vna_buffer[1] = 0x80; + + FX2_Delay(50); i2c_write( 0x0D, 2, vna_buffer); + + FX2_Delay(50); i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + FX2_Delay(50); i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + FX2_Delay(50); i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + + return; + + vna_buffer[0] = 0x82; // adr = 0x82 (start frequency high byte) + vna_buffer[1] = 0x01; // val = 0x01 (high byte) + + if (i2c_write( 0x0D, 2, vna_buffer)) + lcd_putc('2'); + else + lcd_putc('x'); + + FX2_Delay(50); + + vna_buffer[0] = 0x83; // adr = 0x82 (start frequency mid byte) + vna_buffer[1] = 0x02; // val = 0x02 + +// i2c_write( 0x0D, 2, vna_buffer); + + if (i2c_write( 0x0D, 2, vna_buffer)) + lcd_putc('3'); + else + lcd_putc('x'); + + // + vna_buffer[0] = 0xB0; // cmd: pointer command + vna_buffer[1] = 0x82; // cmd: pointer command +// i2c_write( 0x0D, 2, vna_buffer); // + + if (i2c_write( 0x0D, 2, vna_buffer)) + lcd_putc('4'); + else + lcd_putc('x'); + + vna_buffer[0] = 0x01; + FX2_Delay(50); i2c_write( 0x0D, 1, vna_buffer); + FX2_Delay(50); i2c_write( 0x0D, 1, vna_buffer); + FX2_Delay(50); i2c_write( 0x0D, 1, vna_buffer); + + FX2_Delay(50); + + vna_buffer[0] = 0xB0; // cmd: pointer command + vna_buffer[1] = 0x82; // cmd: pointer command + if (i2c_write( 0x0D, 2, vna_buffer)) + lcd_putc('5'); + else + lcd_putc('x'); + + FX2_Delay(50); + i2c_read(0x0D, 1, vna_buffer); + + + + lcd_gotoxy(0,7); + lcd_putx2(vna_buffer[0]); + +*/ +} + +// ================================================================================================ +// dump uvna registers +// ================================================================================================ +void dump(void) +{ + // command + lcd_gotoxy(0,1); lcd_puts("0x80: ",6); + + vna_buffer[0] = 0xB0; + vna_buffer[1] = 0x80; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + fx2_i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + fx2_i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + + // status + lcd_gotoxy(13,1); lcd_puts("0x8F: ",6); + + vna_buffer[0] = 0xB0; + vna_buffer[1] = 0x8F; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + fx2_i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + + + // start freq + lcd_gotoxy(0,2); lcd_puts("0x82: ",6); + + vna_buffer[0] = 0xB0; + vna_buffer[1] = 0x82; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + fx2_i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + fx2_i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + fx2_i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + + // increment + lcd_gotoxy(0,3); lcd_puts("0x85: ",6); + + vna_buffer[0] = 0xB0; + vna_buffer[1] = 0x85; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + fx2_i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + fx2_i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + fx2_i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + + // steps + lcd_gotoxy(0,4); lcd_puts("0x88: ",6); + + vna_buffer[0] = 0xB0; + vna_buffer[1] = 0x88; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + fx2_i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + fx2_i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + + // settling + lcd_gotoxy(0,5); lcd_puts("0x8A: ",6); + + vna_buffer[0] = 0xB0; + vna_buffer[1] = 0x8A; + + fx2_i2c_write( 0x0D, 2, vna_buffer); + + fx2_i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); + fx2_i2c_read( 0x0D, 1, vna_buffer); lcd_putx2(vna_buffer[0]); +} diff --git a/prj/tri.proto/tri_proto.uvgui.roka b/prj/tri.proto/tri_proto.uvgui.roka new file mode 100644 index 0000000..81b2f9b --- /dev/null +++ b/prj/tri.proto/tri_proto.uvgui.roka @@ -0,0 +1,119 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
+ + + + + + + + + + 38003 + Registers + 228 229 + + + 346 + Code Coverage + 293 160 + + + 204 + Performance Analyzer + 453 + + + + + + 35141 + Event Statistics + + 200 50 700 + + + 1506 + Symbols + + 106 106 106 + + + 1936 + Watch 1 + + 200 133 133 + + + 1937 + Watch 2 + + 200 133 133 + + + 1935 + Call Stack + Locals + + 200 133 133 + + + 2506 + Trace Data + + 75 135 130 95 70 230 200 150 + + + 466 + Source Browser + 500 + 300 + + + + + + + + 1 + 1 + 0 + 0 + -1 + + + + + + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 228 + 231 + 1892 + 1333 + + + + 0 + + 366 + 01000000040000000100000001000000010000000100000000000000020000000000000001000000010000000000000028000000280000000100000002000000010000000100000043433A5C576F726B5C6D722E73775C73772E6D63755C6D63752E6678325C6678322E7472695C70726A5C7472692E70726F746F5C7372635C70726F746F5F626F6F742E63000000000C70726F746F5F626F6F742E6300000000C5D4F200FFFFFFFF43433A5C576F726B5C6D722E73775C73772E6D63755C6D63752E6678325C6678322E7472695C70726A5C7472692E70726F746F5C7372635C70726F746F5F636F6E662E63000000000C70726F746F5F636F6E662E6300000000FFDC7800FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD500010000000000000002000000C6020000520100005C0700009A030000 + + + + + diff --git a/prj/tri.proto/tri_proto.uvopt b/prj/tri.proto/tri_proto.uvopt new file mode 100644 index 0000000..669813b --- /dev/null +++ b/prj/tri.proto/tri_proto.uvopt @@ -0,0 +1,664 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + proto + 0x0 + MCS-51 + 0 + + + EZ-USB FX2LP (CY7C68XXX-X) + Cypress + IRAM(0-0xFF) IROM(0-0x3FFF) XRAM(0xE000-0xE1FF) CLOCK(48000000) MODDP2 + + "LIB\STARTUP.A51" ("Standard 8051 Startup Code") + + 3787 + FX2REGS.H + + + + + + + + + + + 0 + 1 + C:\Tools\mcu\Keil\C51\BIN\ + C:\Tools\mcu\Keil\C51\INC;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\lib\fx2lp\inc;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\lib\fx2mr\inc;c:\Work\mr.sw\sw.mcu\mcu.fx2\fx2.tri\prj\tri.base\inc + + + Cypress\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\proto\ + tri_proto + 1 + 0 + 1 + 1 + 1 + .\lst\proto\ + 0 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd /c md bin + + 0 + 0 + 0 + 0 + + + 1 + 0 + cmd /c move obj\proto\*.hex bin + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + 65535 + + + S8051.DLL + + DP51.DLL + -pFX2 + S8051.DLL + + TP51.DLL + -pFX2 + + + + 0 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + -1 + + + + + + + + + + + + + + + + + + + 0 + 0 + 0 + 0 + 0 + -1 + + 0 + + + + + + + 0 + + + + 2 + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0xffff + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x4000 + + + 0 + 0x0 + 0x100 + + + 0 + 0xe000 + 0x200 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + 0 + 0 + 1 + 0 + 1 + 3 + 8 + 2 + 1 + 1 + 0 + 0 + + + LCD_7565,DEBUG + + + + + + 0 + 1 + 0 + 0 + + + BOARD_JTAG + + + + + + 0 + 0 + 1 + 0 + 2 + 1 + + + 15,16 + + + + + + + + + + + + + + + + + + + + + + + + + + fx2lp - startup + + + fx2_startup.s51 + 2 + ..\..\lib\fx2lp\src\fx2_startup.s51 + + + fx2_conf.s51 + 2 + ..\..\lib\fx2lp\src\fx2_conf.s51 + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + fx2lp - init + + + fx2_delay1ms.s51 + 2 + ..\..\lib\fx2lp\src\fx2_delay1ms.s51 + + + fx2_delay.c + 1 + ..\..\lib\fx2lp\src\fx2_delay.c + + + fx2_globals.c + 1 + ..\..\lib\fx2lp\src\fx2_globals.c + + + fx2_init.c + 1 + ..\..\lib\fx2lp\src\fx2_init.c + + + + + fx2lp - iic + + + fx2_i2c.c + 1 + ..\..\lib\fx2lp\src\fx2_i2c.c + + + fx2_eeprom.c + 1 + ..\..\lib\fx2lp\src\fx2_eeprom.c + + + + + fx2lp - timer + + + fx2_tmr.s51 + 2 + ..\..\lib\fx2lp\src\fx2_tmr.s51 + + + + + fx2lp - usb + + + fx2_jmptbl.s51 + 2 + ..\..\lib\fx2lp\src\fx2_jmptbl.s51 + + + fx2_disconnect.c + 1 + ..\..\lib\fx2lp\src\fx2_disconnect.c + + + fx2_usb_isr.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_isr.c + + + fx2_usb_sleep.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_sleep.c + + + fx2_usb_sudav.c + 1 + ..\..\lib\fx2lp\src\fx2_usb_sudav.c + + + + + fx2mr - jtag + + + jtag.s51 + 2 + ..\..\lib\fx2mr\src\jtag\jtag.s51 + + + + + fx2mr - lcd + + + lcd_7565r.c + 1 + ..\..\lib\fx2mr\src\lcd\7565r\lcd_7565r.c + + + + + tri - base + + + tri_dscr.s51 + 2 + ..\tri.base\src\tri_dscr.s51 + + + tri_main.c + 1 + ..\tri.base\src\tri_main.c + + + tri_conf.c + 1 + ..\tri.base\src\tri_conf.c + + + tri_glb.c + 1 + ..\tri.base\src\tri_glb.c + + + tri_cmd.c + 1 + ..\tri.base\src\tri_cmd.c + + + tri_usb_ep1.c + 1 + ..\tri.base\src\tri_usb_ep1.c + + + + + tri - jtag + + + jtag_conf.c + 1 + ..\tri.jtag\src\jtag_conf.c + + + jtag_cmd.c + 1 + ..\tri.jtag\src\jtag_cmd.c + + + jtag_ep2.c + 1 + ..\tri.jtag\src\jtag_ep2.c + + + + + tri - proto + + + proto_boot.c + 1 + .\src\proto_boot.c + + + proto_conf.c + 1 + .\src\proto_conf.c + + + proto_cmd.c + 1 + .\src\proto_cmd.c + + + + + tri - proto - uvna + + + uvna_boot.c + 1 + .\src\uvna\uvna_boot.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + 2 + 8 + 10 + 3 + 2 + 2 + 2 + 0 + + + + + + + + + + + + uvna_conf.c + 1 + .\src\uvna\uvna_conf.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + 2 + 8 + 10 + 3 + 2 + 2 + 2 + 0 + + + + + + + + + + + + uvna_cmd.c + 1 + .\src\uvna\uvna_cmd.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + 2 + 8 + 10 + 3 + 2 + 2 + 2 + 0 + + + + + + + + + + + + uvna.c + 1 + .\src\uvna\uvna.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + 65535 + + + + 2 + 2 + 2 + 2 + 2 + 8 + 10 + 3 + 2 + 2 + 2 + 0 + + + + + + + + + + + + + + + + + diff --git a/prj/tri.uvmpw b/prj/tri.uvmpw new file mode 100644 index 0000000..a273d29 --- /dev/null +++ b/prj/tri.uvmpw @@ -0,0 +1,28 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + WorkSpace + + + .\tri.base\tri_base.uvproj + + + + .\tri.jtag\tri_jtag.uvproj + + + + .\tri.proto\tri_proto.uvproj + 1 + 1 + + + + .\tri.cf1\tri_cf1.uvproj + + + diff --git a/prj/tri.uvmpw.uvgui.roka b/prj/tri.uvmpw.uvgui.roka new file mode 100644 index 0000000..177797c --- /dev/null +++ b/prj/tri.uvmpw.uvgui.roka @@ -0,0 +1,1806 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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