// ============================================================================
// FX2LP SFR Registers at 0xB0 - 0xBF
// ----------------------------------------------------------------------------
// 0xB0 - IOD
// 0xB1 - IOE
// 0xB2 - OEA
// 0xB3 - OEB
// 0xB4 - OEC
// 0xB5 - OED
// 0xB6 - OEE
// 0xB7 -
// 0xB8 - IP
// 0xB9 -
// 0xBA - EP01STAT
// 0xBB - GPIFTRIG
// 0xBC -
// 0xBD - GPIFSGL_DATH
// 0xBE - GPIFSGL_DATLX
// 0xBF - GPIFSGL_DATLNOX
// ============================================================================
#ifndef FX2REGS_SFRBX_H
#define FX2REGS_SFRBX_H

sfr IOD             = 0xB0;
sfr IOE             = 0xB1;
sfr OEA             = 0xB2;
sfr OEB             = 0xB3;
sfr OEC             = 0xB4;
sfr OED             = 0xB5;
sfr OEE             = 0xB6;
sfr IP              = 0xB8;

sfr EP01STAT        = 0xBA;
sfr GPIFTRIG        = 0xBB;
sfr GPIFSGLDATH     = 0xBD;
sfr GPIFSGLDATLX    = 0xBE;
sfr GPIFSGLDATLNOX  = 0xBF;


// ------------------------------------
// PortD (0xB0)
// ------------------------------------
sbit PD0            = 0xB0  +0;
sbit PD1            = 0xB0  +1;
sbit PD2            = 0xB0  +2;
sbit PD3            = 0xB0  +3;
sbit PD4            = 0xB0  +4;
sbit PD5            = 0xB0  +5;
sbit PD6            = 0xB0  +6;
sbit PD7            = 0xB0  +7;

// ------------------------------------
// IP bits
// ------------------------------------
sbit PX0            = 0xB8  +0;
sbit PT0            = 0xB8  +1;
sbit PX1            = 0xB8  +2;
sbit PT1            = 0xB8  +3;
sbit PS0            = 0xB8  +4;
sbit PT2            = 0xB8  +5;
sbit PS1            = 0xB8  +6;

#endif