// ============================================================================
// FX2LP SFR Registers at 0x80 - 0x8F
// ----------------------------------------------------------------------------
// 0x80 - IOA
// 0x81 - SP
// 0x82 - DPL0
// 0x83 - DPH0
// 0x84 - DPL1
// 0x85 - DPH1
// 0x86 - DPS
// 0x87 - PCON
// 0x88 - TCON
// 0x89 - TMOD
// 0x8A - TL0
// 0x8B - TL1
// 0x8C - TH0
// 0x8D - TH1
// 0x8E - CKCON
// 0x8F - (SFUNC)   ????
//
// TODO: check documentation!!!
// ============================================================================
#ifndef FX2REGS_SFR8X_H
#define FX2REGS_SFR8X_H

sfr IOA     = 0x80;
sfr SP      = 0x81;
sfr DPL     = 0x82;
sfr DPH     = 0x83;
sfr DPL1    = 0x84;
sfr DPH1    = 0x85;
sfr DPS     = 0x86;
sfr PCON    = 0x87;
sfr TCON    = 0x88;
sfr TMOD    = 0x89;
sfr TL0     = 0x8A;
sfr TL1     = 0x8B;
sfr TH0     = 0x8C;
sfr TH1     = 0x8D;
sfr CKCON   = 0x8E;
sfr SFUNC   = 0x8F;

sfr16   DP0 = 0x82;
sfr16   DP1 = 0x84;

// ------------------------------------
// PortA (0x80)
// ------------------------------------
sbit PA0    = 0x80 + 0;
sbit PA1    = 0x80 + 1;
sbit PA2    = 0x80 + 2;
sbit PA3    = 0x80 + 3;
sbit PA4    = 0x80 + 4;
sbit PA5    = 0x80 + 5;
sbit PA6    = 0x80 + 6;
sbit PA7    = 0x80 + 7;

// ------------------------------------
// TCON (0x88)
// ------------------------------------
sbit IT0    = 0x88  +0;
sbit IE0    = 0x88  +1;
sbit IT1    = 0x88  +2;
sbit IE1    = 0x88  +3;
sbit TR0    = 0x88  +4;
sbit TF0    = 0x88  +5;
sbit TR1    = 0x88  +6;
sbit TF1    = 0x88  +7;

// ------------------------------------
// PCON bits (0x87)
// ------------------------------------
#define bmIDLE      0x01
//#define bmSTOP      0x02    // ??
//#define bmGF0       0x04    // ??
//#define bmGF1       0x08    // ??
#define bmSMOD0     0x80

// ------------------------------------
// TMOD bits (0x89)
// ------------------------------------
#define bmM00       0x01
#define bmM10       0x02
#define bmCT0       0x04
#define bmGATE0     0x08
#define bmM01       0x10
#define bmM11       0x20
#define bmCT1       0x40
#define bmGATE1     0x80

// ------------------------------------
// CKCON bits (0x8E)
// ------------------------------------
#define bmMD0       0x01
#define bmMD1       0x02
#define bmMD2       0x04
#define bmT0M       0x08
#define bmT1M       0x10
#define bmT2M       0x20

// ------------------------------------
// SFUNC bits
// ------------------------------------
//sbit WRS  = 0x8F  +0;

#endif