// ============================================================================
// FX2LP SFR Registers at 0xA0 - 0xAF
// ----------------------------------------------------------------------------
// 0xA0 - IOC
// 0xA1 - INT2CLR
// 0xA2 - INT4CLR
// 0xA3 -
// 0xA4 -
// 0xA5 -
// 0xA6 -
// 0xA7 -
// 0xA8 - IE
// 0xA9 -
// 0xAA - EP2468STAT
// 0xAB - EP24FIFOFLGS
// 0xAC - EP68FIFOFLGS
// 0xAD -
// 0xAE -
// 0xAF - AUTOPTRSETUP
// ============================================================================
#ifndef FX2REGS_SFRAX_H
#define FX2REGS_SFRAX_H

sfr	IOC			= 0xA0;
sfr	INT2CLR		= 0xA1;
sfr	INT4CLR		= 0xA2;
sfr	IE			= 0xA8;
sfr	EP2468STAT	= 0xAA;
sfr	EP24FIFOFLGS= 0xAB;
sfr	EP68FIFOFLGS= 0xAC;
sfr	AUTOPTRSETUP= 0xAF;


// ------------------------------------
// IOC (0xA0)
// ------------------------------------
sbit PC0	= 0xA0	+0;
sbit PC1	= 0xA0	+1;
sbit PC2	= 0xA0	+2;
sbit PC3	= 0xA0	+3;
sbit PC4	= 0xA0	+4;
sbit PC5	= 0xA0	+5;
sbit PC6	= 0xA0	+6;
sbit PC7	= 0xA0	+7;


// ------------------------------------
// IE (0xA8)
// ------------------------------------
sbit EX0	= 0xA8	+0;
sbit ET0	= 0xA8	+1;
sbit EX1	= 0xA8	+2;
sbit ET1	= 0xA8	+3;
sbit ES0	= 0xA8	+4;
sbit ET2	= 0xA8	+5;
sbit ES1	= 0xA8	+6;
sbit EA		= 0xA8	+7;

// ------------------------------------
// EP2468STAT (0xAA)
// ------------------------------------
#define bmEP2E		0x01
#define bmEP2F		0x02
#define bmEP4E		0x04
#define bmEP4F		0x08
#define bmEP6E		0x10
#define bmEP6F		0x20
#define bmEP8E		0x40
#define bmEP8F		0x80

// ------------------------------------
// EP24FIFOFLGS (0XAB)
// ------------------------------------
#define bmEP2FF		0x01
#define bmEP2EF		0x02
#define bmEP2PF		0x04
#define bmEP4FF		0x10
#define bmEP4EF		0x20
#define bmEP4PF		0x40

// ------------------------------------
// EP68FIFOFLGS (0XAC)
// ------------------------------------
#define bmEP6FF		0x01
#define bmEP6EF		0x02
#define bmEP6PF		0x04
#define bmEP8FF		0x10
#define bmEP8EF		0x20
#define bmEP8PF		0x40

// ------------------------------------
// AUTOPTRSETUP (0xAF)
// ------------------------------------
#define bmAPTREN	0x01
#define bmAPTR1INC	0x02
#define bmAPTR2INC	0x04




#endif