107 lines
2.4 KiB
C
107 lines
2.4 KiB
C
// ============================================================================
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// FX2LP SFR Registers at 0x80 - 0x8F
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// ----------------------------------------------------------------------------
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// 0x80 - IOA
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// 0x81 - SP
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// 0x82 - DPL0
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// 0x83 - DPH0
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// 0x84 - DPL1
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// 0x85 - DPH1
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// 0x86 - DPS
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// 0x87 - PCON
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// 0x88 - TCON
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// 0x89 - TMOD
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// 0x8A - TL0
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// 0x8B - TL1
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// 0x8C - TH0
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// 0x8D - TH1
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// 0x8E - CKCON
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// 0x8F - (SFUNC) ????
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//
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// TODO: check documentation!!!
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// ============================================================================
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#ifndef FX2REGS_SFR8X_H
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#define FX2REGS_SFR8X_H
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sfr IOA = 0x80;
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sfr SP = 0x81;
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sfr DPL = 0x82;
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sfr DPH = 0x83;
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sfr DPL1 = 0x84;
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sfr DPH1 = 0x85;
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sfr DPS = 0x86;
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sfr PCON = 0x87;
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sfr TCON = 0x88;
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sfr TMOD = 0x89;
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sfr TL0 = 0x8A;
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sfr TL1 = 0x8B;
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sfr TH0 = 0x8C;
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sfr TH1 = 0x8D;
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sfr CKCON = 0x8E;
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sfr SFUNC = 0x8F;
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sfr16 DP0 = 0x82;
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sfr16 DP1 = 0x84;
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// ------------------------------------
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// PortA (0x80)
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// ------------------------------------
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sbit PA0 = 0x80 + 0;
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sbit PA1 = 0x80 + 1;
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sbit PA2 = 0x80 + 2;
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sbit PA3 = 0x80 + 3;
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sbit PA4 = 0x80 + 4;
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sbit PA5 = 0x80 + 5;
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sbit PA6 = 0x80 + 6;
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sbit PA7 = 0x80 + 7;
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// ------------------------------------
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// TCON (0x88)
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// ------------------------------------
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sbit IT0 = 0x88 +0;
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sbit IE0 = 0x88 +1;
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sbit IT1 = 0x88 +2;
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sbit IE1 = 0x88 +3;
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sbit TR0 = 0x88 +4;
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sbit TF0 = 0x88 +5;
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sbit TR1 = 0x88 +6;
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sbit TF1 = 0x88 +7;
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// ------------------------------------
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// PCON bits (0x87)
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// ------------------------------------
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#define bmIDLE 0x01
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//#define bmSTOP 0x02 // ??
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//#define bmGF0 0x04 // ??
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//#define bmGF1 0x08 // ??
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#define bmSMOD0 0x80
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// ------------------------------------
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// TMOD bits (0x89)
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// ------------------------------------
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#define bmM00 0x01
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#define bmM10 0x02
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#define bmCT0 0x04
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#define bmGATE0 0x08
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#define bmM01 0x10
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#define bmM11 0x20
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#define bmCT1 0x40
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#define bmGATE1 0x80
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// ------------------------------------
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// CKCON bits (0x8E)
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// ------------------------------------
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#define bmMD0 0x01
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#define bmMD1 0x02
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#define bmMD2 0x04
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#define bmT0M 0x08
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#define bmT1M 0x10
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#define bmT2M 0x20
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// ------------------------------------
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// SFUNC bits
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// ------------------------------------
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//sbit WRS = 0x8F +0;
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#endif
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