60 lines
1.2 KiB
C
60 lines
1.2 KiB
C
// ============================================================================
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// FX2LP SFR Registers at 0xC0 - 0xCF
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// ----------------------------------------------------------------------------
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// 0xC0 - SCON1
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// 0xC1 - SBUF1
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// 0xC2 -
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// 0xC3 -
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// 0xC4 -
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// 0xC5 -
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// 0xC6 -
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// 0xC7 -
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// 0xC8 - T2CON
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// 0xC9 -
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// 0xCA - RCAP2L
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// 0xCB - RCAP2H
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// 0xCC - TL2
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// 0xCD - TH2
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// 0xCE -
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// 0xCF -
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// ============================================================================
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#ifndef FX2REGS_SFRCX_H
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#define FX2REGS_SFRCX_H
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sfr SCON1 = 0xC0;
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sfr SBUF1 = 0xC1;
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sfr T2CON = 0xC8;
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sfr RCAP2L = 0xCA;
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sfr RCAP2H = 0xCB;
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sfr TL2 = 0xCC;
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sfr TH2 = 0xCD;
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// ------------------------------------
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// SCON1 (0xC0)
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// ------------------------------------
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sbit RI1 = 0xC0 +0;
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sbit TI1 = 0xC0 +1;
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sbit RB81 = 0xC0 +2;
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sbit TB81 = 0xC0 +3;
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sbit REN1 = 0xC0 +4;
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sbit SM21 = 0xC0 +5;
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sbit SM11 = 0xC0 +6;
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sbit SM01 = 0xC0 +7;
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// ------------------------------------
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// T2CON (0xC8)
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// ------------------------------------
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sbit CP_RL2 = 0xC8 +0;
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sbit C_T2 = 0xC8 +1;
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sbit TR2 = 0xC8 +2;
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sbit EXEN2 = 0xC8 +3;
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sbit TCLK = 0xC8 +4;
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sbit RCLK = 0xC8 +5;
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sbit EXF2 = 0xC8 +6;
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sbit TF2 = 0xC8 +7;
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#endif
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