644 lines
16 KiB
C
644 lines
16 KiB
C
#pragma NOIV // Do not generate interrupt vectors
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//-----------------------------------------------------------------------------
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// File: FX2_to_extsyncFIFO.c
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// Contents: Hooks required to implement FX2 GPIF interface to a TI
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// 5416 DSP via it's HPI (Host Port Interface)
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//
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// Copyright (c) 2002 Cypress Semiconductor, Inc. All rights reserved
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//-----------------------------------------------------------------------------
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#include "fx2.h"
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#include "fx2regs.h"
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#include "fx2sdly.h" // SYNCDELAY macro, see Section 15.14 of FX2 Tech.
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// Ref. Manual for usage details.
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#define HPI_RDY GPIFREADYSTAT & bmBIT0 // RDY0
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#define LED_ALL (bmBIT0 | bmBIT1 | bmBIT2 | bmBIT3)
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#define bmEP0BSY 0x01
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#define bmEP1OUTBSY 0x02
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#define bmEP1INBSY 0x04
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#define bmHPIC 0x00 // HCNTL[1:0] = 00
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#define bmHPID_AUTO 0x04 // HCNTL[1:0] = 01
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#define bmHPIA 0x08 // HCNTL[1:0] = 10
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#define bmHPID_MANUAL 0x0C // HCNTL[1:0] = 11
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#define GPIFTRIGRD 4
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#define GPIF_EP2 0
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#define GPIF_EP4 1
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#define GPIF_EP6 2
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#define GPIF_EP8 3
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extern BOOL GotSUD; // Received setup data flag
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extern BOOL Sleep;
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extern BOOL Rwuen;
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extern BOOL Selfpwr;
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BYTE Configuration; // Current configuration
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BYTE AlternateSetting; // Alternate settings
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static WORD xdata LED_Count = 0;
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static BYTE xdata LED_Status = 0;
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BOOL in_enable = FALSE; // flag to enable IN transfers
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BOOL hpi_int = FALSE; // HPI interrupt flag
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static WORD xdata Tcount = 0; // transaction count
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BOOL enum_high_speed = FALSE; // flag to let firmware know FX2 enumerated at high speed
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static WORD xFIFOBC_IN = 0x0000; // variable that contains EP6FIFOBCH/L value
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//-----------------------------------------------------------------------------
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// Task Dispatcher hooks
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// The following hooks are called by the task dispatcher.
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//-----------------------------------------------------------------------------
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void LED_Off (BYTE LED_Mask);
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void LED_On (BYTE LED_Mask);
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void GpifInit ();
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void GPIF_SingleByteWrite (BYTE gdata)
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{
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while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
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{
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;
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}
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XGPIFSGLDATLX = gdata; // trigger GPIF Single Byte Write transaction
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}
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void TD_Init(void) // Called once at startup
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{
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// set the CPU clock to 48MHz
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CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
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SYNCDELAY;
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EP1OUTCFG = 0xA0; // always OUT, valid, bulk
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EP1INCFG = 0xA0; // always IN, valid, bulk
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SYNCDELAY;
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EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
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SYNCDELAY;
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EP4CFG = 0x00; // EP4 not valid
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SYNCDELAY;
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EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered
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SYNCDELAY;
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EP8CFG = 0x00; // EP8 not valid
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SYNCDELAY;
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FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
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SYNCDELAY;
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FIFORESET = 0x02; // reset EP2 FIFO
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SYNCDELAY;
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FIFORESET = 0x06; // reset EP6 FIFO
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SYNCDELAY;
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FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
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SYNCDELAY;
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EP2FIFOCFG = 0x00; // allow core to see zero to one transition of auto out bit
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SYNCDELAY;
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EP2FIFOCFG = 0x10; // auto out mode, disable PKTEND zero length send, byte ops
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SYNCDELAY;
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EP6FIFOCFG = 0x08; // auto in mode, disable PKTEND zero length send, byte ops
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SYNCDELAY;
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EP1OUTBC = 0x00; // arm EP1OUT by writing any value to EP1OUTBC register
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GpifInit (); // initialize GPIF registers
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PORTACFG = bmBIT0; // PA0 takes on INT0/ alternate function
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OEA |= 0x0C; // initialize PA3 and PA2 port i/o pins as outputs
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EX0 = 1; // Enable INT0/ interrupt
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IT0 = 1; // Detect INT0/ on falling edge
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}
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void TD_Poll(void)
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{
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if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
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{
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if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there's a packet in the peripheral domain for EP2
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{
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IOA = bmHPID_AUTO; // select HPID register with address auto-increment
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while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer
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SYNCDELAY;
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GPIFTCB1 = EP2FIFOBCH; // setup transaction count with number of bytes in the EP2 FIFO
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SYNCDELAY;
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GPIFTCB0 = EP2FIFOBCL;
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SYNCDELAY;
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GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
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SYNCDELAY;
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while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
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{
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;
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}
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SYNCDELAY;
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}
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}
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if(in_enable) // if IN transfers are enabled,
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{
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if(Tcount) // if Tcount is not zero
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{
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if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
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{
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if( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full
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{
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IOA = bmHPID_AUTO; // select HPID register with address auto-increment
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while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer
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SYNCDELAY;
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GPIFTCB1 = MSB(Tcount); // setup transaction count with Tcount value
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SYNCDELAY;
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GPIFTCB0 = LSB(Tcount);
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SYNCDELAY;
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GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6IN
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SYNCDELAY;
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while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
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{
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;
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}
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SYNCDELAY;
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xFIFOBC_IN = ( ( EP6FIFOBCH << 8 ) + EP6FIFOBCL ); // get EP6FIFOBCH/L value
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if( xFIFOBC_IN < 0x0200 ) // if pkt is short,
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{
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INPKTEND = 0x06; // force a commit to the host
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}
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Tcount = 0; // set Tcount to zero to cease reading from DSP HPI RAM
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}
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}
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}
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}
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if(!(EP01STAT & bmEP1OUTBSY))
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{
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// handle OUTs to EP1OUT
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}
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if(!(EP01STAT & bmEP1INBSY))
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{
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// handle INs to EP1IN
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}
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if (hpi_int)
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{
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hpi_int = FALSE; // clear HPI interrupt flag
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EX0 = 1; // enable INT0 interrupt again
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LED_On (bmBIT1); // turn on LED1 to alert user HPI interrupt occurred
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}
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// blink LED0 to indicate firmware is running
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if (++LED_Count == 10000)
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{
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if (LED_Status)
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{
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LED_Off (bmBIT0);
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LED_Status = 0;
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}
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else
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{
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LED_On (bmBIT0);
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LED_Status = 1;
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}
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LED_Count = 0;
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}
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}
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BOOL TD_Suspend(void) // Called before the device goes into suspend mode
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{
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return(TRUE);
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}
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BOOL TD_Resume(void) // Called after the device resumes
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{
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return(TRUE);
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}
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//-----------------------------------------------------------------------------
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// Device Request hooks
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// The following hooks are called by the end point 0 device request parser.
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//-----------------------------------------------------------------------------
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BOOL DR_GetDescriptor(void)
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{
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return(TRUE);
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}
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BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
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{
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if( EZUSB_HIGHSPEED( ) )
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{ // FX2 enumerated at high speed
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SYNCDELAY;
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EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes
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SYNCDELAY;
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EP6AUTOINLENL = 0x00;
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SYNCDELAY;
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enum_high_speed = TRUE;
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}
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else
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{ // FX2 enumerated at full speed
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SYNCDELAY;
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EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes
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SYNCDELAY;
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EP6AUTOINLENL = 0x40;
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SYNCDELAY;
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enum_high_speed = FALSE;
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}
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Configuration = SETUPDAT[2];
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return(TRUE); // Handled by user code
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}
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BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
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{
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EP0BUF[0] = Configuration;
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EP0BCH = 0;
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EP0BCL = 1;
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return(TRUE); // Handled by user code
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}
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BOOL DR_SetInterface(void) // Called when a Set Interface command is received
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{
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AlternateSetting = SETUPDAT[2];
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return(TRUE); // Handled by user code
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}
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BOOL DR_GetInterface(void) // Called when a Set Interface command is received
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{
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EP0BUF[0] = AlternateSetting;
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EP0BCH = 0;
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EP0BCL = 1;
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return(TRUE); // Handled by user code
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}
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BOOL DR_GetStatus(void)
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{
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return(TRUE);
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}
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BOOL DR_ClearFeature(void)
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{
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return(TRUE);
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}
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BOOL DR_SetFeature(void)
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{
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return(TRUE);
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}
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#define VX_B2 0xB2 // turn off LED1
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#define VX_B3 0xB3 // enable IN transfers
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#define VX_B4 0xB4 // disable IN transfers
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#define VX_B5 0xB5 // set Tcount value
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#define VX_B6 0xB6 // write to HPIC register
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#define VX_B7 0xB7 // write to HPIA register
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#define VX_B8 0xB8 // reset EP6 FIFO
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#define VX_B9 0xB9 // read GPIFTRIG register
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#define VX_BA 0xBA // read GPIFTC registers
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BOOL DR_VendorCmnd(void)
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{
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switch (SETUPDAT[1])
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{
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case VX_B2: // turn off LED1
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{
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LED_Off (bmBIT1);
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*EP0BUF = VX_B2;
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EP0BCH = 0;
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EP0BCL = 1; // Arm endpoint with # bytes to transfer
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EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
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break;
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}
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case VX_B3: // enable IN transfers
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{
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in_enable = TRUE;
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*EP0BUF = VX_B3;
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EP0BCH = 0;
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EP0BCL = 1;
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EP0CS |= bmHSNAK;
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break;
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}
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case VX_B4: // disable IN transfers
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{
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in_enable = FALSE;
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*EP0BUF = VX_B4;
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EP0BCH = 0;
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EP0BCL = 1;
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EP0CS |= bmHSNAK;
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break;
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}
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case VX_B5: // set Tcount value
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{
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EP0BCL = 0;
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while(EP01STAT & bmEP0BSY); // wait until EP0 is available to be accessed by CPU
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Tcount = (EP0BUF[0] << 8) + EP0BUF[1]; // load transaction count with EP0 values
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break;
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}
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case VX_B6: // write to HPIC register
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{
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EP0BCL = 0; // re-arm EP0
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while(EP01STAT & bmEP0BSY); // wait until EP0 is available to be accessed by CPU
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while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer
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IOA = bmHPIC; // select HPIC register
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GPIFWFSELECT = 0x1E; // point to waveforms that write first byte of HPI protocol
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GPIF_SingleByteWrite(EP0BUF[0]); // write LSB of DSP address
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GPIFWFSELECT = 0x4E; // point to waveforms that write second byte of HPI protocol
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GPIF_SingleByteWrite(EP0BUF[1]); // write MSB of DSP address
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break;
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}
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case VX_B7: // write to HPIA register
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{
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EP0BCL = 0; // re-arm EP0
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while(EP01STAT & bmEP0BSY); // wait until EP0 is available to be accessed by CPU
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while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer
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IOA = bmHPIA; // select HPIA register
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GPIFWFSELECT = 0x1E; // point to waveforms that write first byte of HPI protocol
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GPIF_SingleByteWrite(EP0BUF[0]); // write LSB of DSP address
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GPIFWFSELECT = 0x4E; // point to waveforms that write second byte of HPI protocol
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GPIF_SingleByteWrite(EP0BUF[1]); // write MSB of DSP address
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break;
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}
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case VX_B8: // reset EP6 FIFO
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{
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FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
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SYNCDELAY;
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FIFORESET = 0x06; // reset EP6 FIFO
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SYNCDELAY;
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FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
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SYNCDELAY;
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*EP0BUF = VX_B8;
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EP0BCH = 0;
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EP0BCL = 1;
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EP0CS |= bmHSNAK;
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break;
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}
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case VX_B9: // read GPIFTRIG register
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{
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EP0BUF[0] = VX_B9;
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EP0BUF[1] = GPIFTRIG;
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EP0BCH = 0;
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EP0BCL = 2;
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EP0CS |= bmHSNAK;
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break;
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}
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case VX_BA: // read GPIFTC registers
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{
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EP0BUF[0] = VX_BA;
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EP0BUF[1] = GPIFTCB1;
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EP0BUF[2] = GPIFTCB0;
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EP0BCH = 0;
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EP0BCL = 3;
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EP0CS |= bmHSNAK;
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break;
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}
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default:
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return(TRUE);
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}
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return(FALSE);
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}
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//-----------------------------------------------------------------------------
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// USB Interrupt Handlers
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// The following functions are called by the USB interrupt jump table.
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//-----------------------------------------------------------------------------
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// Setup Data Available Interrupt Handler
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void ISR_Sudav(void) interrupt 0
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{
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GotSUD = TRUE; // Set flag
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EZUSB_IRQ_CLEAR();
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USBIRQ = bmSUDAV; // Clear SUDAV IRQ
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}
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// Setup Token Interrupt Handler
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void ISR_Sutok(void) interrupt 0
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{
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EZUSB_IRQ_CLEAR();
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USBIRQ = bmSUTOK; // Clear SUTOK IRQ
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}
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void ISR_Sof(void) interrupt 0
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{
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EZUSB_IRQ_CLEAR();
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USBIRQ = bmSOF; // Clear SOF IRQ
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}
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void ISR_Ures(void) interrupt 0
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{
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// whenever we get a USB reset, we should revert to full speed mode
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pConfigDscr = pFullSpeedConfigDscr;
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((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
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pOtherConfigDscr = pHighSpeedConfigDscr;
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((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
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EZUSB_IRQ_CLEAR();
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USBIRQ = bmURES; // Clear URES IRQ
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}
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void ISR_Susp(void) interrupt 0
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{
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Sleep = TRUE;
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EZUSB_IRQ_CLEAR();
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USBIRQ = bmSUSP;
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}
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void ISR_Highspeed(void) interrupt 0
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{
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if (EZUSB_HIGHSPEED())
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{
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pConfigDscr = pHighSpeedConfigDscr;
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((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
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pOtherConfigDscr = pFullSpeedConfigDscr;
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((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
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}
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EZUSB_IRQ_CLEAR();
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USBIRQ = bmHSGRANT;
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}
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void ISR_Ep0ack(void) interrupt 0
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{
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}
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void ISR_Stub(void) interrupt 0
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{
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}
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void ISR_Ep0in(void) interrupt 0
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{
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}
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void ISR_Ep0out(void) interrupt 0
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{
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}
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void ISR_Ep1in(void) interrupt 0
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{
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}
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void ISR_Ep1out(void) interrupt 0
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{
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}
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void ISR_Ep2inout(void) interrupt 0
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{
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}
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void ISR_Ep4inout(void) interrupt 0
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{
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}
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void ISR_Ep6inout(void) interrupt 0
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{
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}
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void ISR_Ep8inout(void) interrupt 0
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{
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}
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void ISR_Ibn(void) interrupt 0
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{
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}
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void ISR_Ep0pingnak(void) interrupt 0
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{
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}
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void ISR_Ep1pingnak(void) interrupt 0
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{
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}
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void ISR_Ep2pingnak(void) interrupt 0
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{
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}
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void ISR_Ep4pingnak(void) interrupt 0
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{
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}
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void ISR_Ep6pingnak(void) interrupt 0
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{
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}
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void ISR_Ep8pingnak(void) interrupt 0
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{
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}
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void ISR_Errorlimit(void) interrupt 0
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{
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}
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void ISR_Ep2piderror(void) interrupt 0
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{
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}
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void ISR_Ep4piderror(void) interrupt 0
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{
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}
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void ISR_Ep6piderror(void) interrupt 0
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{
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}
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void ISR_Ep8piderror(void) interrupt 0
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{
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}
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void ISR_Ep2pflag(void) interrupt 0
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{
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}
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void ISR_Ep4pflag(void) interrupt 0
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{
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}
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void ISR_Ep6pflag(void) interrupt 0
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{
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}
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void ISR_Ep8pflag(void) interrupt 0
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{
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}
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void ISR_Ep2eflag(void) interrupt 0
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{
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}
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void ISR_Ep4eflag(void) interrupt 0
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{
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}
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void ISR_Ep6eflag(void) interrupt 0
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{
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}
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void ISR_Ep8eflag(void) interrupt 0
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{
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}
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void ISR_Ep2fflag(void) interrupt 0
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{
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}
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void ISR_Ep4fflag(void) interrupt 0
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{
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}
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void ISR_Ep6fflag(void) interrupt 0
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{
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}
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void ISR_Ep8fflag(void) interrupt 0
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{
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}
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void ISR_GpifComplete(void) interrupt 0
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{
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}
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void ISR_GpifWaveform(void) interrupt 0
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{
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}
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// ...debug LEDs: accessed via movx reads only ( through CPLD )
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// it may be worth noting here that the default monitor loads at 0xC000
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xdata volatile const BYTE LED0_ON _at_ 0x8000;
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xdata volatile const BYTE LED0_OFF _at_ 0x8100;
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xdata volatile const BYTE LED1_ON _at_ 0x9000;
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xdata volatile const BYTE LED1_OFF _at_ 0x9100;
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xdata volatile const BYTE LED2_ON _at_ 0xA000;
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xdata volatile const BYTE LED2_OFF _at_ 0xA100;
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xdata volatile const BYTE LED3_ON _at_ 0xB000;
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xdata volatile const BYTE LED3_OFF _at_ 0xB100;
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// use this global variable when (de)asserting debug LEDs...
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BYTE xdata ledX_rdvar = 0x00;
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BYTE xdata LED_State = 0;
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void LED_Off (BYTE LED_Mask)
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{
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if (LED_Mask & bmBIT0)
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{
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ledX_rdvar = LED0_OFF;
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LED_State &= ~bmBIT0;
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}
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if (LED_Mask & bmBIT1)
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{
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ledX_rdvar = LED1_OFF;
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LED_State &= ~bmBIT1;
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}
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if (LED_Mask & bmBIT2)
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{
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ledX_rdvar = LED2_OFF;
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LED_State &= ~bmBIT2;
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}
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if (LED_Mask & bmBIT3)
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{
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ledX_rdvar = LED3_OFF;
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LED_State &= ~bmBIT3;
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}
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}
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void LED_On (BYTE LED_Mask)
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{
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if (LED_Mask & bmBIT0)
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{
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ledX_rdvar = LED0_ON;
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LED_State |= bmBIT0;
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}
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if (LED_Mask & bmBIT1)
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{
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ledX_rdvar = LED1_ON;
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LED_State |= bmBIT1;
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}
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if (LED_Mask & bmBIT2)
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{
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ledX_rdvar = LED2_ON;
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LED_State |= bmBIT2;
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}
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if (LED_Mask & bmBIT3)
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{
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ledX_rdvar = LED3_ON;
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LED_State |= bmBIT3;
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}
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}
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