529 lines
13 KiB
C
529 lines
13 KiB
C
#pragma NOIV // Do not generate interrupt vectors
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//-----------------------------------------------------------------------------
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// File: FX2_to_extsyncFIFO.c
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// Contents: Hooks required to implement FX2 GPIF to external sync. FIFO
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// interface using CY4265-15AC
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//
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// Copyright (c) 2003 Cypress Semiconductor, Inc. All rights reserved
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//-----------------------------------------------------------------------------
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#include "fx2.h"
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#include "fx2regs.h"
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#include "fx2sdly.h" // SYNCDELAY macro, see Section 15.14 of FX2 Tech.
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// Ref. Manual for usage details.
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#define EXTFIFONOTFULL GPIFREADYSTAT & bmBIT1
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#define EXTFIFONOTEMPTY GPIFREADYSTAT & bmBIT0
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#define GPIFTRIGRD 4
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#define GPIF_EP2 0
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#define GPIF_EP4 1
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#define GPIF_EP6 2
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#define GPIF_EP8 3
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extern BOOL GotSUD; // Received setup data flag
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extern BOOL Sleep;
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extern BOOL Rwuen;
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extern BOOL Selfpwr;
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BYTE Configuration; // Current configuration
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BYTE AlternateSetting; // Alternate settings
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BOOL in_enable = FALSE; // flag to enable IN transfers
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BOOL enum_high_speed = FALSE; // flag to let firmware know FX2 enumerated at high speed
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extern const char xdata FlowStates[36];
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//-----------------------------------------------------------------------------
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// Task Dispatcher hooks
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// The following hooks are called by the task dispatcher.
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//-----------------------------------------------------------------------------
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void Setup_FLOWSTATE_Write ( void );
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void Setup_FLOWSTATE_Read ( void );
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void GpifInit ();
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void TD_Init(void) // Called once at startup
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{
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// set the CPU clock to 48MHz
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CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
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SYNCDELAY;
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EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
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SYNCDELAY;
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EP4CFG = 0x00; // EP4 not valid
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SYNCDELAY;
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EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered
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SYNCDELAY;
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EP8CFG = 0x00; // EP8 not valid
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SYNCDELAY;
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FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
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SYNCDELAY;
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FIFORESET = 0x02; // reset EP2 FIFO
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SYNCDELAY;
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FIFORESET = 0x06; // reset EP6 FIFO
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SYNCDELAY;
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FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
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SYNCDELAY;
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EP2FIFOCFG = 0x01; // allow core to see zero to one transition of auto out bit
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SYNCDELAY;
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EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word ops
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SYNCDELAY;
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EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops
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SYNCDELAY;
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GpifInit (); // initialize GPIF registers
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SYNCDELAY;
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EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses EF flag
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SYNCDELAY;
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EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses FF flag
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SYNCDELAY;
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// global flowstate register initializations
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FLOWLOGIC = FlowStates[19]; // 0011 0110b - LFUNC[1:0] = 00 (A AND B), TERMA/B[2:0]=110 (FIFO Flag)
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SYNCDELAY;
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FLOWSTB = FlowStates[22]; // 0000 0100b - MSTB[2:0] = 100 (CTL4), not used as strobe
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SYNCDELAY;
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GPIFHOLDAMOUNT = FlowStates[26]; // hold data for one half clock (10ns) assuming 48MHz IFCLK
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SYNCDELAY;
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FLOWSTBEDGE = FlowStates[24]; // move data on both edges of clock
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SYNCDELAY;
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FLOWSTBHPERIOD = FlowStates[25]; // 20.83ns half period
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SYNCDELAY;
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// reset the external FIFO
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OEA |= 0x04; // turn on PA2 as output pin
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IOA |= 0x04; // pull PA2 high initially
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IOA &= 0xFB; // bring PA2 low
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EZUSB_Delay (1); // keep PA2 low for ~1ms, more than enough time
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IOA |= 0x04; // bring PA2 high
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}
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void TD_Poll(void)
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{
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if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
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{
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if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there's a packet in the peripheral domain for EP2
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{
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if ( EXTFIFONOTFULL ) // if the external FIFO is not full
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{
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if(enum_high_speed)
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{
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SYNCDELAY;
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GPIFTCB1 = 0x01; // setup transaction count (512 bytes/2 for word wide -> 0x0100)
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SYNCDELAY;
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GPIFTCB0 = 0x00;
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SYNCDELAY;
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}
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else
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{
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SYNCDELAY;
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GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20)
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SYNCDELAY;
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GPIFTCB0 = 0x20;
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SYNCDELAY;
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}
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Setup_FLOWSTATE_Write(); // setup FLOWSTATE registers for FIFO Write operation
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SYNCDELAY;
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GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
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SYNCDELAY;
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while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
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{
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;
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}
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SYNCDELAY;
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}
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}
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}
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if(in_enable) // if IN transfers are enabled
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{
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if ( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
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{
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if ( EXTFIFONOTEMPTY ) // if external FIFO is not empty
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{
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if ( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full
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{
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if(enum_high_speed)
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{
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SYNCDELAY;
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GPIFTCB1 = 0x01; // setup transaction count (512 bytes/2 for word wide -> 0x0100)
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SYNCDELAY;
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GPIFTCB0 = 0x00;
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SYNCDELAY;
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}
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else
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{
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SYNCDELAY;
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GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20)
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SYNCDELAY;
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GPIFTCB0 = 0x20;
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SYNCDELAY;
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}
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Setup_FLOWSTATE_Read(); // setup FLOWSTATE registers for FIFO Read operation
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SYNCDELAY;
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GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO
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SYNCDELAY;
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while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
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{
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;
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}
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SYNCDELAY;
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}
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}
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}
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}
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}
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BOOL TD_Suspend(void) // Called before the device goes into suspend mode
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{
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return(TRUE);
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}
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BOOL TD_Resume(void) // Called after the device resumes
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{
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return(TRUE);
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}
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//-----------------------------------------------------------------------------
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// Device Request hooks
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// The following hooks are called by the end point 0 device request parser.
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//-----------------------------------------------------------------------------
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BOOL DR_GetDescriptor(void)
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{
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return(TRUE);
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}
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BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
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{
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if( EZUSB_HIGHSPEED( ) )
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{ // FX2 enumerated at high speed
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SYNCDELAY; //
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EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes
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SYNCDELAY; //
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EP6AUTOINLENL = 0x00;
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SYNCDELAY;
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enum_high_speed = TRUE;
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}
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else
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{ // FX2 enumerated at full speed
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SYNCDELAY;
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EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes
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SYNCDELAY;
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EP6AUTOINLENL = 0x40;
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SYNCDELAY;
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enum_high_speed = FALSE;
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}
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Configuration = SETUPDAT[2];
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return(TRUE); // Handled by user code
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}
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BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
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{
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EP0BUF[0] = Configuration;
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EP0BCH = 0;
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EP0BCL = 1;
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return(TRUE); // Handled by user code
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}
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BOOL DR_SetInterface(void) // Called when a Set Interface command is received
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{
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AlternateSetting = SETUPDAT[2];
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return(TRUE); // Handled by user code
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}
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BOOL DR_GetInterface(void) // Called when a Set Interface command is received
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{
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EP0BUF[0] = AlternateSetting;
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EP0BCH = 0;
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EP0BCL = 1;
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return(TRUE); // Handled by user code
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}
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BOOL DR_GetStatus(void)
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{
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return(TRUE);
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}
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BOOL DR_ClearFeature(void)
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{
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return(TRUE);
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}
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BOOL DR_SetFeature(void)
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{
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return(TRUE);
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}
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#define VX_B2 0xB2 // reset the external FIFO
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#define VX_B3 0xB3 // enable IN transfers
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#define VX_B4 0xB4 // disable IN transfers
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#define VX_B5 0xB5 // read GPIFREADYSTAT register
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#define VX_B6 0xB6 // read GPIFTRIG register
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BOOL DR_VendorCmnd(void)
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{
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switch (SETUPDAT[1])
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{
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case VX_B2:
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{
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// reset the external FIFO
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OEA |= 0x04; // turn on PA2 as output pin
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IOA |= 0x04; // pull PA2 high initially
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IOA &= 0xFB; // bring PA2 low
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EZUSB_Delay (1); // keep PA2 low for ~1ms, more than enough time
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IOA |= 0x04; // bring PA2 high
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*EP0BUF = VX_B2;
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EP0BCH = 0;
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EP0BCL = 1; // Arm endpoint with # bytes to transfer
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EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
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break;
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}
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case VX_B3: // enable IN transfers
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{
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in_enable = TRUE;
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*EP0BUF = VX_B3;
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EP0BCH = 0;
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EP0BCL = 1;
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EP0CS |= bmHSNAK;
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break;
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}
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case VX_B4: // disable IN transfers
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{
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in_enable = FALSE;
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*EP0BUF = VX_B4;
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EP0BCH = 0;
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EP0BCL = 1;
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EP0CS |= bmHSNAK;
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break;
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}
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case VX_B5: // read GPIFREADYSTAT register
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{
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EP0BUF[0] = VX_B5;
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SYNCDELAY;
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EP0BUF[1] = GPIFREADYSTAT;
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SYNCDELAY;
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EP0BCH = 0;
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EP0BCL = 2;
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EP0CS |= bmHSNAK;
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break;
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}
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case VX_B6: // read GPIFTRIG register
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{
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EP0BUF[0] = VX_B6;
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SYNCDELAY;
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EP0BUF[1] = GPIFTRIG;
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SYNCDELAY;
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EP0BCH = 0;
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EP0BCL = 2;
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EP0CS |= bmHSNAK;
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break;
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}
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default:
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return(TRUE);
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}
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return(FALSE);
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}
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//-----------------------------------------------------------------------------
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// USB Interrupt Handlers
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// The following functions are called by the USB interrupt jump table.
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//-----------------------------------------------------------------------------
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// Setup Data Available Interrupt Handler
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void ISR_Sudav(void) interrupt 0
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{
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GotSUD = TRUE; // Set flag
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EZUSB_IRQ_CLEAR();
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USBIRQ = bmSUDAV; // Clear SUDAV IRQ
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}
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// Setup Token Interrupt Handler
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void ISR_Sutok(void) interrupt 0
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{
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EZUSB_IRQ_CLEAR();
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USBIRQ = bmSUTOK; // Clear SUTOK IRQ
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}
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void ISR_Sof(void) interrupt 0
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{
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EZUSB_IRQ_CLEAR();
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USBIRQ = bmSOF; // Clear SOF IRQ
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}
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void ISR_Ures(void) interrupt 0
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{
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// whenever we get a USB reset, we should revert to full speed mode
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pConfigDscr = pFullSpeedConfigDscr;
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((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
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pOtherConfigDscr = pHighSpeedConfigDscr;
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((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
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EZUSB_IRQ_CLEAR();
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USBIRQ = bmURES; // Clear URES IRQ
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}
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void ISR_Susp(void) interrupt 0
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{
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Sleep = TRUE;
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EZUSB_IRQ_CLEAR();
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USBIRQ = bmSUSP;
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}
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void ISR_Highspeed(void) interrupt 0
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{
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if (EZUSB_HIGHSPEED())
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{
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pConfigDscr = pHighSpeedConfigDscr;
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((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
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pOtherConfigDscr = pFullSpeedConfigDscr;
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((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
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}
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EZUSB_IRQ_CLEAR();
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USBIRQ = bmHSGRANT;
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}
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void ISR_Ep0ack(void) interrupt 0
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{
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}
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void ISR_Stub(void) interrupt 0
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{
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}
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void ISR_Ep0in(void) interrupt 0
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{
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}
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void ISR_Ep0out(void) interrupt 0
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{
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}
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void ISR_Ep1in(void) interrupt 0
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{
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}
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void ISR_Ep1out(void) interrupt 0
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{
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}
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void ISR_Ep2inout(void) interrupt 0
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{
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}
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void ISR_Ep4inout(void) interrupt 0
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{
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}
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void ISR_Ep6inout(void) interrupt 0
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{
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}
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void ISR_Ep8inout(void) interrupt 0
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{
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}
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void ISR_Ibn(void) interrupt 0
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{
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}
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void ISR_Ep0pingnak(void) interrupt 0
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{
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}
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void ISR_Ep1pingnak(void) interrupt 0
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{
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}
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void ISR_Ep2pingnak(void) interrupt 0
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{
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}
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void ISR_Ep4pingnak(void) interrupt 0
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{
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}
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void ISR_Ep6pingnak(void) interrupt 0
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{
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}
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void ISR_Ep8pingnak(void) interrupt 0
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{
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}
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void ISR_Errorlimit(void) interrupt 0
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{
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}
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void ISR_Ep2piderror(void) interrupt 0
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{
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}
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void ISR_Ep4piderror(void) interrupt 0
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{
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}
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void ISR_Ep6piderror(void) interrupt 0
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{
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}
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void ISR_Ep8piderror(void) interrupt 0
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{
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}
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void ISR_Ep2pflag(void) interrupt 0
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{
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}
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void ISR_Ep4pflag(void) interrupt 0
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{
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}
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void ISR_Ep6pflag(void) interrupt 0
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{
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}
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void ISR_Ep8pflag(void) interrupt 0
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{
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}
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void ISR_Ep2eflag(void) interrupt 0
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{
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}
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void ISR_Ep4eflag(void) interrupt 0
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{
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}
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void ISR_Ep6eflag(void) interrupt 0
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{
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}
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void ISR_Ep8eflag(void) interrupt 0
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{
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}
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void ISR_Ep2fflag(void) interrupt 0
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{
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}
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void ISR_Ep4fflag(void) interrupt 0
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{
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}
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void ISR_Ep6fflag(void) interrupt 0
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{
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}
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void ISR_Ep8fflag(void) interrupt 0
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{
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}
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void ISR_GpifComplete(void) interrupt 0
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{
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}
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void ISR_GpifWaveform(void) interrupt 0
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{
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}
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void Setup_FLOWSTATE_Read ( void )
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{
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FLOWSTATE = FlowStates[18]; // 1000 0011b - FSE=1, FS[2:0]=003
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SYNCDELAY;
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FLOWEQ0CTL = FlowStates[20]; // CTL1/CTL2 = 0 when flow condition equals zero (data flows)
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SYNCDELAY;
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FLOWEQ1CTL = FlowStates[21]; // CTL1/CTL2 = 1 when flow condition equals one (data does not flow)
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SYNCDELAY;
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}
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void Setup_FLOWSTATE_Write ( void )
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{
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FLOWSTATE = FlowStates[27]; // 1000 0001b - FSE=1, FS[2:0]=001
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SYNCDELAY;
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FLOWEQ0CTL = FlowStates[29]; // CTL0 = 0 when flow condition equals zero (data flows)
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SYNCDELAY;
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FLOWEQ1CTL = FlowStates[30]; // CTL0 = 1 when flow condition equals one (data does not flow)
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SYNCDELAY;
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}
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