518 lines
23 KiB
C
518 lines
23 KiB
C
#ifndef FX2_REGS_H
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#define FX2_REGS_H
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#ifdef ALLOCATE_EXTERN
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#define XBYTE( name, addr) xdata volatile unsigned char name _at_ addr
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#else
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#define XBYTE( name, addr) extern xdata volatile unsigned char name
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#endif
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// ============================================================================
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// General configuration
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// ============================================================================
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XBYTE( CPUCS , 0xE600); // Control & Status
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XBYTE( IFCONFIG , 0xE601); // Interface Configuration
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XBYTE( PINFLAGSAB , 0xE602); // FIFO FLAGA and FLAGB Assignments
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XBYTE( PINFLAGSCD , 0xE603); // FIFO FLAGC and FLAGD Assignments
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XBYTE( FIFORESET , 0xE604); // Restore FIFOS to default state
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XBYTE( BREAKPT , 0xE605); // Breakpoint
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XBYTE( BPADDRH , 0xE606); // Breakpoint Address H
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XBYTE( BPADDRL , 0xE607); // Breakpoint Address L
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XBYTE( UART230 , 0xE608); // 230 Kbaud clock for T0,T1,T2
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XBYTE( FIFOPINPOLAR , 0xE609); // FIFO polarities
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XBYTE( REVID , 0xE60A); // Chip Revision
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XBYTE( REVCTL , 0xE60B); // Chip Revision Control
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// ============================================================================
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// Endpoint configuration registers
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// ============================================================================
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XBYTE( EP1OUTCFG , 0xE610); // Endpoint 1-OUT Configuration
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XBYTE( EP1INCFG , 0xE611); // Endpoint 1-IN Configuration
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XBYTE( EP2CFG , 0xE612); // Endpoint 2 Configuration
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XBYTE( EP4CFG , 0xE613); // Endpoint 4 Configuration
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XBYTE( EP6CFG , 0xE614); // Endpoint 6 Configuration
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XBYTE( EP8CFG , 0xE615); // Endpoint 8 Configuration
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XBYTE( EP2FIFOCFG , 0xE618); // Endpoint 2 FIFO configuration
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XBYTE( EP4FIFOCFG , 0xE619); // Endpoint 4 FIFO configuration
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XBYTE( EP6FIFOCFG , 0xE61A); // Endpoint 6 FIFO configuration
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XBYTE( EP8FIFOCFG , 0xE61B); // Endpoint 8 FIFO configuration
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XBYTE( EP2AUTOINLENH , 0xE620); // Endpoint 2 Packet Length H (IN only)
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XBYTE( EP2AUTOINLENL , 0xE621); // Endpoint 2 Packet Length L (IN only)
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XBYTE( EP4AUTOINLENH , 0xE622); // Endpoint 4 Packet Length H (IN only)
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XBYTE( EP4AUTOINLENL , 0xE623); // Endpoint 4 Packet Length L (IN only)
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XBYTE( EP6AUTOINLENH , 0xE624); // Endpoint 6 Packet Length H (IN only)
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XBYTE( EP6AUTOINLENL , 0xE625); // Endpoint 6 Packet Length L (IN only)
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XBYTE( EP8AUTOINLENH , 0xE626); // Endpoint 8 Packet Length H (IN only)
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XBYTE( EP8AUTOINLENL , 0xE627); // Endpoint 8 Packet Length L (IN only)
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XBYTE( EP2FIFOPFH , 0xE630); // EP2 Programmable Flag trigger H
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XBYTE( EP2FIFOPFL , 0xE631); // EP2 Programmable Flag trigger L
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XBYTE( EP4FIFOPFH , 0xE632); // EP4 Programmable Flag trigger H
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XBYTE( EP4FIFOPFL , 0xE633); // EP4 Programmable Flag trigger L
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XBYTE( EP6FIFOPFH , 0xE634); // EP6 Programmable Flag trigger H
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XBYTE( EP6FIFOPFL , 0xE635); // EP6 Programmable Flag trigger L
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XBYTE( EP8FIFOPFH , 0xE636); // EP8 Programmable Flag trigger H
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XBYTE( EP8FIFOPFL , 0xE637); // EP8 Programmable Flag trigger L
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XBYTE( EP2ISOINPKTS , 0xE640); // EP2 (if ISO) IN Packets per frame (1-3)
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XBYTE( EP4ISOINPKTS , 0xE641); // EP4 (if ISO) IN Packets per frame (1-3)
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XBYTE( EP6ISOINPKTS , 0xE642); // EP6 (if ISO) IN Packets per frame (1-3)
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XBYTE( EP8ISOINPKTS , 0xE643); // EP8 (if ISO) IN Packets per frame (1-3)
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XBYTE( INPKTEND , 0xE648); // Force IN Packet End
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XBYTE( OUTPKTEND , 0xE649); // Force OUT Packet End
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// ============================================================================
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// Interrupts
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// ============================================================================
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XBYTE( EP2FIFOIE , 0xE650); // Endpoint 2 Flag Interrupt Enable
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XBYTE( EP2FIFOIRQ , 0xE651); // Endpoint 2 Flag Interrupt Request
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XBYTE( EP4FIFOIE , 0xE652); // Endpoint 4 Flag Interrupt Enable
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XBYTE( EP4FIFOIRQ , 0xE653); // Endpoint 4 Flag Interrupt Request
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XBYTE( EP6FIFOIE , 0xE654); // Endpoint 6 Flag Interrupt Enable
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XBYTE( EP6FIFOIRQ , 0xE655); // Endpoint 6 Flag Interrupt Request
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XBYTE( EP8FIFOIE , 0xE656); // Endpoint 8 Flag Interrupt Enable
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XBYTE( EP8FIFOIRQ , 0xE657); // Endpoint 8 Flag Interrupt Request
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XBYTE( IBNIE , 0xE658); // IN-BULK-NAK Interrupt Enable
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XBYTE( IBNIRQ , 0xE659); // IN-BULK-NAK interrupt Request
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XBYTE( NAKIE , 0xE65A); // Endpoint Ping NAK interrupt Enable
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XBYTE( NAKIRQ , 0xE65B); // Endpoint Ping NAK interrupt Request
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XBYTE( USBIE , 0xE65C); // USB Int Enables
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XBYTE( USBIRQ , 0xE65D); // USB Interrupt Requests
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XBYTE( EPIE , 0xE65E); // Endpoint Interrupt Enables
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XBYTE( EPIRQ , 0xE65F); // Endpoint Interrupt Requests
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XBYTE( GPIFIE , 0xE660); // GPIF Interrupt Enable
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XBYTE( GPIFIRQ , 0xE661); // GPIF Interrupt Request
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XBYTE( USBERRIE , 0xE662); // USB Error Interrupt Enables
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XBYTE( USBERRIRQ , 0xE663); // USB Error Interrupt Requests
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XBYTE( ERRCNTLIM , 0xE664); // USB Error counter and limit
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XBYTE( CLRERRCNT , 0xE665); // Clear Error Counter EC[3..0]
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XBYTE( INT2IVEC , 0xE666); // Interupt 2 (USB) Autovector
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XBYTE( INT4IVEC , 0xE667); // Interupt 4 (FIFOS & GPIF) Autovector
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XBYTE( INTSETUP , 0xE668); // Interrupt 2&4 Setup
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// ============================================================================
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// Input/Output
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// ============================================================================
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XBYTE( PORTACFG , 0xE670); // I/O Port A Alternate Configuration
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XBYTE( PORTCCFG , 0xE671); // I/O Port C Alternate Configuration
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XBYTE( PORTECFG , 0xE672); // I/O Port E Alternate Configuration
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XBYTE( I2CS , 0xE678); // I2C Control & Status
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XBYTE( I2DAT , 0xE679); // I2C Data
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XBYTE( I2CTL , 0xE67A); // I2C Control
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XBYTE( XAUTODAT1 , 0xE67B); // Autopointer1 MOVX access
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XBYTE( XAUTODAT2 , 0xE67C); // Autopointer2 MOVX access
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// ============================================================================
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// USB Control
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// ============================================================================
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XBYTE( USBCS , 0xE680); // USB Control & Status
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XBYTE( SUSPEND , 0xE681); // Put chip into suspend
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XBYTE( WAKEUPCS , 0xE682); // Wakeup source and polarity
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XBYTE( TOGCTL , 0xE683); // Toggle Control
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XBYTE( USBFRAMEH , 0xE684); // USB Frame count H
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XBYTE( USBFRAMEL , 0xE685); // USB Frame count L
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XBYTE( MICROFRAME , 0xE686); // Microframe count, 0-7
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XBYTE( FNADDR , 0xE687); // USB Function address
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// ============================================================================
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// Endpoints
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// ============================================================================
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XBYTE( EP0BCH , 0xE68A); // Endpoint 0 Byte Count H
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XBYTE( EP0BCL , 0xE68B); // Endpoint 0 Byte Count L
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XBYTE( EP1OUTBC , 0xE68D); // Endpoint 1 OUT Byte Count
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XBYTE( EP1INBC , 0xE68F); // Endpoint 1 IN Byte Count
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XBYTE( EP2BCH , 0xE690); // Endpoint 2 Byte Count H
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XBYTE( EP2BCL , 0xE691); // Endpoint 2 Byte Count L
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XBYTE( EP4BCH , 0xE694); // Endpoint 4 Byte Count H
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XBYTE( EP4BCL , 0xE695); // Endpoint 4 Byte Count L
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XBYTE( EP6BCH , 0xE698); // Endpoint 6 Byte Count H
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XBYTE( EP6BCL , 0xE699); // Endpoint 6 Byte Count L
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XBYTE( EP8BCH , 0xE69C); // Endpoint 8 Byte Count H
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XBYTE( EP8BCL , 0xE69D); // Endpoint 8 Byte Count L
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XBYTE( EP0CS , 0xE6A0); // Endpoint Control and Status
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XBYTE( EP1OUTCS , 0xE6A1); // Endpoint 1 OUT Control and Status
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XBYTE( EP1INCS , 0xE6A2); // Endpoint 1 IN Control and Status
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XBYTE( EP2CS , 0xE6A3); // Endpoint 2 Control and Status
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XBYTE( EP4CS , 0xE6A4); // Endpoint 4 Control and Status
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XBYTE( EP6CS , 0xE6A5); // Endpoint 6 Control and Status
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XBYTE( EP8CS , 0xE6A6); // Endpoint 8 Control and Status
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XBYTE( EP2FIFOFLGS , 0xE6A7); // Endpoint 2 Flags
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XBYTE( EP4FIFOFLGS , 0xE6A8); // Endpoint 4 Flags
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XBYTE( EP6FIFOFLGS , 0xE6A9); // Endpoint 6 Flags
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XBYTE( EP8FIFOFLGS , 0xE6AA); // Endpoint 8 Flags
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XBYTE( EP2FIFOBCH , 0xE6AB); // EP2 FIFO total byte count H
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XBYTE( EP2FIFOBCL , 0xE6AC); // EP2 FIFO total byte count L
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XBYTE( EP4FIFOBCH , 0xE6AD); // EP4 FIFO total byte count H
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XBYTE( EP4FIFOBCL , 0xE6AE); // EP4 FIFO total byte count L
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XBYTE( EP6FIFOBCH , 0xE6AF); // EP6 FIFO total byte count H
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XBYTE( EP6FIFOBCL , 0xE6B0); // EP6 FIFO total byte count L
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XBYTE( EP8FIFOBCH , 0xE6B1); // EP8 FIFO total byte count H
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XBYTE( EP8FIFOBCL , 0xE6B2); // EP8 FIFO total byte count L
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XBYTE( SUDPTRH , 0xE6B3); // Setup Data Pointer high address byte
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XBYTE( SUDPTRL , 0xE6B4); // Setup Data Pointer low address byte
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XBYTE( SUDPTRCTL , 0xE6B5); // Setup Data Pointer Auto Mode
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XBYTE( SETUPDAT[8] , 0xE6B8); // 8 bytes of SETUP data
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// ============================================================================
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// GPIF
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// ============================================================================
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XBYTE( GPIFWFSELECT , 0xE6C0); // Waveform Selector
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XBYTE( GPIFIDLECS , 0xE6C1); // GPIF Done, GPIF IDLE drive mode
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XBYTE( GPIFIDLECTL , 0xE6C2); // Inactive Bus, CTL states
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XBYTE( GPIFCTLCFG , 0xE6C3); // CTL OUT pin drive
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XBYTE( GPIFADRH , 0xE6C4); // GPIF Address H
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XBYTE( GPIFADRL , 0xE6C5); // GPIF Address L
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XBYTE( GPIFTCB3 , 0xE6CE); // GPIF Transaction Count Byte 3
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XBYTE( GPIFTCB2 , 0xE6CF); // GPIF Transaction Count Byte 2
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XBYTE( GPIFTCB1 , 0xE6D0); // GPIF Transaction Count Byte 1
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XBYTE( GPIFTCB0 , 0xE6D1); // GPIF Transaction Count Byte 0
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#define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility
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#define EP2GPIFTCL GPIFTCB0 //
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#define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility
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#define EP4GPIFTCL GPIFTCB0 //
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#define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility
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#define EP6GPIFTCL GPIFTCB0 //
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#define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility
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#define EP8GPIFTCL GPIFTCB0 //
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XBYTE( EP2GPIFFLGSEL , 0xE6D2); // EP2 GPIF Flag select
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XBYTE( EP2GPIFPFSTOP , 0xE6D3); // Stop GPIF EP2 transaction on prog. flag
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XBYTE( EP2GPIFTRIG , 0xE6D4); // EP2 FIFO Trigger
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XBYTE( EP4GPIFFLGSEL , 0xE6DA); // EP4 GPIF Flag select
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XBYTE( EP4GPIFPFSTOP , 0xE6DB); // Stop GPIF EP4 transaction on prog. flag
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XBYTE( EP4GPIFTRIG , 0xE6DC); // EP4 FIFO Trigger
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XBYTE( EP6GPIFFLGSEL , 0xE6E2); // EP6 GPIF Flag select
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XBYTE( EP6GPIFPFSTOP , 0xE6E3); // Stop GPIF EP6 transaction on prog. flag
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XBYTE( EP6GPIFTRIG , 0xE6E4); // EP6 FIFO Trigger
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XBYTE( EP8GPIFFLGSEL , 0xE6EA); // EP8 GPIF Flag select
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XBYTE( EP8GPIFPFSTOP , 0xE6EB); // Stop GPIF EP8 transaction on prog. flag
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XBYTE( EP8GPIFTRIG , 0xE6EC); // EP8 FIFO Trigger
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XBYTE( XGPIFSGLDATH , 0xE6F0); // GPIF Data H (16-bit mode only)
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XBYTE( XGPIFSGLDATLX , 0xE6F1); // Read/Write GPIF Data L & trigger transac
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XBYTE( XGPIFSGLDATLNOX , 0xE6F2); // Read GPIF Data L, no transac trigger
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XBYTE( GPIFREADYCFG , 0xE6F3); // Internal RDY,Sync/Async, RDY5CFG
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XBYTE( GPIFREADYSTAT , 0xE6F4); // RDY pin states
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XBYTE( GPIFABORT , 0xE6F5); // Abort GPIF cycles
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// ============================================================================
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// UDMA
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// ============================================================================
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XBYTE( FLOWSTATE , 0xE6C6); // Defines GPIF flow state
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XBYTE( FLOWLOGIC , 0xE6C7); // Defines flow/hold decision criteria
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XBYTE( FLOWEQ0CTL , 0xE6C8); // CTL states during active flow state
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XBYTE( FLOWEQ1CTL , 0xE6C9); // CTL states during hold flow state
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XBYTE( FLOWHOLDOFF , 0xE6CA);
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XBYTE( FLOWSTB , 0xE6CB); // CTL/RDY Signal to use as master data strobe
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XBYTE( FLOWSTBEDGE , 0xE6CC); // Defines active master strobe edge
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XBYTE( FLOWSTBHPERIOD , 0xE6CD); // Half Period of output master strobe
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XBYTE( GPIFHOLDAMOUNT , 0xE60C); // Data delay shift
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XBYTE( UDMACRCH , 0xE67D); // CRC Upper byte
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XBYTE( UDMACRCL , 0xE67E); // CRC Lower byte
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XBYTE( UDMACRCQUAL , 0xE67F); // UDMA In only, host terminated use only
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// ============================================================================
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// Endpoint Buffers
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// ============================================================================
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XBYTE( EP0BUF [64] , 0xE740); // EP0 IN-OUT buffer
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XBYTE( EP1OUTBUF [64] , 0xE780); // EP1-OUT buffer
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XBYTE( EP1INBUF [64] , 0xE7C0); // EP1-IN buffer
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XBYTE( EP2FIFOBUF [1024] , 0xF000); // 512/1024-byte EP2 buffer (IN or OUT)
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XBYTE( EP4FIFOBUF [1024] , 0xF400); // 512 byte EP4 buffer (IN or OUT)
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XBYTE( EP6FIFOBUF [1024] , 0xF800); // 512/1024-byte EP6 buffer (IN or OUT)
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XBYTE( EP8FIFOBUF [1024] , 0xFC00); // 512 byte EP8 buffer (IN or OUT)
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// ============================================================================
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// Error Correction Code (ECC) Registers (FX2LP/FX1 only)
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// ============================================================================
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XBYTE( ECCCFG , 0xE628); // ECC Configuration
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XBYTE( ECCRESET , 0xE629); // ECC Reset
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XBYTE( ECC1B0 , 0xE62A); // ECC1 Byte 0
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XBYTE( ECC1B1 , 0xE62B); // ECC1 Byte 1
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XBYTE( ECC1B2 , 0xE62C); // ECC1 Byte 2
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XBYTE( ECC2B0 , 0xE62D); // ECC2 Byte 0
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XBYTE( ECC2B1 , 0xE62E); // ECC2 Byte 1
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XBYTE( ECC2B2 , 0xE62F); // ECC2 Byte 2
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// ============================================================================
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// Feature Registers (FX2LP/FX1 only)
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// ============================================================================
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XBYTE( GPCR2 , 0xE50D); // Chip Features
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// ============================================================================
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// Special Function Registers (sfr)
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// ============================================================================
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#include <fx2_regs_sfr8x.h>
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#include <fx2_regs_sfr9x.h>
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#include <fx2_regs_sfrAx.h>
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#include <fx2_regs_sfrBx.h>
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#include <fx2_regs_sfrCx.h>
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#include <fx2_regs_sfrDx.h>
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#include <fx2_regs_sfrEx.h>
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#include <fx2_regs_sfrFx.h>
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// ============================================================================
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// Bit masks
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// ============================================================================
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// ----------------------------------------------------------------------------
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// CPU Control & Status Register (CPUCS)
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// ----------------------------------------------------------------------------
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#define bmPRTCSTB bmBIT5
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#define bmCLKSPD (bmBIT4 | bmBIT3)
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#define bmCLKSPD1 bmBIT4
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#define bmCLKSPD0 bmBIT3
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#define bmCLKINV bmBIT2
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#define bmCLKOE bmBIT1
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#define bm8051RES bmBIT0
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// ----------------------------------------------------------------------------
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// Port A (PORTACFG)
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// ----------------------------------------------------------------------------
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#define bmFLAGD bmBIT7
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#define bmINT1 bmBIT1
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#define bmINT0 bmBIT0
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// ----------------------------------------------------------------------------
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// Port C (PORTCCFG)
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// ----------------------------------------------------------------------------
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#define bmGPIFA7 bmBIT7
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#define bmGPIFA6 bmBIT6
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#define bmGPIFA5 bmBIT5
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#define bmGPIFA4 bmBIT4
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#define bmGPIFA3 bmBIT3
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#define bmGPIFA2 bmBIT2
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#define bmGPIFA1 bmBIT1
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#define bmGPIFA0 bmBIT0
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// ----------------------------------------------------------------------------
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// Port E (PORTECFG)
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// ----------------------------------------------------------------------------
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#define bmGPIFA8 bmBIT7
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#define bmT2EX bmBIT6
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#define bmINT6 bmBIT5
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#define bmRXD1OUT bmBIT4
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#define bmRXD0OUT bmBIT3
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#define bmT2OUT bmBIT2
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#define bmT1OUT bmBIT1
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#define bmT0OUT bmBIT0
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// ----------------------------------------------------------------------------
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// I2C Control & Status Register (I2CS)
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// ----------------------------------------------------------------------------
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#define bmSTART bmBIT7
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#define bmSTOP bmBIT6
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#define bmLASTRD bmBIT5
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#define bmID (bmBIT4 | bmBIT3)
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#define bmBERR bmBIT2
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#define bmACK bmBIT1
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#define bmDONE bmBIT0
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// ----------------------------------------------------------------------------
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// I2C Control Register (I2CTL)
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// ----------------------------------------------------------------------------
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#define bmSTOPIE bmBIT1
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#define bm400KHZ bmBIT0
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// ----------------------------------------------------------------------------
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// Interrupt 2 (USB) Autovector Register (INT2IVEC)
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// ----------------------------------------------------------------------------
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#define bmIV4 bmBIT6
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#define bmIV3 bmBIT5
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#define bmIV2 bmBIT4
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#define bmIV1 bmBIT3
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#define bmIV0 bmBIT2
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// ----------------------------------------------------------------------------
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// USB Interrupt Request & Enable Registers (USBIE/USBIRQ)
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// ----------------------------------------------------------------------------
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#define bmEP0ACK bmBIT6
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#define bmHSGRANT bmBIT5
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#define bmURES bmBIT4
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#define bmSUSP bmBIT3
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#define bmSUTOK bmBIT2
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#define bmSOF bmBIT1
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#define bmSUDAV bmBIT0
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// ----------------------------------------------------------------------------
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// USB Interrupt Request & Enable Registers (EPIE/EPIRQ)
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// ----------------------------------------------------------------------------
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#define bmEP8 bmBIT7
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#define bmEP6 bmBIT6
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#define bmEP4 bmBIT5
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#define bmEP2 bmBIT4
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#define bmEP1OUT bmBIT3
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#define bmEP1IN bmBIT2
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#define bmEP0OUT bmBIT1
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#define bmEP0IN bmBIT0
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// ----------------------------------------------------------------------------
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// GPIF Interrupt Request & Enable Registers (GPIFIE/GPIFIRQ)
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// ----------------------------------------------------------------------------
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#define bmGPIFWF bmBIT1
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#define bmGPIFDONE bmBIT0
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// ----------------------------------------------------------------------------
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// Breakpoint register (BREAKPT)
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// ----------------------------------------------------------------------------
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#define bmBREAK bmBIT3
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#define bmBPPULSE bmBIT2
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#define bmBPEN bmBIT1
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// ----------------------------------------------------------------------------
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// Interrupt 2 & 4 Setup (INTSETUP)
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// ----------------------------------------------------------------------------
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#define bmAV2EN bmBIT3
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#define INT4IN bmBIT1
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#define bmAV4EN bmBIT0
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// ----------------------------------------------------------------------------
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// USB Control & Status Register (USBCS)
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// ----------------------------------------------------------------------------
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#define bmHSM bmBIT7
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#define bmDISCON bmBIT3
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#define bmNOSYNSOF bmBIT2
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#define bmRENUM bmBIT1
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#define bmSIGRESUME bmBIT0
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// ----------------------------------------------------------------------------
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// Wakeup Control and Status Register (WAKEUPCS)
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// ----------------------------------------------------------------------------
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#define bmWU2 bmBIT7
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#define bmWU bmBIT6
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#define bmWU2POL bmBIT5
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#define bmWUPOL bmBIT4
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#define bmDPEN bmBIT2
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#define bmWU2EN bmBIT1
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#define bmWUEN bmBIT0
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|
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// ----------------------------------------------------------------------------
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// End Point 0 Control & Status Register (EP0CS)
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// ----------------------------------------------------------------------------
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#define bmHSNAK bmBIT7
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|
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// ----------------------------------------------------------------------------
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// End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS)
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// ----------------------------------------------------------------------------
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#define bmEPBUSY bmBIT1
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#define bmEPSTALL bmBIT0
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|
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// ----------------------------------------------------------------------------
|
|
// End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS)
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// ----------------------------------------------------------------------------
|
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#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
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#define bmEPFULL bmBIT3
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#define bmEPEMPTY bmBIT2
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|
|
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/* Endpoint Status (EP2468STAT) SFR bits */
|
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#define bmEP8FULL bmBIT7
|
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#define bmEP8EMPTY bmBIT6
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#define bmEP6FULL bmBIT5
|
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#define bmEP6EMPTY bmBIT4
|
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#define bmEP4FULL bmBIT3
|
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#define bmEP4EMPTY bmBIT2
|
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#define bmEP2FULL bmBIT1
|
|
#define bmEP2EMPTY bmBIT0
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|
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// SETUP Data Pointer Auto Mode (SUDPTRCTL)
|
|
// ----------------------------------------------------------------------------
|
|
#define bmSDPAUTO bmBIT0
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Endpoint Data Toggle Control (TOGCTL)
|
|
// ----------------------------------------------------------------------------
|
|
#define bmQUERYTOGGLE bmBIT7
|
|
#define bmSETTOGGLE bmBIT6
|
|
#define bmRESETTOGGLE bmBIT5
|
|
#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ)
|
|
// ----------------------------------------------------------------------------
|
|
#define bmEP8IBN bmBIT5
|
|
#define bmEP6IBN bmBIT4
|
|
#define bmEP4IBN bmBIT3
|
|
#define bmEP2IBN bmBIT2
|
|
#define bmEP1IBN bmBIT1
|
|
#define bmEP0IBN bmBIT0
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// PING-NAK enable and request bits (NAKIE/NAKIRQ)
|
|
// ----------------------------------------------------------------------------
|
|
#define bmEP8PING bmBIT7
|
|
#define bmEP6PING bmBIT6
|
|
#define bmEP4PING bmBIT5
|
|
#define bmEP2PING bmBIT4
|
|
#define bmEP1PING bmBIT3
|
|
#define bmEP0PING bmBIT2
|
|
#define bmIBN bmBIT0
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Interface Configuration bits (IFCONFIG)
|
|
// ----------------------------------------------------------------------------
|
|
#define bmIFCLKSRC bmBIT7
|
|
#define bm3048MHZ bmBIT6
|
|
#define bmIFCLKOE bmBIT5
|
|
#define bmIFCLKPOL bmBIT4
|
|
#define bmASYNC bmBIT3
|
|
#define bmGSTATE bmBIT2
|
|
#define bmIFCFG1 bmBIT1
|
|
#define bmIFCFG0 bmBIT0
|
|
|
|
#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
|
|
#define bmIFGPIF bmIFCFG1
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG)
|
|
// ----------------------------------------------------------------------------
|
|
#define bmINFM bmBIT6
|
|
#define bmOEP bmBIT5
|
|
#define bmAUTOOUT bmBIT4
|
|
#define bmAUTOIN bmBIT3
|
|
#define bmZEROLENIN bmBIT2
|
|
#define bmWORDWIDE bmBIT0
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Chip Revision Control Bits (REVCTL) - used to ebable/disable revision
|
|
// specific features.
|
|
// ----------------------------------------------------------------------------
|
|
#define bmNOAUTOARM bmBIT1
|
|
#define bmSKIPCOMMIT bmBIT0
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// FIFO polarity (FIFOPINPOLAR)
|
|
// ----------------------------------------------------------------------------
|
|
#define bmPKTEND bmBIT5
|
|
#define bmSLOE bmBIT4
|
|
#define bmSLRD bmBIT3
|
|
#define bmSLWR bmBIT2
|
|
#define bmEF bmBIT1
|
|
#define bmFF bmBIT0
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// FIFO Reset bits (FIFORESET)
|
|
// ----------------------------------------------------------------------------
|
|
#define bmNAKALL bmBIT7
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Chip Feature Register (GPCR2)
|
|
// ----------------------------------------------------------------------------
|
|
#define bmFULLSPEEDONLY bmBIT4
|
|
|
|
#endif |