diff --git a/circuit/ael/mrmodels_include.ael b/circuit/ael/mrmodels_include.ael
new file mode 100644
index 0000000..1df651c
--- /dev/null
+++ b/circuit/ael/mrmodels_include.ael
@@ -0,0 +1,134 @@
+defun scan_folder_va( folder)
+{
+	decl modelFileList;
+	decl net = "";
+	decl file;
+	decl path;
+	
+	
+	// ----------------------------------------------------
+	// Collect veriloga model files in the specified folder
+	// ----------------------------------------------------
+	modelFileList = get_dir_files(folder,"va");
+	
+	while( is_list(modelFileList))
+	{
+		file = car(modelFileList);
+		path = strcat(folder,file);
+		net	 = strcat(net,sprintf("#load \"veriloga\", \"%s\"\n",path));
+
+		modelFileList = cdr( modelFileList);
+	}
+	
+	// ----------------------------------------------------
+	// scan sub folders
+	// ----------------------------------------------------
+	modelFileList = get_dir_files(folder);
+	
+	while( is_list(modelFileList))
+	{
+		file = car(modelFileList);
+		path = strcat(folder,file);
+	
+		if( is_dir(path) == TRUE)
+			if( file != "." && file != "..")
+				net = strcat(net,scan_folder_va(strcat(path,"/")));
+			
+		modelFileList = cdr( modelFileList);
+	}
+	
+	return net;
+}
+
+defun scan_folder( folder, ext)
+{
+	decl modelFileList;
+	decl net = "";
+	decl file;
+	decl path;
+	
+	
+	// ----------------------------------------------------
+	// Collect models in the specified folder
+	// ----------------------------------------------------
+	modelFileList = get_dir_files(folder,"mod");
+	
+	while( is_list(modelFileList))
+	{
+		file = car(modelFileList);
+		path = strcat(folder,file);
+		net	 = strcat(net,sprintf("#include \"%s\"\n",path));
+
+		modelFileList = cdr( modelFileList);
+	}
+	
+	modelFileList = get_dir_files(folder,"net");
+	
+	while( is_list(modelFileList))
+	{
+		file = car(modelFileList);
+		path = strcat(folder,file);
+		net	 = strcat(net,sprintf("#include \"%s\"\n",path));
+
+		modelFileList = cdr( modelFileList);
+	}
+	
+	// ----------------------------------------------------
+	// scan sub folders
+	// ----------------------------------------------------
+	modelFileList = get_dir_files(folder);
+	
+	while( is_list(modelFileList))
+	{
+		file = car(modelFileList);
+		path = strcat(folder,file);
+	
+		if( is_dir(path) == TRUE)
+			if( file != "." && file != "..")
+				net = strcat(net,scan_folder(strcat(path,"/"),ext));
+			
+		modelFileList = cdr( modelFileList);
+	}
+	
+	return net;
+}
+
+defun mrModels_process_netlist_cb( cbP, cbData, instH)
+{
+	decl net = "";
+	
+	net = strcat(net,"; models\n");
+	net	= strcat(net,scan_folder(MRMODELS_DIR_CIRCUIT_MODELS,""));
+	
+	net = strcat(net, "; veriloga models\n");
+	net	= strcat(net,scan_folder_va(MRMODELS_DIR_VERILOGA));
+	
+	fprintf(stderr, "%s",net);
+	return net;
+}
+
+// ----------------------------------------------------------------------------
+// Item definition
+// ----------------------------------------------------------------------------
+create_item(	"mrmodels_include",				// name
+				"Process Netlist Include",		// description label
+				"NetlistInclude",				// prefix
+				ITEM_UNIQUE | ITEM_GLOBAL,		// attributes
+				NULL,							// priority
+				NULL,							// iconName
+				standard_dialog,				// dialogName
+				NULL,							// dialogData
+				ComponentNetlistFmt,			// netlist format string
+				NULL,							// netlist data
+				ComponentAnnotFmt,				// display format string
+				NULL,							// symbol name
+				NULL,							// artwork type
+				NULL,							// artwork data
+				ITEM_PRIMITIVE_EX,				// extra attributes
+				
+				list(
+					dm_create_cb(	ITEM_NETLIST_CB,
+									"mrModels_process_netlist_cb",
+									"",
+									TRUE))
+);
diff --git a/de/ael/boot.ael b/de/ael/boot.ael
index 48877cf..bbf5e53 100644
--- a/de/ael/boot.ael
+++ b/de/ael/boot.ael
@@ -22,8 +22,7 @@ fprintf(stderr, "Loading %s design kit\n", MRMODELS_NAME);
 // Load
 // ----------------------------------------------------------------------------
 load( strcat( MRMODELS_DIR_DE_AEL,		"palette"				));
-
-////load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "mrmodels_include"		));
+load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "mrmodels_include"		));
 
 // load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "sample_fet"			));
 
diff --git a/mrModels/eesof_lib.cfg b/mrModels/eesof_lib.cfg
index b2eeb7b..9aeaca3 100644
--- a/mrModels/eesof_lib.cfg
+++ b/mrModels/eesof_lib.cfg
@@ -14,4 +14,4 @@ DOC_DIRECTORY             = ../doc
 DRC_DIRECTORY             = ../drc/rules
 NETLIST_EXPORTER_DIRECTORY= ../netlist_exp
 BIN_DIRECTORY             = ../bin/$SIMARCH$COMPILER_VER
-DEFAULTS_DESIGNS          = mrModels:netlistinclude:schematic
+DEFAULTS_DESIGNS=mrModels:mrmodels_include:schematic
diff --git a/mrModels/netlistinclude/schematic/master.tag b/mrModels/mrmodels_include/schematic/master.tag
similarity index 100%
rename from mrModels/netlistinclude/schematic/master.tag
rename to mrModels/mrmodels_include/schematic/master.tag
diff --git a/mrModels/netlistinclude/schematic/sch.oa b/mrModels/mrmodels_include/schematic/sch.oa
similarity index 84%
rename from mrModels/netlistinclude/schematic/sch.oa
rename to mrModels/mrmodels_include/schematic/sch.oa
index e7ba813..189a422 100644
Binary files a/mrModels/netlistinclude/schematic/sch.oa and b/mrModels/mrmodels_include/schematic/sch.oa differ
diff --git a/mrModels/netlistinclude/symbol/master.tag b/mrModels/mrmodels_include/symbol/master.tag
similarity index 100%
rename from mrModels/netlistinclude/symbol/master.tag
rename to mrModels/mrmodels_include/symbol/master.tag
diff --git a/mrModels/netlistinclude/symbol/symbol.oa b/mrModels/mrmodels_include/symbol/symbol.oa
similarity index 59%
rename from mrModels/netlistinclude/symbol/symbol.oa
rename to mrModels/mrmodels_include/symbol/symbol.oa
index 03c3512..eb639bc 100644
Binary files a/mrModels/netlistinclude/symbol/symbol.oa and b/mrModels/mrmodels_include/symbol/symbol.oa differ
diff --git a/mrModels_tech/eesof_lib.cfg b/mrModels_tech/eesof_lib.cfg
index 1a51c0c..bf037a8 100644
--- a/mrModels_tech/eesof_lib.cfg
+++ b/mrModels_tech/eesof_lib.cfg
@@ -1,3 +1,3 @@
 TECH_DESC=mrModels_tech
-DEFAULTS_DESIGNS=mrModels:netlistinclude:schematic;
+DEFAULTS_DESIGNS=mrModels:mrmodels_include:schematic
 EXPR_EVALUATOR_PREF=No Preference