Commit Graph

  • 44c68d04f9 Added the generic include components. It scans model folders to add items to a simulation. main roka 2026-06-26 16:59:08 +02:00
  • 459a3dd394 Added a two component palette with bipolar transistors. roka 2026-06-26 16:16:40 +02:00
  • e87aed86c1 Added base technology configuration roka 2026-06-26 15:51:07 +02:00
  • c1eaff9a06 Added symbol files roka 2026-06-26 15:50:23 +02:00
  • 07d6172524 Added VerilogA reference manuals roka 2026-06-26 15:48:29 +02:00
  • ca65b637df Added device kit configuration file roka 2026-06-26 15:47:18 +02:00
  • a24bb26f9d First absolute minimum check in roka 2026-06-25 20:20:38 +02:00