Files

135 lines
3.3 KiB
Plaintext

defun scan_folder_va( folder)
{
decl modelFileList;
decl net = "";
decl file;
decl path;
// ----------------------------------------------------
// Collect veriloga model files in the specified folder
// ----------------------------------------------------
modelFileList = get_dir_files(folder,"va");
while( is_list(modelFileList))
{
file = car(modelFileList);
path = strcat(folder,file);
net = strcat(net,sprintf("#load \"veriloga\", \"%s\"\n",path));
modelFileList = cdr( modelFileList);
}
// ----------------------------------------------------
// scan sub folders
// ----------------------------------------------------
modelFileList = get_dir_files(folder);
while( is_list(modelFileList))
{
file = car(modelFileList);
path = strcat(folder,file);
if( is_dir(path) == TRUE)
if( file != "." && file != "..")
net = strcat(net,scan_folder_va(strcat(path,"/")));
modelFileList = cdr( modelFileList);
}
return net;
}
defun scan_folder( folder, ext)
{
decl modelFileList;
decl net = "";
decl file;
decl path;
// ----------------------------------------------------
// Collect models in the specified folder
// ----------------------------------------------------
modelFileList = get_dir_files(folder,"mod");
while( is_list(modelFileList))
{
file = car(modelFileList);
path = strcat(folder,file);
net = strcat(net,sprintf("#include \"%s\"\n",path));
modelFileList = cdr( modelFileList);
}
modelFileList = get_dir_files(folder,"net");
while( is_list(modelFileList))
{
file = car(modelFileList);
path = strcat(folder,file);
net = strcat(net,sprintf("#include \"%s\"\n",path));
modelFileList = cdr( modelFileList);
}
// ----------------------------------------------------
// scan sub folders
// ----------------------------------------------------
modelFileList = get_dir_files(folder);
while( is_list(modelFileList))
{
file = car(modelFileList);
path = strcat(folder,file);
if( is_dir(path) == TRUE)
if( file != "." && file != "..")
net = strcat(net,scan_folder(strcat(path,"/"),ext));
modelFileList = cdr( modelFileList);
}
return net;
}
defun mrModels_process_netlist_cb( cbP, cbData, instH)
{
decl net = "";
net = strcat(net,"; models\n");
net = strcat(net,scan_folder(MRMODELS_DIR_CIRCUIT_MODELS,""));
net = strcat(net, "; veriloga models\n");
net = strcat(net,scan_folder_va(MRMODELS_DIR_VERILOGA));
fprintf(stderr, "%s",net);
return net;
}
// ----------------------------------------------------------------------------
// Item definition
// ----------------------------------------------------------------------------
create_item( "mrmodels_include", // name
"Process Netlist Include", // description label
"NetlistInclude", // prefix
ITEM_UNIQUE | ITEM_GLOBAL, // attributes
NULL, // priority
NULL, // iconName
standard_dialog, // dialogName
NULL, // dialogData
ComponentNetlistFmt, // netlist format string
NULL, // netlist data
ComponentAnnotFmt, // display format string
NULL, // symbol name
NULL, // artwork type
NULL, // artwork data
ITEM_PRIMITIVE_EX, // extra attributes
list(
dm_create_cb( ITEM_NETLIST_CB,
"mrModels_process_netlist_cb",
"",
TRUE))
);