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DESIGN_KIT_NAME = mrModels
TECH_DESC = mrModels
VERSION = 1.0
DESIGN_KIT_ROOT = ../
BOOT_AEL = ../de/ael/boot
ADSLIBCONFIG_DIRECTORY = ../circuit/config
INPUT_DATA_PATH = ../circuit.data;../circuit/models
DDS_TEMPLATES_DIRECTORY = ../circuit/templates
TEMPLATES_DIRECTORY = ../circuit/templates/library
LIB_BROWSER_CTL = ../circuit/records/mrModels_library.ctl
VERILOGA_DIRECTORY = ../veriloga
EXPRESSIONS_DIRECTORY = ../expressions/ael
DOC_DIRECTORY = ../doc
DRC_DIRECTORY = ../drc/rules
NETLIST_EXPORTER_DIRECTORY= ../netlist_exp
BIN_DIRECTORY = ../bin/$SIMARCH$COMPILER_VER
DEFAULTS_DESIGNS=mrModels:mrmodels_include:schematic