From 39572774549608907973c0659deab21b86005e90 Mon Sep 17 00:00:00 2001 From: Roka Miklos Date: Sat, 27 Jun 2026 17:33:25 +0200 Subject: [PATCH] Absolute minimal initial checkin --- .gitignore | 4 + circuit/ael/mrmodels_include.ael | 134 ++++++++++++++++++ de/ael/boot.ael | 24 ++++ lib_ro.defs | 7 + lib_rw.defs | 7 + mrModels/eesof_lib.cfg | 17 +++ .../mrmodels_include/schematic/master.tag | 2 + mrModels/mrmodels_include/schematic/sch.oa | Bin 0 -> 21404 bytes mrModels/mrmodels_include/symbol/master.tag | 2 + mrModels/mrmodels_include/symbol/symbol.oa | Bin 0 -> 15852 bytes mrModels/tech.db | Bin 0 -> 10604 bytes mrModels_tech/eesof_lib.cfg | 3 + mrModels_tech/tech.db | Bin 0 -> 10604 bytes 13 files changed, 200 insertions(+) create mode 100644 .gitignore create mode 100644 circuit/ael/mrmodels_include.ael create mode 100644 de/ael/boot.ael create mode 100644 lib_ro.defs create mode 100644 lib_rw.defs create mode 100644 mrModels/eesof_lib.cfg create mode 100644 mrModels/mrmodels_include/schematic/master.tag create mode 100644 mrModels/mrmodels_include/schematic/sch.oa create mode 100644 mrModels/mrmodels_include/symbol/master.tag create mode 100644 mrModels/mrmodels_include/symbol/symbol.oa create mode 100644 mrModels/tech.db create mode 100644 mrModels_tech/eesof_lib.cfg create mode 100644 mrModels_tech/tech.db diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..4c26d32 --- /dev/null +++ b/.gitignore @@ -0,0 +1,4 @@ +*.*~ +*.atf +.oalib +libRefs.json diff --git a/circuit/ael/mrmodels_include.ael b/circuit/ael/mrmodels_include.ael new file mode 100644 index 0000000..1df651c --- /dev/null +++ b/circuit/ael/mrmodels_include.ael @@ -0,0 +1,134 @@ +defun scan_folder_va( folder) +{ + decl modelFileList; + decl net = ""; + decl file; + decl path; + + + // ---------------------------------------------------- + // Collect veriloga model files in the specified folder + // ---------------------------------------------------- + modelFileList = get_dir_files(folder,"va"); + + while( is_list(modelFileList)) + { + file = car(modelFileList); + path = strcat(folder,file); + net = strcat(net,sprintf("#load \"veriloga\", \"%s\"\n",path)); + + modelFileList = cdr( modelFileList); + } + + // ---------------------------------------------------- + // scan sub folders + // ---------------------------------------------------- + modelFileList = get_dir_files(folder); + + while( is_list(modelFileList)) + { + file = car(modelFileList); + path = strcat(folder,file); + + if( is_dir(path) == TRUE) + if( file != "." && file != "..") + net = strcat(net,scan_folder_va(strcat(path,"/"))); + + modelFileList = cdr( modelFileList); + } + + return net; +} + +defun scan_folder( folder, ext) +{ + decl modelFileList; + decl net = ""; + decl file; + decl path; + + + // ---------------------------------------------------- + // Collect models in the specified folder + // ---------------------------------------------------- + modelFileList = get_dir_files(folder,"mod"); + + while( is_list(modelFileList)) + { + file = car(modelFileList); + path = strcat(folder,file); + net = strcat(net,sprintf("#include \"%s\"\n",path)); + + modelFileList = cdr( modelFileList); + } + + modelFileList = get_dir_files(folder,"net"); + + while( is_list(modelFileList)) + { + file = car(modelFileList); + path = strcat(folder,file); + net = strcat(net,sprintf("#include \"%s\"\n",path)); + + modelFileList = cdr( modelFileList); + } + + // ---------------------------------------------------- + // scan sub folders + // ---------------------------------------------------- + modelFileList = get_dir_files(folder); + + while( is_list(modelFileList)) + { + file = car(modelFileList); + path = strcat(folder,file); + + if( is_dir(path) == TRUE) + if( file != "." && file != "..") + net = strcat(net,scan_folder(strcat(path,"/"),ext)); + + modelFileList = cdr( modelFileList); + } + + return net; +} + +defun mrModels_process_netlist_cb( cbP, cbData, instH) +{ + decl net = ""; + + net = strcat(net,"; models\n"); + net = strcat(net,scan_folder(MRMODELS_DIR_CIRCUIT_MODELS,"")); + + net = strcat(net, "; veriloga models\n"); + net = strcat(net,scan_folder_va(MRMODELS_DIR_VERILOGA)); + + fprintf(stderr, "%s",net); + return net; +} + +// ---------------------------------------------------------------------------- +// Item definition +// ---------------------------------------------------------------------------- +create_item( "mrmodels_include", // name + "Process Netlist Include", // description label + "NetlistInclude", // prefix + ITEM_UNIQUE | ITEM_GLOBAL, // attributes + NULL, // priority + NULL, // iconName + standard_dialog, // dialogName + NULL, // dialogData + ComponentNetlistFmt, // netlist format string + NULL, // netlist data + ComponentAnnotFmt, // display format string + NULL, // symbol name + NULL, // artwork type + NULL, // artwork data + ITEM_PRIMITIVE_EX, // extra attributes + + list( + dm_create_cb( ITEM_NETLIST_CB, + "mrModels_process_netlist_cb", + "", + TRUE)) +); diff --git a/de/ael/boot.ael b/de/ael/boot.ael new file mode 100644 index 0000000..f8a40ce --- /dev/null +++ b/de/ael/boot.ael @@ -0,0 +1,24 @@ +// ---------------------------------------------------------------------------- +// (setq tab-width 4) +// Place custom AEL code here. +// For example, any custom AEL shared by all components in this library. +// ---------------------------------------------------------------------------- +decl MRMODELS_NAME = designKitRecord[0]; +decl MRMODELS_PATH = designKitRecord[1]; +decl MRMODELS_BOOT = designKitRecord[2]; +decl MRMODELS_VER = designKitRecord[3]; + +decl MRMODELS_DIR_CIRCUIT_AEL = strcat(MRMODELS_PATH, "circuit/ael/" ); +decl MRMODELS_DIR_CIRCUIT_BITMAP = strcat(MRMODELS_PATH, "circuit/bitmaps/" ); +decl MRMODELS_DIR_CIRCUIT_ARTWORK = strcat(MRMODELS_PATH, "circuit/artwork/" ); +decl MRMODELS_DIR_CIRCUIT_MODELS = strcat(MRMODELS_PATH, "circuit/models/" ); +decl MRMODELS_DIR_DE_AEL = strcat(MRMODELS_PATH, "de/ael/" ); +decl MRMODELS_DIR_DRC_RULES = strcat(MRMODELS_PATH, "drc/rules/" ); +decl MRMODELS_DIR_VERILOGA = strcat(MRMODELS_PATH, "veriloga/" ); + +fprintf(stderr, "Loading %s design kit\n", MRMODELS_NAME); + +// ---------------------------------------------------------------------------- +// Load +// ---------------------------------------------------------------------------- +load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "mrmodels_include")); diff --git a/lib_ro.defs b/lib_ro.defs new file mode 100644 index 0000000..158d3c5 --- /dev/null +++ b/lib_ro.defs @@ -0,0 +1,7 @@ +# Library defs for mrModels +# ----------------------------------------------- +DEFINE mrModels ./mrModels +DEFINE mrModels_tech ./mrModels_tech + +ASSIGN mrModels libMode readOnly +ASSIGN mrModels_tech libMode readOnly diff --git a/lib_rw.defs b/lib_rw.defs new file mode 100644 index 0000000..eb98055 --- /dev/null +++ b/lib_rw.defs @@ -0,0 +1,7 @@ +# Library defs for editing "mrModels" +# ----------------------------------------------- +DEFINE mrModels ./mrModels +DEFINE mrModels_tech ./mrModels_tech + +ASSIGN mrModels libMode shared +ASSIGN mrModels_tech libMode shared diff --git a/mrModels/eesof_lib.cfg b/mrModels/eesof_lib.cfg new file mode 100644 index 0000000..9aeaca3 --- /dev/null +++ b/mrModels/eesof_lib.cfg @@ -0,0 +1,17 @@ +DESIGN_KIT_NAME = mrModels +TECH_DESC = mrModels +VERSION = 1.0 +DESIGN_KIT_ROOT = ../ +BOOT_AEL = ../de/ael/boot +ADSLIBCONFIG_DIRECTORY = ../circuit/config +INPUT_DATA_PATH = ../circuit.data;../circuit/models +DDS_TEMPLATES_DIRECTORY = ../circuit/templates +TEMPLATES_DIRECTORY = ../circuit/templates/library +LIB_BROWSER_CTL = ../circuit/records/mrModels_library.ctl +VERILOGA_DIRECTORY = ../veriloga +EXPRESSIONS_DIRECTORY = ../expressions/ael +DOC_DIRECTORY = ../doc +DRC_DIRECTORY = ../drc/rules +NETLIST_EXPORTER_DIRECTORY= ../netlist_exp +BIN_DIRECTORY = ../bin/$SIMARCH$COMPILER_VER +DEFAULTS_DESIGNS=mrModels:mrmodels_include:schematic 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