diff --git a/circuit/ael/mr/mr_opamp.ael b/circuit/ael/mr/mr_opamp.ael new file mode 100644 index 0000000..1c881d3 --- /dev/null +++ b/circuit/ael/mr/mr_opamp.ael @@ -0,0 +1,35 @@ +// (setq tab-width 4) + +create_item( + "mr_opamp", // name + "mr Operation Amplifier", // label + "U", // prefix + 0, // attributes + NULL, // priority + NULL, // icon + + standard_dialog, // dialog name + "", // dialog data + + CmpModelNetlistFmt, // netlist format + "", // netlist data + + NULL, // symbol name (not used since 2011) + NULL, // artwork type (not used since 2011) + NULL, // artwork data (not used since 2011) + + ITEM_PRIMITIVE_EX, // extra attributes + + // ----------------------------------------------------- + // model + // ----------------------------------------------------- + create_parm( + "Model", + "Model instance name", + 0, + "StdFileFormSet", + UNITLESS_UNIT, + prm("StdForm", "va_opamp") + ) + +); diff --git a/circuit/ael/mr/tubes/mr_triode.ael b/circuit/ael/mr/tubes/mr_triode.ael new file mode 100644 index 0000000..3a0447b --- /dev/null +++ b/circuit/ael/mr/tubes/mr_triode.ael @@ -0,0 +1,190 @@ +// (setq tab-width 4) +//decl diode_va_ModelNetlistFmt = "%43?global %;model %t diode_va %b%r%8?%29?%:%30?%p %:%k%?[%1i]%;=%p %;%;%;%e%e"; + +create_item( + "mr_triode", // name + "Verilog-A implementation of Triode", // label + "T", // prefix + 0, // attributes + NULL, // priority + NULL, // icon + + standard_dialog, // dialog name + "", // dialog data + + CmpModelNetlistFmt, // netlist format + "", // netlist data + + ComponentAnnotFmt, // display format string + + NULL, // symbol name (not used since 2011) + NULL, // artwork type (not used since 2011) + NULL, // artwork data (not used since 2011) + + ITEM_PRIMITIVE_EX, // extra attributes + + + // ------------------------------------------------------------------------ + // Model + // ------------------------------------------------------------------------ + create_parm + ( + "Model", + "Model instance name", + 0, + "StdFileFormSet", + UNITLESS_UNIT, + prm("StdForm","mr_triode") + ), + + + // ------------------------------------------------------------------------ + // Kp + // ------------------------------------------------------------------------ + create_parm + ( + "Kp", + "Perveance of the triode", + PARM_NO_DISPLAY | + PARM_OPTIMIZABLE | + PARM_STATISTICAL, + "StdFileFormSet", + UNITLESS_UNIT, + prm("StdForm","") + ), + + // ------------------------------------------------------------------------ + // smallKp + // ------------------------------------------------------------------------ + create_parm + ( + "smallKp", + "Fitting parameter", + PARM_NO_DISPLAY | + PARM_OPTIMIZABLE | + PARM_STATISTICAL, + "StdFileFormSet", + UNITLESS_UNIT, + prm("StdForm","") + ), + + // ------------------------------------------------------------------------ + // Kvb + // ------------------------------------------------------------------------ + create_parm + ( + "kvb", + "fitting parameter", + PARM_NO_DISPLAY | + PARM_OPTIMIZABLE | + PARM_STATISTICAL, + "StdFileFormSet", + UNITLESS_UNIT, + prm("StdForm","") + ), + + // ------------------------------------------------------------------------ + // mu + // ------------------------------------------------------------------------ + create_parm + ( + "mu", + "amplification factor", + PARM_NO_DISPLAY | + PARM_OPTIMIZABLE | + PARM_STATISTICAL, + "StdFileFormSet", + UNITLESS_UNIT, + prm("StdForm","") + ), + + // ------------------------------------------------------------------------ + // X + // ------------------------------------------------------------------------ + create_parm + ( + "X", + "Fitting parameter", + PARM_NO_DISPLAY | + PARM_OPTIMIZABLE | + PARM_STATISTICAL, + "StdFileFormSet", + UNITLESS_UNIT, + prm("StdForm","") + ), + + // ------------------------------------------------------------------------ + // cgc + // ------------------------------------------------------------------------ + create_parm + ( + "cgc", + "Grid-Cathode capacitance", + PARM_NO_DISPLAY | + PARM_OPTIMIZABLE | + PARM_STATISTICAL, + "StdFileFormSet", + CAPACITANCE_UNIT, + prm("StdForm","") + ), + + // ------------------------------------------------------------------------ + // cga + // ------------------------------------------------------------------------ + create_parm + ( + "cga", + "Grid-Anode capacitance", + PARM_NO_DISPLAY | + PARM_OPTIMIZABLE | + PARM_STATISTICAL, + "StdFileFormSet", + CAPACITANCE_UNIT, + prm("StdForm","") + ), + + // ------------------------------------------------------------------------ + // cac + // ------------------------------------------------------------------------ + create_parm + ( + "cac", + "Anode-Cathode capacitance", + PARM_NO_DISPLAY | + PARM_OPTIMIZABLE | + PARM_STATISTICAL, + "StdFileFormSet", + CAPACITANCE_UNIT, + prm("StdForm","") + ), + + // ------------------------------------------------------------------------ + // Tcathode + // ------------------------------------------------------------------------ + create_parm + ( + "Tchatode", + "Cathode temperature (noise analysis only)", + PARM_NO_DISPLAY | + PARM_OPTIMIZABLE | + PARM_STATISTICAL, + "StdFileFormSet", + TEMPERATURE_UNIT, + prm("StdForm","") + ), + + // ------------------------------------------------------------------------ + // gm + // ------------------------------------------------------------------------ + create_parm + ( + "gm", + "Transconductance (noise analysis only)", + PARM_NO_DISPLAY | + PARM_OPTIMIZABLE | + PARM_STATISTICAL, + "StdFileFormSet", + UNITLESS_UNIT, + prm("StdForm","") + ) +); diff --git a/circuit/bitmaps/mr_bjt_npn.bmp b/circuit/bitmaps/mr_bjt_npn.bmp new file mode 100644 index 0000000..a0dec46 Binary files /dev/null and b/circuit/bitmaps/mr_bjt_npn.bmp differ diff --git a/circuit/bitmaps/mr_bjt_pnp.bmp b/circuit/bitmaps/mr_bjt_pnp.bmp new file mode 100644 index 0000000..6f11c95 Binary files /dev/null and b/circuit/bitmaps/mr_bjt_pnp.bmp differ diff --git a/circuit/bitmaps/mr_capacitor.bmp b/circuit/bitmaps/mr_capacitor.bmp new file mode 100644 index 0000000..963e3ff Binary files /dev/null and b/circuit/bitmaps/mr_capacitor.bmp differ diff --git a/circuit/bitmaps/mr_diode.bmp b/circuit/bitmaps/mr_diode.bmp new file mode 100644 index 0000000..defefbb Binary files /dev/null and b/circuit/bitmaps/mr_diode.bmp differ diff --git a/circuit/bitmaps/mr_inductor.bmp b/circuit/bitmaps/mr_inductor.bmp new file mode 100644 index 0000000..0d9ef67 Binary files /dev/null and b/circuit/bitmaps/mr_inductor.bmp differ diff --git a/circuit/bitmaps/mr_jfet_n.bmp b/circuit/bitmaps/mr_jfet_n.bmp new file mode 100644 index 0000000..71b9874 Binary files /dev/null and b/circuit/bitmaps/mr_jfet_n.bmp differ diff --git a/circuit/bitmaps/mr_jfet_p.bmp b/circuit/bitmaps/mr_jfet_p.bmp new file mode 100644 index 0000000..7cf94d8 Binary files /dev/null and b/circuit/bitmaps/mr_jfet_p.bmp differ diff --git a/circuit/bitmaps/mr_opamp.bmp b/circuit/bitmaps/mr_opamp.bmp new file mode 100644 index 0000000..230246e Binary files /dev/null and b/circuit/bitmaps/mr_opamp.bmp differ diff --git a/circuit/bitmaps/mr_resistor.bmp b/circuit/bitmaps/mr_resistor.bmp new file mode 100644 index 0000000..445616a Binary files /dev/null and b/circuit/bitmaps/mr_resistor.bmp differ diff --git a/circuit/bitmaps/mr_zener.bmp b/circuit/bitmaps/mr_zener.bmp new file mode 100644 index 0000000..7aeafb7 Binary files /dev/null and b/circuit/bitmaps/mr_zener.bmp differ diff --git a/circuit/models/jfet/plp/BF862.mod b/circuit/models/jfet/plp/BF862.mod new file mode 100644 index 0000000..6581cfd --- /dev/null +++ b/circuit/models/jfet/plp/BF862.mod @@ -0,0 +1,99 @@ +;(setq tab-width 4) +; BF862 + +define BF862 (D G S) + + ; SOT23 package parasitics + L :Ld D 1 L=1.1 nH + L :Ls S 3 L=1.25 nH + L :Lg G 4 L=0.78 nH + + R :Rg 4 2 R=0.535 + + C :Cds D S C=0.0001 pF + C :Cgs G S C=0.05 pF + C :Cgd G D C=0.201 pF + + + + + JBF862 :J1 1 2 3 ; + + model JBF862 JFET \ + PFET = 0 \ + NFET = 1 \ + Vto = -0.7 \ + Beta = 0.035 \ + Lambda = 0.035 \ + Rd = 5 \ + Rs = 5 \ + Cgs = 3.5E-12 \ + Cgd = 1.8E-12 \ + Kf = 5.0E-16 \ + Af = 1.0 + +; model JBF862 JFET \ +; PFET = 0 \ +; NFET = 1 \ +; Vto = -0.57093 \ +; Beta = 47.800E-3 \ +; Lambda = 37.300E-3 \ +; Rd = 0.8 \ +; Rs = 7.5000 \ +; Cgs = 8.2890E-12 \ +; Cgd = 7.4002E-12 \ +; Pb = 0.5 \ +; Is = 424.60E-12 \ +; M = 0.6015 \ +; Kf = 87.5E-18 \ +; Af = 1 \ +; Fc = 0.5 \ +; Betatce = -0.5 \ +; Vtotc = -2.0000E-3 \ +; Isr = 2.995p \ +; N = 1 \ +; Nr = 2 \ +; Xti = 3 \ +; Alpha = -1.0000E-3 \ +; Vk = 69.97 + +; model JBF862 tom1_va \ +; Af = 1.0 \ +; Alpha = 1.0e-3 \ +; Area = 1.0 \ +; Beta = 47.8e-3 \ +; Betace = -0.5 \ +; Cgs = 8.2890e-12 \ +; Cgd = 7.4002e-12 \ +; Fc = 0.5 \ +; Is = 424.60e-12 \ +; Kf = 87.5e-18 \ +; M = 0.6015 \ +; N = 1.0 \ +; Rd = 0.8 \ +; Rs = 7.5 \ +; Vto = -0.57093 \ +; Vtotc = -2.0e-3 + +; model JBF862 jfetva \ +; NJF = 1 \ +; PJF = 0 \ +; Level = 2 \ +; Vto = -0.57093 ; Rhreshold voltage [V] \ +; Beta = 47.8e-3 ; Transconductancia \ +; Lambda = 37.3e-3 ; Channel-length modulation \ +; Lambda1 = 50.0 ; Channel-length modulation \ +; Rd = 0.8 ; Drain ohmic resistance [ohm] \ +; Rs = 7.5 ; Source ohmic resistance [ohm] \ +; Cgs = 8.2890e-12 ; Zero-bias G-S junction capacitance [F] \ +; Cgd = 7.4002e-12 ; Zero-bias G-D junction capacitance [F] \ +; Pb = 0.5 ; Gate juntion potential [V] \ +; Is = 424.6e-12 ; Gate junction saturation current [A] \ +; B = 1.0 ; Doping tail \ +; M = 0.6015 ; Gate p-n grading coefficient \ +; Kf = 87.5e-18 ; Flicker noise coefficient \ +; Af = 1.0 ; Flicker noise exponent \ +; Fc = 0.5 ; Forward bias depletion cap coefficient \ +; Tnom = 27 + +end BF862 diff --git a/circuit/models/jfet/plp/njfet.modx b/circuit/models/jfet/plp/njfet.modx new file mode 100644 index 0000000..77126d8 --- /dev/null +++ b/circuit/models/jfet/plp/njfet.modx @@ -0,0 +1,52 @@ +*=========================== +*NJFET Pinout: 1=D, 2=G, 3=S +*=========================== + +*NJFET +*Default N-Ch J-FET parameters pkg:TO-92 3,1,2 +.MODEL JNJFET~ NJF() + +*2N4393 +*Motorola 40V 30mA Dep-Mode pkg:TO-18 2,3,1 +.MODEL J2N4393 NJF(VTO=-1.422 BETA=0.009109 LAMBDA=0.006 RD=1 RS=1 ++ CGS=4.06E-12 CGD=4.57E-12 IS=2.052E-13 KF=1.23E-16 ) + +*2N5457 MCE 7-10-95 +*25V 25mA 250 ohm Dep-Mode pkg:TO-92 3,1,2 +.MODEL J2N5457 NJF(VTO=-1.8 BETA=0.00135 LAMBDA=0.001 RD=35 RS=31.5 ++ CGS=2.25E-12 CGD=6E-12 KF=6.5E-17 AF=0.5 ) + +*2N5459 MCE 7-10-95 +*25V 25mA 250 ohm Dep-Mode pkg:TO-92 3,1,2 +.MODEL J2N5459 NJF(VTO=-3 BETA=0.00135 LAMBDA=0.001 RD=35 RS=31.5 ++ CGS=2.25E-12 CGD=6E-12 KF=6.5E-17 AF=0.5 ) + +*2N5484 MCE 7-10-95 +*25V 30mA 175 ohm Dep-Mode pkg:TO-92 3,1,2 +.MODEL J2N5484 NJF(VTO=-1.8 BETA=0.004 LAMBDA=0.01 RD=24.5 RS=22 ++ CGS=2.5E-12 CGD=4E-12 IS=9.48E-15 ) + +*2N5486 MCE +*25V 30mA 28.8ohm Dep-Mode pkg:TO-92 3,1,2 +.MODEL J2N5486 NJF(VTO=-4 BETA=0.0065 LAMBDA=0.00266 RD=4.04 RS=3.63 ++ CGS=2E-12 CGD=3.03E-12 IS=9.48E-15 ) + +*2N5640 MCE +*30V 20mA 35.3ohm Dep-Mode pkg:TO-92 3,1,2 +.MODEL J2N5640 NJF(VTO=-2.5 BETA=0.005 LAMBDA=0.001 RD=4.95 RS=4.45 ++ CGS=1.92E-11 CGD=5.12E-12 IS=5.26E-15 ) + +*2N5668 MCE +*25V 20mA 35.3ohm Dep-Mode pkg:TO-92 3,1,2 +.MODEL J2N5668 NJF(VTO=-2.5 BETA=0.0015 LAMBDA=0.0012 RD=4.95 RS=4.45 ++ CGS=2.35E-12 CGD=4E-12 IS=6.32E-15 ) + +*2N5669 MCE +*25V 20mA 35.3ohm Dep-Mode pkg:TO-92 3,1,2 +.MODEL J2N5669 NJF(VTO=-3.5 BETA=0.0035 LAMBDA=0.0012 RD=4.95 RS=4.45 ++ CGS=2.35E-12 CGD=4E-12 IS=6.32E-15 ) + +*2N5670 MCE +*25V 20mA 35.3ohm Dep-Mode pkg:TO-92 3,1,2 +.MODEL J2N5670 NJF(VTO=-5 BETA=0.0065 LAMBDA=0.0012 RD=4.95 RS=4.45 ++ CGS=2.35E-12 CGD=4E-12 IS=6.32E-15 ) diff --git a/circuit/models/jfet/plp/pjfet.modx b/circuit/models/jfet/plp/pjfet.modx new file mode 100644 index 0000000..b910e4a --- /dev/null +++ b/circuit/models/jfet/plp/pjfet.modx @@ -0,0 +1,12 @@ +*=========================== +*PJFET Pinout: 1=D, 2=G, 3=S +*=========================== + +*PJFET +*Default P-Ch J-FET parameters pkg:TO-92 2,1,3 +.MODEL JPJFET~ PJF() + +*2N5460 +*Motorola Dep-Mode 20V 20mA 35.3ohm pkg:TO-92 2,1,3 +.MODEL J2N5460 PJF(VTO=-3.2 BETA=0.0017 LAMBDA=0.00563 RD=49.4 RS=44.5 ++ CGS=9E-12 CGD=4E-12 IS=1.95E-15 KF=1.104E-17 ) diff --git a/de/ael/boot.ael b/de/ael/boot.ael index 671e291..3a0fe65 100644 --- a/de/ael/boot.ael +++ b/de/ael/boot.ael @@ -36,6 +36,11 @@ else de_error("Failed to open log file!"); } +// ---------------------------------------------------------------------------- +// Load palettes +// ---------------------------------------------------------------------------- +load( strcat( MRMODELS_DIR_DE_AEL, "palette" )); + // ---------------------------------------------------------------------------- // Load // ---------------------------------------------------------------------------- @@ -44,7 +49,9 @@ load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "mrmodels_include")); load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "mr/mr_capacitor" )); load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "mr/mr_inductor" )); load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "mr/mr_resistor" )); +load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "mr/mr_opamp" )); load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "mr/mr_diode" )); +load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "mr/mr_diode_zener" )); load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "mr/mr_bjt" )); load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "mr/mr_jfet" )); diff --git a/de/ael/palette.ael b/de/ael/palette.ael new file mode 100644 index 0000000..736e673 --- /dev/null +++ b/de/ael/palette.ael @@ -0,0 +1,54 @@ +// (setq tab-width 4) +set_design_type(analogRFnet); + +// ------------------------------------------------------------------------------------------------------------------------------ +// mrModels palette +// ------------------------------------------------------------------------------------------------------------------------------ +de_define_library_palette( + "mrModels", // palette library name + SCHEMATIC_WINDOW, // window type (SCHEMATIC_WINDOW, LAYOUT_WINDOW) + "analogRF_net", // design type ("analogRF_net", "sigproc_net") + "mrModels", // palette name + "mrModels", // palette label + 0, // insert position + + // ---------------------------------------------------------------------------------------------------------------------- + // libName cellName viewName compLabel compBitmap + // ---------------------------------------------------------------------------------------------------------------------- + list( "mrModels", "mr_pas_r", "", "Resistor", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_resistor" )), + list( "mrModels", "mr_pas_c", "", "Capacitor", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_capacitor" )), + list( "mrModels", "mr_pas_l", "", "Inductor", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_inductor" )), + + list( "mrModels", "mr_diode", "", "Diode", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_diode" )), + list( "mrModels", "mr_diode_zener", "", "Zener", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_zener" )), + list( "mrModels", "mr_opamp", "", "Operation Amplifier", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_opamp" )), + + list( "mrModels", "mr_bjt_npn", "", "Bipolar Transistor (NPN)", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_bjt_npn" )), + list( "mrModels", "mr_bjt_pnp", "", "Bipolar Transistor (PNP)", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_bjt_pnp" )), + list( "mrModels", "mr_jfet_n", "", "JFET N", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_jfet_n" )), + list( "mrModels", "mr_jfet_p", "", "JFET P", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_jfet_p" )) +); + + + +// ------------------------------------------------------------------------------------------------------------------------------ +// mrModels VerilogA palette +// ------------------------------------------------------------------------------------------------------------------------------ +de_define_library_palette( + "mrModels", // palette library name + SCHEMATIC_WINDOW, // window type (SCHEMATIC_WINDOW,LAYOUT_WINDOW) + "analogRF_net", // design type ("analogRF_net", "sigproc_net") + "mrModels Verilog-A", // palette name + "mrModels VerilogA", // palette label + 1, + + // ---------------------------------------------------------------------------------------------------------------------- + // libName cellName viewName compLabel compBitmap + // ---------------------------------------------------------------------------------------------------------------------- +// list( "mrModels", "mr_opamp", "", "Operation Amplifier", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_opamp" )) +// list( "mrModels", "diode_va", "", "Diode", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_diode" )), +// list( "mrModels", "mrt_nand", "", "NAND", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_diode" )), +// list( "mrModels", "z_res", "", "Resistor", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_resistor" )), +// list( "mrModels", "z_nand", "", "NAND", strcat(MRMODELS_DIR_CIRCUIT_BITMAP, "mr_resistor" )) +); + diff --git a/mrModels/mr_opamp/symbol/master.tag b/mrModels/mr_opamp/symbol/master.tag new file mode 100644 index 0000000..e1024da --- /dev/null +++ b/mrModels/mr_opamp/symbol/master.tag @@ -0,0 +1,2 @@ +-- Master.tag File, Rev:1.0 +symbol.oa diff --git a/mrModels/mr_opamp/symbol/symbol.oa b/mrModels/mr_opamp/symbol/symbol.oa new file mode 100644 index 0000000..e62da61 Binary files /dev/null and b/mrModels/mr_opamp/symbol/symbol.oa differ diff --git a/mrModels/test3/schematic/sch.oa b/mrModels/test3/schematic/sch.oa index 2cc0d4f..aff5ff6 100644 Binary files a/mrModels/test3/schematic/sch.oa and b/mrModels/test3/schematic/sch.oa differ diff --git a/veriloga/mr/bf862.va b/veriloga/mr/bf862.va new file mode 100644 index 0000000..968ecf8 --- /dev/null +++ b/veriloga/mr/bf862.va @@ -0,0 +1,84 @@ +`include "constants.vams" +`include "disciplines.vams" + +module bf862_noise (d, g, s); + inout d, g, s; + electrical d, g, s; + + // ==================== BF862 Core Parameters ==================== + parameter real VTO = -0.70; // Pinch-off voltage (typical) + parameter real BETA = 0.030; // Transconductance parameter (A/V²) + parameter real LAMBDA = 0.035; // Channel length modulation (1/V) + parameter real RD = 5.0; // Drain resistance + parameter real RS = 5.0; // Source resistance + + // Flicker noise + parameter real KF = 5.0e-16; // Flicker noise coefficient (drain current) + parameter real AF = 1.0; + + // Capacitances + parameter real CGS = 3.5e-12; // Gate-Source capacitance + parameter real CGD = 1.8e-12; // Gate-Drain capacitance + + // ==================== Package Parameters (SOT-23) ==================== + parameter real Ld = 1.1e-9; // Drain lead inductance + parameter real Lg = 1.0e-9; // Gate lead inductance + parameter real Ls = 1.25e-9; // Source lead inductance + parameter real Rd_pkg = 0.08; // Drain package resistance + parameter real Rg_pkg = 0.08; // Gate package resistance + parameter real Rs_pkg = 0.08; // Source package resistance + + electrical di, gi, si; // Internal chip nodes + + real vgs, vds, id, gm; + real T; + + analog begin + T = $temperature; + + vgs = V(gi, si); + vds = V(di, si); + + // ==================== JFET Current (Square Law + Early) ==================== + if (vgs > VTO) begin + id = 0; // Cutoff + end else begin + id = BETA * (vgs - VTO)*(vgs - VTO) * (1 + LAMBDA * vds); + end + + // Transconductance (for noise calculation) + gm = 2 * BETA * (vgs - VTO) * (1 + LAMBDA * vds); + + // ==================== Package Parasitics ==================== + V(d, di) <+ Ld * ddt(I(d, di)) + Rd_pkg * I(d, di); + V(g, gi) <+ Lg * ddt(I(g, gi)) + Rg_pkg * I(g, gi); + V(s, si) <+ Ls * ddt(I(s, si)) + Rs_pkg * I(s, si); + + // ==================== Internal Resistances ==================== + V(di, di) <+ RD * I(di); + V(si, si) <+ RS * I(si); + + // ==================== Drain Current ==================== + I(di, si) <+ id; + + // ==================== NOISE SOURCES ==================== + + // 1. Thermal channel noise (dominant in JFETs) + if (gm > 0) begin + I(di, si) <+ white_noise( (4.0/3.0) * `P_K * T * gm , "thermal"); + end + + // 2. Flicker (1/f) noise on drain current + if (KF > 0 && id > 0) begin + I(di, si) <+ flicker_noise(KF * pow(id, AF), 1.0, "flicker"); + end + + // 3. Gate shot noise (very small in JFETs) + I(g, gi) <+ white_noise(2 * `P_Q * 1e-12, "gate_shot"); // ~1pA leakage + + // ==================== Capacitances ==================== + I(gi, si) <+ ddt( CGS * V(gi, si) ); + I(gi, di) <+ ddt( CGD * V(gi, di) ); + + end +endmodule diff --git a/veriloga/mr/mr_opamp.va b/veriloga/mr/mr_opamp.va new file mode 100644 index 0000000..c97d5ab --- /dev/null +++ b/veriloga/mr/mr_opamp.va @@ -0,0 +1,188 @@ +// (setq tab-width 4) +`include "constants.h" +`include "discipline.h" + +`define dB2dec(x) pow(10,x/20) + +`include "mr_diode.va" + +module va_opamp(inp, inn, out, vdd, vss); + inout inp, inn, out, vdd, vss; + electrical inp, inn, out, vdd, vss; + + + // default parameters are for a typical uA741. + + + parameter real Aol = 200e3 from (0 : inf); // Open loop DC gain [V/V] 200e3 + parameter real GBW = 1e6 from (1 : inf); // Gain bandwidth product [Hz] 10e6 + parameter real Rin = 2e6 from [0.01 : inf]; // Differential Input resistance [Ohm] + parameter real Rout = 75 from [0.01 : inf]; // Output resistance [Ohm] + + parameter real VRailp = 1 from [0 : inf]; // Positive output voltage limit [V] + parameter real VRailn = 1 from [0 : inf]; // Negative output voltage limit [V] + + parameter real Vos = 1.0e-3 from [0 : inf]; // Input voltage offset [V] + parameter real Ios = 20.0e-9 from [1e-20 : inf]; // Input offset current [A] + parameter real Ib = 80.0e-9 from [-inf : inf]; // Input bias current [A] + parameter real Cin = 1.4e-12 from [1e-20 : inf]; // Differential input capacitance [F] + + parameter real SRp = 500e3 from [1 : inf]; // Positive slew rate [V/s] + parameter real SRn = 500e3 from [1 : inf]; // Negative slew rate [V/s] + +// parameter real fp2 = 3e6 from [0.01 : inf]; // Secod pole frequency [Hz] + +// parameter real CMR = 90 from [1 : inf]; // Common mode rejection ratio at DC [dB] +// parameter real FCM = 200 from [0.01 : inf]; // Common mode zero corner frequency [Hz] + +// parameter real Io_maxp = 35e-3 from [1e-09 : inf]; // Positive output voltage limit [V] +// parameter real Io_maxn = -35e-3 from [-inf : 0]; // Negative output voltage limit [V] + +// parameter real CScale = 50 from [0 : inf]; // Current limit scaling factor + + electrical net_s1; + electrical net_ref; + electrical net_limp; + electrical net_limn; + + branch (net_s1, net_ref) cur_s1, res_s1, cap_s1; + branch (net_s1, net_limp) res_limp, cap_limp; + branch (net_limn, net_s1) res_limn, cap_limn; + + // --- + real Vin; + + // ------------------------------------------------------------------------- + // first stage (gain, pole, slew) + // ------------------------------------------------------------------------- + real I1; + real Ig1; + real fp1; + real Kp1; + real Rp1; + real Cp1; + + // ------------------------------------------------------------------------- + // simplified diode model parameters + // the diodes used in voltage limit subcircuits + // ------------------------------------------------------------------------- + real is = 10f; // saturation current [A] 10f + real tf = 1u; // forward transit tim [s] + real cjo = 10f; // zero-bias junction capacitance [F] + real phi = 0.7; // built-in junction potential [V] + + // ------------------------------------------------------------------------- + // output voltage limitation + // ------------------------------------------------------------------------- + real Vo_max; // maximum positive output voltage + real Vo_min; // maximum negative output voltage + + real qdp; // positive output voltage limit diode charge + real qdn; // negative output voltage limit diode charge + + analog + begin + @(initial_step) + begin + I1 = 0.01; + fp1 = GBW / Aol; + Cp1 = I1 / SRp; + Rp1 = 1 / (2 * `M_PI * fp1 * Cp1); + Kp1 = Aol / (I1 * Rp1); + + Vo_max = V(vdd) - VRailp; + Vo_min = V(vss) + VRailn; + + $display("\n"); + $display("--------------------------------------"); + $display("GBW = %12.3f Hz", GBW); + $display("SRp = %12.3f V/s", SRp); + $display("--------------------------------------"); + $display("I1 = %12.3f mA", I1 *1e3); + $display("fp1 = %12.3f Hz", fp1); + $display("Cp1 = %12.3f nF", Cp1 *1e9); + $display("Rp1 = %12.3f kOhm", Rp1 /1000); + $display("Kp1 = %12.3f V/V", Kp1); + $display("--------------------------------------"); + $display("Vdd = %12.3f V", V(vdd)); + $display("Vss = %12.3f V", V(vss)); + $display("Vo_max = %12.3f V", Vo_max); + $display("Vo_min = %12.3f V", Vo_min); + end; + + // ----------------------------------------------------------- + // set fix net voltages + // ----------------------------------------------------------- + V(net_ref) <+ (V(vdd) +V(vss)) / 2; + V(net_limp) <+ Vo_max - phi; + V(net_limn) <+ Vo_min + phi; + + // ----------------------------------------------------------- + // input bias and offset currents, offset voltage + // ----------------------------------------------------------- + Vin = V(inp,inn) + Vos; // Input offset voltage + + I(inp) <+ Ib; // Input bias current + I(inn) <+ Ib; // Input bias current + I(inp,inn) <+ Ios / 2; // Input offset current + I(inp,inn) <+ Vin / Rin; // Input stage current + + // ----------------------------------------------------------- + // gain, pole 1, slew + // ----------------------------------------------------------- + I(cur_s1) <+ -I1 * tanh( Kp1 * Vin);; + V(res_s1) <+ Rp1 * I(res_s1); + +/* + if( analysis("ic")) + $display("-> IC"); + else if( analysis("dc")) + $display("-> DC"); + else if( analysis("ac")) + $display("-> AC"); + else if(analysis("static")) + $display("-> STATIC"); + else if( analysis("tran")) + $display("-> TRAN"); + else if( analysis("noise")) + $display("-> NOISE"); + else + $display("-> unknown"); +*/ + + + + if( analysis("ic")) + begin + + V(cap_s1) <+ 0; + V(cap_limp) <+ 0; + V(cap_limn) <+ 0; + end + + else if( analysis("dc")) + I(cap_s1) <+ 0; + else + I(cap_s1) <+ Cp1 * ddt( V(cap_s1)); + + if( !analysis("ac")) + begin + // ----------------------------------------------------------------- + // positive output voltage limiting + // ----------------------------------------------------------------- + qdp = tf * I(res_limp) - 2 * cjo * phi * sqrt(1 -V(cap_limp)/phi); + I(res_limp) <+ is * (limexp( V(res_limp)/$vt) -1); + I(cap_limp) <+ ddt(qdp); + + // ----------------------------------------------------------------- + // negative output voltage limiting + // ----------------------------------------------------------------- + qdn = tf * I(res_limn) - 2 * cjo * phi * sqrt(1 -V(cap_limn)/phi); + I(res_limn) <+ is * (limexp( V(res_limn)/$vt) -1); + I(cap_limn) <+ ddt(qdn); + end; + + V(out) <+ V(cap_s1); + end + +endmodule diff --git a/veriloga/mr/opamps/opamps.va b/veriloga/mr/opamps/opamps.va new file mode 100644 index 0000000..9787d53 --- /dev/null +++ b/veriloga/mr/opamps/opamps.va @@ -0,0 +1,338 @@ +`include "constants.h" +`include "discipline.h" + +// uA741 +// AD822 +// LTC1050 +// TL071 +// NE5534 +// OPA627 + + + +// --------------------------------------------------------- +// uA741 +// --------------------------------------------------------- +module uA741( inp, inn, out, vdd, vss); + inout inp, inn, out, vdd, vss; + electrical inp, inn, out, vdd, vss; + + va_opamp opa( inp, inn, out, vdd, vss); +endmodule + +// --------------------------------------------------------- +// TLC2272 +// --------------------------------------------------------- +module TLC2272( inp, inn, out, vdd, vss); + inout inp, inn, out, vdd, vss; + electrical inp, inn, out, vdd, vss; + + va_opamp #( .Aol(50e3), + .GBW(2.18e6), + .Rin(10e12), + .Rout(140), + + .VRailp(0.25), + .VRailn(0.25), + + .Vos(950e-6), + .Ios(100e-12), + .Ib(100e-12), + .Cin(8), + + .SRp(3.5e6), + .SRn(3.5e6) + ) + opa( inp, inn, out, vdd, vss); +endmodule + + + +// --------------------------------------------------------- +// NJM2068 +// +// .Rout(), +// .Cin(), +// --------------------------------------------------------- +module NJM2068( inp, inn, out, vdd, vss); + inout inp, inn, out, vdd, vss; + electrical inp, inn, out, vdd, vss; + + va_opamp #( .Aol(750e3), + .GBW(27e6), + .Rin(300e3), + + .VRailp(1.5), + .VRailn(1.5), + + .Vos(3e-3), + .Ios(200e-9), + .Ib(1e-6), + + .SRp(6e6), + .SRn(6e6) + ) + opa( inp, inn, out, vdd, vss); +endmodule + +// --------------------------------------------------------- +// NJM4058 (50 mA) +// +// .Rin() +// .Rout() +// .Cin() +// --------------------------------------------------------- +module NJM4058( inp, inn, out, vdd, vss); + inout inp, inn, out, vdd, vss; + electrical inp, inn, out, vdd, vss; + + va_opamp #( .Aol(750e3), + .GBW(15e6), + + .VRailp(1.5), + .VRailn(1.5), + + .Vos(3e-3), + .Ios(200e-9), + .Ib(500e-9), + + .SRp(5e6), + .SRn(5e6) + ) + opa( inp, inn, out, vdd, vss); +endmodule + +// --------------------------------------------------------- +// LT1001 +// +// .Rout() +// .Cin() +// --------------------------------------------------------- +module LT1001( inp, inn, out, vdd, vss); + inout inp, inn, out, vdd, vss; + electrical inp, inn, out, vdd, vss; + + va_opamp #( .Aol(8e5), + .GBW(8e5), + .Rin(80e6), + + .VRailp(1), + .VRailn(1), + + .Vos(60e-6), + .Ios(1e-9), + .Ib(1e-9), + + .SRp(0.25e6), + .SRn(0.25e6) + ) + opa( inp, inn, out, vdd, vss); +endmodule + +// --------------------------------------------------------- +// LT1007 +// +// .Cin() +// --------------------------------------------------------- +module LT1007( inp, inn, out, vdd, vss); + inout inp, inn, out, vdd, vss; + electrical inp, inn, out, vdd, vss; + + va_opamp #( .Aol(20e6), + .GBW(8e6), + .Rin(5e9), + .Rout(70), + + .VRailp(1.5), + .VRailn(1.5), + + .Vos(60e-6), + .Ios(50e-9), + .Ib(50e-9), + + .SRp(2.5e6), + .SRn(2.5e6) + ) + opa( inp, inn, out, vdd, vss); +endmodule + +// --------------------------------------------------------- +// OPA627 +// --------------------------------------------------------- +module OPA627( inp, inn, out, vdd, vss); + inout inp, inn, out, vdd, vss; + electrical inp, inn, out, vdd, vss; + + va_opamp #( .Aol(1e6), + .GBW(16e6), + .Rin(10e13), + .Rout(55), + + .VRailp(2.7), + .VRailn(2.7), + + .Vos(100e-6), + .Ios(1e-12), + .Ib(2e-12), + .Cin(8e-12), + + .SRp(55e6), + .SRn(55e6) + ) + opa( inp, inn, out, vdd, vss); +endmodule + +// --------------------------------------------------------- +// LTC1050 +// --------------------------------------------------------- +module LTC1050( inp, inn, out, vdd, vss); + inout inp, inn, out, vdd, vss; + electrical inp, inn, out, vdd, vss; + + va_opamp #( .Aol(1e6), + .GBW(2.5e6), + .Rin(1e13), + .Rout(50), + + .VRailp(0.15), + .VRailn(0.15), + + .Vos(5e-6), + .Ios(60e-12), + .Ib(30e-12), + .Cin(8e-12), + + .SRp(4e6), + .SRn(4e6) + ) + opa( inp, inn, out, vdd, vss); +endmodule + +// --------------------------------------------------------- +// TL071 +// --------------------------------------------------------- +module TL071( inp, inn, out, vdd, vss); + inout inp, inn, out, vdd, vss; + electrical inp, inn, out, vdd, vss; + + va_opamp #( .Aol(200e3), + .GBW(3e6), + .Rin(1e12), + .VRailp(1.5), + .VRailn(1.5), + .Vos(3e-3), + .Ios(5e-12), + .Ib(65e-12), + .SRp(13e6), + .SRn(13e6) + ) + opa( inp, inn, out, vdd, vss); +endmodule + +// --------------------------------------------------------- +// LM324 +// --------------------------------------------------------- +module LM324( inp, inn, out, vdd, vss); + inout inp, inn, out, vdd, vss; + electrical inp, inn, out, vdd, vss; + + va_opamp #( .Aol(100e3), + .GBW(1e6), + .VRailp(1.5), + .VRailn(0.01), + .Vos(2e-3), + .Ios(5e-9), + .Ib(-45e-9), + .SRp(1.2e6), + .SRn(1.2e6) + ) + opa( inp, inn, out, vdd, vss); +endmodule + +// --------------------------------------------------------- +// NE5534 +// --------------------------------------------------------- +module NE5534( inp, inn, out, vdd, vss); + inout inp, inn, out, vdd, vss; + electrical inp, inn, out, vdd, vss; + + va_opamp #( .Aol(101e3), + .GBW(10e6), + .Rin(100e3), + .Rout(0.3), + + .VRailp(2), + .VRailn(2), + + .Vos(0.5e-3), + .Ios(20e-9), + .Ib(500e-9), + + .SRp(13e6), + .SRn(13e6) + ) + opa( inp, inn, out, vdd, vss); +endmodule + +// --------------------------------------------------------- +// AD822 +// --------------------------------------------------------- +module AD822( inp, inn, out, vdd, vss); + inout inp, inn, out, vdd, vss; + electrical inp, inn, out, vdd, vss; + + va_opamp #( .Aol(1e6), + .GBW(1.8e6), + .Rin(1e13), + .Rout(20), + + .VRailp(0.1), + .VRailn(0.1), + + .Vos(0.5e-3), // 0.5e-3 + .Ios(10e-12), + .Ib(10e-12), + .Cin(0.5e-12), + + .SRp(3e6), + .SRn(3e6) + ) + opa( inp, inn, out, vdd, vss); +endmodule + +/* + parameter real Aol = 200e3 from (0 : inf); // Open loop DC gain [V/V] 200e3 + parameter real GBW = 1e6 from (1 : inf); // Gain bandwidth product [Hz] 10e6 + parameter real Rin = 2e6 from [0.01 : inf]; // Differential Input resistance [Ohm] + parameter real Rout = 75 from [0.01 : inf]; // Output resistance [Ohm] + + parameter real VRailp = 1 from [0 : inf]; // Positive output voltage limit [V] + parameter real VRailn = 1 from [0 : inf]; // Negative output voltage limit [V] + + parameter real Vos = 1.0e-3 from [0 : inf]; // Input voltage offset [V] + parameter real Ios = 20.0e-9 from [1e-20 : inf]; // Input offset current [A] + parameter real Ib = 80.0e-9 from [1e-20 : inf]; // Input bias current [A] + parameter real Cin = 1.4e-12 from [1e-20 : inf]; // Differential input capacitance [F] + + parameter real SRp = 500e3 from [1 : inf]; // Positive slew rate [V/s] + parameter real SRn = 500e3 from [1 : inf]; // Negative slew rate [V/s] + + va_opamp #( .Aol(), + .GBW(), + .Rin(), + .Rout(), + + .VRailp(), + .VRailn(), + + .Vos(), + .Ios(), + .Ib(), + .Cin(), + + .SRp(), + .SRn() + ) + opa( inp, inn, out, vdd, vss); + +*/