Commit Graph

  • efc9995164 Added palette JFET opamp main roka 2026-07-01 13:27:32 +02:00
  • 15c03659da Added BJT models roka 2026-06-30 17:38:40 +02:00
  • 51f17e5c2d Added Diode component with standard and verilog model (diode, led, zener) roka 2026-06-30 17:24:07 +02:00
  • c0c3de344a Fixed capacitor ael file roka 2026-06-30 17:23:00 +02:00
  • 20e94f3dfa Added capacitor and inductor components roka 2026-06-30 16:26:36 +02:00
  • d8edd68938 Added JFET component with 1 model roka 2026-06-30 15:54:18 +02:00
  • 0175490365 Added BJT component with 2 models roka 2026-06-29 20:18:44 +02:00
  • 5c458d5a63 Added resistor component with 3 different simulation model including Verilog-A roka 2026-06-29 10:58:24 +02:00
  • 2562ba7a10 Expand verilog model search path with the folder where the cells are located roka 2026-06-28 13:12:16 +02:00
  • 3957277454 Absolute minimal initial checkin roka 2026-06-27 17:33:25 +02:00