// (setq tab-width 4) `include "constants.h" `include "discipline.h" `define dB2dec(x) pow(10,x/20) `include "mr_diode.va" module va_opamp(inp, inn, out, vdd, vss); inout inp, inn, out, vdd, vss; electrical inp, inn, out, vdd, vss; // default parameters are for a typical uA741. parameter real Aol = 200e3 from (0 : inf); // Open loop DC gain [V/V] 200e3 parameter real GBW = 1e6 from (1 : inf); // Gain bandwidth product [Hz] 10e6 parameter real Rin = 2e6 from [0.01 : inf]; // Differential Input resistance [Ohm] parameter real Rout = 75 from [0.01 : inf]; // Output resistance [Ohm] parameter real VRailp = 1 from [0 : inf]; // Positive output voltage limit [V] parameter real VRailn = 1 from [0 : inf]; // Negative output voltage limit [V] parameter real Vos = 1.0e-3 from [0 : inf]; // Input voltage offset [V] parameter real Ios = 20.0e-9 from [1e-20 : inf]; // Input offset current [A] parameter real Ib = 80.0e-9 from [-inf : inf]; // Input bias current [A] parameter real Cin = 1.4e-12 from [1e-20 : inf]; // Differential input capacitance [F] parameter real SRp = 500e3 from [1 : inf]; // Positive slew rate [V/s] parameter real SRn = 500e3 from [1 : inf]; // Negative slew rate [V/s] // parameter real fp2 = 3e6 from [0.01 : inf]; // Secod pole frequency [Hz] // parameter real CMR = 90 from [1 : inf]; // Common mode rejection ratio at DC [dB] // parameter real FCM = 200 from [0.01 : inf]; // Common mode zero corner frequency [Hz] // parameter real Io_maxp = 35e-3 from [1e-09 : inf]; // Positive output voltage limit [V] // parameter real Io_maxn = -35e-3 from [-inf : 0]; // Negative output voltage limit [V] // parameter real CScale = 50 from [0 : inf]; // Current limit scaling factor electrical net_s1; electrical net_ref; electrical net_limp; electrical net_limn; branch (net_s1, net_ref) cur_s1, res_s1, cap_s1; branch (net_s1, net_limp) res_limp, cap_limp; branch (net_limn, net_s1) res_limn, cap_limn; // --- real Vin; // ------------------------------------------------------------------------- // first stage (gain, pole, slew) // ------------------------------------------------------------------------- real I1; real Ig1; real fp1; real Kp1; real Rp1; real Cp1; // ------------------------------------------------------------------------- // simplified diode model parameters // the diodes used in voltage limit subcircuits // ------------------------------------------------------------------------- real is = 10f; // saturation current [A] 10f real tf = 1u; // forward transit tim [s] real cjo = 10f; // zero-bias junction capacitance [F] real phi = 0.7; // built-in junction potential [V] // ------------------------------------------------------------------------- // output voltage limitation // ------------------------------------------------------------------------- real Vo_max; // maximum positive output voltage real Vo_min; // maximum negative output voltage real qdp; // positive output voltage limit diode charge real qdn; // negative output voltage limit diode charge analog begin @(initial_step) begin I1 = 0.01; fp1 = GBW / Aol; Cp1 = I1 / SRp; Rp1 = 1 / (2 * `M_PI * fp1 * Cp1); Kp1 = Aol / (I1 * Rp1); Vo_max = V(vdd) - VRailp; Vo_min = V(vss) + VRailn; $display("\n"); $display("--------------------------------------"); $display("GBW = %12.3f Hz", GBW); $display("SRp = %12.3f V/s", SRp); $display("--------------------------------------"); $display("I1 = %12.3f mA", I1 *1e3); $display("fp1 = %12.3f Hz", fp1); $display("Cp1 = %12.3f nF", Cp1 *1e9); $display("Rp1 = %12.3f kOhm", Rp1 /1000); $display("Kp1 = %12.3f V/V", Kp1); $display("--------------------------------------"); $display("Vdd = %12.3f V", V(vdd)); $display("Vss = %12.3f V", V(vss)); $display("Vo_max = %12.3f V", Vo_max); $display("Vo_min = %12.3f V", Vo_min); end; // ----------------------------------------------------------- // set fix net voltages // ----------------------------------------------------------- V(net_ref) <+ (V(vdd) +V(vss)) / 2; V(net_limp) <+ Vo_max - phi; V(net_limn) <+ Vo_min + phi; // ----------------------------------------------------------- // input bias and offset currents, offset voltage // ----------------------------------------------------------- Vin = V(inp,inn) + Vos; // Input offset voltage I(inp) <+ Ib; // Input bias current I(inn) <+ Ib; // Input bias current I(inp,inn) <+ Ios / 2; // Input offset current I(inp,inn) <+ Vin / Rin; // Input stage current // ----------------------------------------------------------- // gain, pole 1, slew // ----------------------------------------------------------- I(cur_s1) <+ -I1 * tanh( Kp1 * Vin);; V(res_s1) <+ Rp1 * I(res_s1); /* if( analysis("ic")) $display("-> IC"); else if( analysis("dc")) $display("-> DC"); else if( analysis("ac")) $display("-> AC"); else if(analysis("static")) $display("-> STATIC"); else if( analysis("tran")) $display("-> TRAN"); else if( analysis("noise")) $display("-> NOISE"); else $display("-> unknown"); */ if( analysis("ic")) begin V(cap_s1) <+ 0; V(cap_limp) <+ 0; V(cap_limn) <+ 0; end else if( analysis("dc")) I(cap_s1) <+ 0; else I(cap_s1) <+ Cp1 * ddt( V(cap_s1)); if( !analysis("ac")) begin // ----------------------------------------------------------------- // positive output voltage limiting // ----------------------------------------------------------------- qdp = tf * I(res_limp) - 2 * cjo * phi * sqrt(1 -V(cap_limp)/phi); I(res_limp) <+ is * (limexp( V(res_limp)/$vt) -1); I(cap_limp) <+ ddt(qdp); // ----------------------------------------------------------------- // negative output voltage limiting // ----------------------------------------------------------------- qdn = tf * I(res_limn) - 2 * cjo * phi * sqrt(1 -V(cap_limn)/phi); I(res_limn) <+ is * (limexp( V(res_limn)/$vt) -1); I(cap_limn) <+ ddt(qdn); end; V(out) <+ V(cap_s1); end endmodule