189 lines
7.6 KiB
Plaintext
189 lines
7.6 KiB
Plaintext
// (setq tab-width 4)
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`include "constants.h"
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`include "discipline.h"
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`define dB2dec(x) pow(10,x/20)
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`include "mr_diode.va"
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module va_opamp(inp, inn, out, vdd, vss);
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inout inp, inn, out, vdd, vss;
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electrical inp, inn, out, vdd, vss;
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// default parameters are for a typical uA741.
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parameter real Aol = 200e3 from (0 : inf); // Open loop DC gain [V/V] 200e3
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parameter real GBW = 1e6 from (1 : inf); // Gain bandwidth product [Hz] 10e6
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parameter real Rin = 2e6 from [0.01 : inf]; // Differential Input resistance [Ohm]
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parameter real Rout = 75 from [0.01 : inf]; // Output resistance [Ohm]
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parameter real VRailp = 1 from [0 : inf]; // Positive output voltage limit [V]
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parameter real VRailn = 1 from [0 : inf]; // Negative output voltage limit [V]
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parameter real Vos = 1.0e-3 from [0 : inf]; // Input voltage offset [V]
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parameter real Ios = 20.0e-9 from [1e-20 : inf]; // Input offset current [A]
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parameter real Ib = 80.0e-9 from [-inf : inf]; // Input bias current [A]
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parameter real Cin = 1.4e-12 from [1e-20 : inf]; // Differential input capacitance [F]
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parameter real SRp = 500e3 from [1 : inf]; // Positive slew rate [V/s]
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parameter real SRn = 500e3 from [1 : inf]; // Negative slew rate [V/s]
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// parameter real fp2 = 3e6 from [0.01 : inf]; // Secod pole frequency [Hz]
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// parameter real CMR = 90 from [1 : inf]; // Common mode rejection ratio at DC [dB]
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// parameter real FCM = 200 from [0.01 : inf]; // Common mode zero corner frequency [Hz]
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// parameter real Io_maxp = 35e-3 from [1e-09 : inf]; // Positive output voltage limit [V]
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// parameter real Io_maxn = -35e-3 from [-inf : 0]; // Negative output voltage limit [V]
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// parameter real CScale = 50 from [0 : inf]; // Current limit scaling factor
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electrical net_s1;
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electrical net_ref;
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electrical net_limp;
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electrical net_limn;
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branch (net_s1, net_ref) cur_s1, res_s1, cap_s1;
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branch (net_s1, net_limp) res_limp, cap_limp;
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branch (net_limn, net_s1) res_limn, cap_limn;
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// ---
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real Vin;
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// -------------------------------------------------------------------------
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// first stage (gain, pole, slew)
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// -------------------------------------------------------------------------
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real I1;
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real Ig1;
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real fp1;
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real Kp1;
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real Rp1;
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real Cp1;
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// -------------------------------------------------------------------------
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// simplified diode model parameters
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// the diodes used in voltage limit subcircuits
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// -------------------------------------------------------------------------
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real is = 10f; // saturation current [A] 10f
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real tf = 1u; // forward transit tim [s]
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real cjo = 10f; // zero-bias junction capacitance [F]
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real phi = 0.7; // built-in junction potential [V]
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// -------------------------------------------------------------------------
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// output voltage limitation
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// -------------------------------------------------------------------------
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real Vo_max; // maximum positive output voltage
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real Vo_min; // maximum negative output voltage
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real qdp; // positive output voltage limit diode charge
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real qdn; // negative output voltage limit diode charge
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analog
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begin
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@(initial_step)
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begin
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I1 = 0.01;
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fp1 = GBW / Aol;
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Cp1 = I1 / SRp;
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Rp1 = 1 / (2 * `M_PI * fp1 * Cp1);
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Kp1 = Aol / (I1 * Rp1);
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Vo_max = V(vdd) - VRailp;
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Vo_min = V(vss) + VRailn;
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$display("\n");
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$display("--------------------------------------");
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$display("GBW = %12.3f Hz", GBW);
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$display("SRp = %12.3f V/s", SRp);
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$display("--------------------------------------");
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$display("I1 = %12.3f mA", I1 *1e3);
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$display("fp1 = %12.3f Hz", fp1);
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$display("Cp1 = %12.3f nF", Cp1 *1e9);
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$display("Rp1 = %12.3f kOhm", Rp1 /1000);
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$display("Kp1 = %12.3f V/V", Kp1);
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$display("--------------------------------------");
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$display("Vdd = %12.3f V", V(vdd));
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$display("Vss = %12.3f V", V(vss));
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$display("Vo_max = %12.3f V", Vo_max);
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$display("Vo_min = %12.3f V", Vo_min);
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end;
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// -----------------------------------------------------------
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// set fix net voltages
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// -----------------------------------------------------------
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V(net_ref) <+ (V(vdd) +V(vss)) / 2;
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V(net_limp) <+ Vo_max - phi;
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V(net_limn) <+ Vo_min + phi;
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// -----------------------------------------------------------
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// input bias and offset currents, offset voltage
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// -----------------------------------------------------------
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Vin = V(inp,inn) + Vos; // Input offset voltage
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I(inp) <+ Ib; // Input bias current
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I(inn) <+ Ib; // Input bias current
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I(inp,inn) <+ Ios / 2; // Input offset current
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I(inp,inn) <+ Vin / Rin; // Input stage current
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// -----------------------------------------------------------
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// gain, pole 1, slew
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// -----------------------------------------------------------
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I(cur_s1) <+ -I1 * tanh( Kp1 * Vin);;
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V(res_s1) <+ Rp1 * I(res_s1);
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/*
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if( analysis("ic"))
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$display("-> IC");
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else if( analysis("dc"))
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$display("-> DC");
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else if( analysis("ac"))
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$display("-> AC");
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else if(analysis("static"))
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$display("-> STATIC");
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else if( analysis("tran"))
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$display("-> TRAN");
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else if( analysis("noise"))
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$display("-> NOISE");
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else
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$display("-> unknown");
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*/
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if( analysis("ic"))
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begin
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V(cap_s1) <+ 0;
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V(cap_limp) <+ 0;
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V(cap_limn) <+ 0;
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end
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else if( analysis("dc"))
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I(cap_s1) <+ 0;
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else
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I(cap_s1) <+ Cp1 * ddt( V(cap_s1));
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if( !analysis("ac"))
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begin
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// -----------------------------------------------------------------
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// positive output voltage limiting
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// -----------------------------------------------------------------
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qdp = tf * I(res_limp) - 2 * cjo * phi * sqrt(1 -V(cap_limp)/phi);
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I(res_limp) <+ is * (limexp( V(res_limp)/$vt) -1);
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I(cap_limp) <+ ddt(qdp);
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// -----------------------------------------------------------------
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// negative output voltage limiting
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// -----------------------------------------------------------------
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qdn = tf * I(res_limn) - 2 * cjo * phi * sqrt(1 -V(cap_limn)/phi);
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I(res_limn) <+ is * (limexp( V(res_limn)/$vt) -1);
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I(cap_limn) <+ ddt(qdn);
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end;
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V(out) <+ V(cap_s1);
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end
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endmodule
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