Initial check in

2026-01-03 19:05:48 +01:00
commit 1254878a31
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+// ============================================================================
+// FX2LP SFR Registers at 0x90 - 0x9F
+// ----------------------------------------------------------------------------
+// 0x90 - IOB
+// 0x91 - EXIF
+// 0x92 - MPAGE
+// 0x93 -
+// 0x94 -
+// 0x95 -
+// 0x96 -
+// 0x97 -
+// 0x98 - SCON0
+// 0x99 - SBUF0
+// 0x9A - AUTOPTRH1
+// 0x9B - AUTOPTRL1
+// 0x9C -
+// 0x9D - AUTOPTRH2
+// 0x9E - AUTOPTRL2
+// 0x9F -
+// ============================================================================
+#ifndef FX2REGS_SFR9X_H
+#define FX2REGS_SFR9X_H
+
+sfr	IOB			= 0x90;
+sfr	EXIF		= 0x91;
+sfr	MPAGE		= 0x92;
+sfr	SCON0		= 0x98;
+sfr	SBUF0		= 0x99;
+sfr	AUTOPTRH1	= 0x9A;
+sfr	AUTOPTRL1	= 0x9B;
+sfr	AUTOPTRH2	= 0x9D;
+sfr	AUTOPTRL2	= 0x9E;
+
+// ------------------------------------
+// PortB (0x90)
+// ------------------------------------
+sbit PB0		= 0x90	+0;
+sbit PB1		= 0x90	+1;
+sbit PB2		= 0x90	+2;
+sbit PB3		= 0x90	+3;
+sbit PB4		= 0x90	+4;
+sbit PB5		= 0x90	+5;
+sbit PB6		= 0x90	+6;
+sbit PB7		= 0x90	+7;
+
+// ------------------------------------
+// SCON0 (0x98)
+// ------------------------------------
+sbit RI			= 0x98	+0;
+sbit TI			= 0x98	+1;
+sbit RB8		= 0x98	+2;
+sbit TB8		= 0x98	+3;
+sbit REN		= 0x98	+4;
+sbit SM2		= 0x98	+5;
+sbit SM1		= 0x98	+6;
+sbit SM0		= 0x98	+7;
+
+// ------------------------------------
+// EXIF (0x91)
+// ------------------------------------
+#define bmUSBINT	0x10
+#define bmI2CINT	0x20
+#define bmIE4		0x40
+#define bmIE5		0x80
+
+#endif
+