Initial check in

2026-01-03 19:05:48 +01:00
commit 1254878a31
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+// ============================================================================
+// FX2LP SFR Registers at 0xC0 - 0xCF
+// ----------------------------------------------------------------------------
+// 0xC0 - SCON1
+// 0xC1 - SBUF1
+// 0xC2 -
+// 0xC3 -
+// 0xC4 -
+// 0xC5 -
+// 0xC6 -
+// 0xC7 -
+// 0xC8 - T2CON
+// 0xC9 -
+// 0xCA - RCAP2L
+// 0xCB - RCAP2H
+// 0xCC - TL2
+// 0xCD - TH2
+// 0xCE -
+// 0xCF -
+// ============================================================================
+#ifndef FX2REGS_SFRCX_H
+#define FX2REGS_SFRCX_H
+
+sfr	SCON1	= 0xC0;
+sfr	SBUF1	= 0xC1;
+sfr	T2CON	= 0xC8;
+sfr	RCAP2L	= 0xCA;
+sfr	RCAP2H	= 0xCB;
+sfr	TL2		= 0xCC;
+sfr	TH2		= 0xCD;
+
+
+// ------------------------------------
+// SCON1 (0xC0)
+// ------------------------------------
+sbit RI1	= 0xC0	+0;
+sbit TI1	= 0xC0	+1;
+sbit RB81	= 0xC0	+2;
+sbit TB81	= 0xC0	+3;
+sbit REN1	= 0xC0	+4;
+sbit SM21	= 0xC0	+5;
+sbit SM11	= 0xC0	+6;
+sbit SM01	= 0xC0	+7;
+
+
+// ------------------------------------
+// T2CON (0xC8)
+// ------------------------------------
+sbit CP_RL2	= 0xC8	+0;
+sbit C_T2	= 0xC8	+1;
+sbit TR2	= 0xC8	+2;
+sbit EXEN2	= 0xC8	+3;
+sbit TCLK	= 0xC8	+4;
+sbit RCLK	= 0xC8	+5;
+sbit EXF2	= 0xC8	+6;
+sbit TF2	= 0xC8	+7;
+
+#endif
+