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2026-01-03 19:05:48 +01:00
commit 1254878a31
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+// ============================================================================
+// FX2LP SFR Registers at 0xD0 - 0xDF
+// ----------------------------------------------------------------------------
+// 0xD0 - PSW
+// 0xD1 -
+// 0xD2 -
+// 0xD3 -
+// 0xD4 -
+// 0xD5 -
+// 0xD6 -
+// 0xD7 -
+// 0xD8 - EICON
+// 0xD9 -
+// 0xDA -
+// 0xDB -
+// 0xDC -
+// 0xDD -
+// 0xDE -
+// 0xDF -
+// ============================================================================
+#ifndef FX2REGS_SFRDX_H
+#define FX2REGS_SFRDX_H
+
+sfr	PSW		= 0xD0;
+sfr	EICON	= 0xD8;
+
+// ------------------------------------
+// PSW bits
+// ------------------------------------
+sbit P		= 0xD0	+0;
+sbit FL		= 0xD0	+1;
+sbit OV		= 0xD0	+2;
+sbit RS0	= 0xD0	+3;
+sbit RS1	= 0xD0	+4;
+sbit F0		= 0xD0	+5;
+sbit AC		= 0xD0	+6;
+sbit CY		= 0xD0	+7;
+
+
+// ------------------------------------
+// EICON bits
+// ------------------------------------
+sbit INT6	= 0xD8	+3;
+sbit RESI	= 0xD8	+4;
+sbit ERESI	= 0xD8	+5;
+sbit SMOD1	= 0xD8	+7;
+
+#endif
+