50 lines
975 B
C
50 lines
975 B
C
// ============================================================================
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// FX2LP SFR Registers at 0xD0 - 0xDF
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// ----------------------------------------------------------------------------
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// 0xD0 - PSW
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// 0xD1 -
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// 0xD2 -
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// 0xD3 -
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// 0xD4 -
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// 0xD5 -
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// 0xD6 -
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// 0xD7 -
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// 0xD8 - EICON
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// 0xD9 -
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// 0xDA -
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// 0xDB -
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// 0xDC -
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// 0xDD -
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// 0xDE -
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// 0xDF -
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// ============================================================================
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#ifndef FX2REGS_SFRDX_H
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#define FX2REGS_SFRDX_H
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sfr PSW = 0xD0;
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sfr EICON = 0xD8;
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// ------------------------------------
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// PSW bits
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// ------------------------------------
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sbit P = 0xD0 +0;
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sbit FL = 0xD0 +1;
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sbit OV = 0xD0 +2;
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sbit RS0 = 0xD0 +3;
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sbit RS1 = 0xD0 +4;
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sbit F0 = 0xD0 +5;
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sbit AC = 0xD0 +6;
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sbit CY = 0xD0 +7;
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// ------------------------------------
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// EICON bits
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// ------------------------------------
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sbit INT6 = 0xD8 +3;
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sbit RESI = 0xD8 +4;
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sbit ERESI = 0xD8 +5;
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sbit SMOD1 = 0xD8 +7;
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#endif
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