315 lines
13 KiB
HTML
315 lines
13 KiB
HTML
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"
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<title>GPIF</title>
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<p align="center"><font face="Verdana,Arial" size="2" color="#000000"><B><a name="Overview"></a>16-bit Interface to External Synchronous Cypress FIFO CY7C4625-15AC</B><br></font><font size="2" face="Verdana">
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<font face="Verdana,Arial" size="2" color="#000000"><B>Overview</B> </font>
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<p>
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<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000">The end objective of this example is to be able to perform a bulk loop back function with the external FIFO. The FX2 will write data
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out FD[15:0] to the external FIFO and read data back from FD[15:0] (the outputs from the external FIFO Q[15:0] are also connected to FD[15:0]). The bulk
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transfers can be exercised by using the EZ-USB Control Panel or bulkloop.exe utility supplied with the EZ-USB development kit software.<br>
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<br>
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<font face="verdana, arial, helvetica, sans-serif" size="2" color="#000000"><B><a name="Physical"></a>Hardware
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Connections</B></font>
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<p>
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<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000">This section discusses the definition of the GPIF interconnect which is shown below in Figure 4-1.<br>
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<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000"><br>
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<img src="images/fifo-ic.gif" align="center" width="525" height="240" border="0" ismap usemap="#ic_map"><br>
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Figure 4-1. GPIF Interconnect Diagram<br>
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<br>
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<ul>
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<p><font face="Verdana" size="1"><b>IFCLK ----> WCLK, RCLK</b>
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<br>IFCLK is connected to the write and read clock inputs (WCLK,
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RCLK) of the external FIFO. Data is clocked into the external FIFO
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on every rising edge of WCLK while WEN/ is asserted. Likewise, new
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data is presented on Q[15:0] on every rising edge of RCLK while
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REN/ and OE/ are asserted. The external FIFO can accept an input
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clock frequency of up to 66.7Mhz so it can handle the incoming IFCLK
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frequency (either 30MHz or 48MHz).</font><font face="Verdana,Arial" size="1" color="#000000"> <br> </font><font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000">
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</font></p>
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<p><font face="Verdana" size="1"><b>FD[15:0] <----> D[15:0]
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Q[15:0]</b><br>The GPIF data bus (FD[15:0]) is connected to the
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external FIFO&rsquo;s input data bus (D[15:0]) to allow for
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word wide operations. The output data bus of the external FIFO (Q[15:0])
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is also connected to the GPIF data bus to allow the FX2 to read
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back the data contents. In order to ensure that bus contention will
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never occur, the OE/ signal must be manipulated appropriately.<br> </font></p>
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<p><font face="Verdana" size="1"><b>CTL0 ----> WEN</b><br>CTL0
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is connected to the write enable line (WEN/) of the external FIFO.
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While WEN/ is held low, data is written into the external FIFO on
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every rising edge of WCLK.<br> </font></p>
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<p><font face="Verdana" size="1"><b>CTL1 ----> REN</b><br>CTL1
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is connected to the read enable line (REN/) of the external FIFO.
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While REN/ and OE/ are held low, new data is presented on Q[15:0]
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on every rising edge of RCLK.<br> </font></p>
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<p><font face="Verdana" size="1"><b>CTL2 ----> OE</b><br>CTL2
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is connected to the output enable line (OE/) of the external FIFO.
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While REN/ and OE/ are held low, new data is presented on Q[15:0]
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on every rising edge of RCLK.<br> </font></p>
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<p><font face="Verdana" size="1"><b>RDY0 <---- EF</b><br>RDY0
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is connected to the empty flag (EF/) of the external FIFO. EF/ is
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asserted low if the external FIFO is empty. The GPIF can use this
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to regulate data transfers when reading from the external FIFO.<br> </font></p>
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</ul>
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<p><font face="Verdana" size="1"><b>RDY1 <---- FF</b><br>RDY1
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is connected to the full flag (FF/) of the external FIFO. FF/ is
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asserted low if the external FIFO is full. The GPIF can use this
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to regulate data transfers when writing to the external FIFO.<br> </font></p>
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</ul>
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<p><font face="Verdana" size="1"><b>PA2 ----> RS</b><br>PA2 is
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connected to the reset signal of the external FIFO. PA2 is not part
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of the GPIF interconnect but is still part of the overall system
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design. PA2 is used as an I/O pin to reset the external FIFO to
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a known state before GPIF data transfers commence.<br><br></font></p>
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<p align="left"><font face="Verdana" size="1">The GPIF Designer
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block diagram for the single transaction portion of the FIFO design example is shown below.</font></p>
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<p align="center"> <img src="images/SingleBlkDiag.gif" width="432" height="327" border="0"></p>
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</ul>
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<p align="center"> </p>
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</td>
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<td colspan="1" align="left">
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<p><font face="Verdana" size="1">The assignment of CTLx and RDYn
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lines is optimized for the FX2 56-pin package. The CTLx lines are
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used as input strobes into the external FIFO, and the status outputs
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from the external FIFO (EF and FF) are used to monitor under run
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and over run conditions. The basic rule of thumb is: one should
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never read from an empty FIFO or write to a full FIFO.<br></font><font face="Verdana,Arial" size="1" color="#000000"><br>T</font><font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000">he external FIFO was mounted onto an FX2 development board by using the prototype board supplied with the development
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kit. The external FIFO was placed on a 64-pin TQFP package surface mount adapter (available from Twin Industries at
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<A href="http://www.twinhunter.com" target="resource window">www.twinhunter.com</A>) and piggybacked on top of the prototype board. Figure 9 shows a snapshot of the actual hardware setup.
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For full hardware specifications on the external FIFO, its datasheet can be downloaded from the Cypress website. For a pin-out
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list for the prototype board connection to the FX2 development board and a full schematic for the external FIFO prototype board,
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see the software contents available with this primer.<br>
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</font></p>
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<p align="center">
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<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000"><br><img src="images/setup.jpg" align="center" width="298" height="200" border="0"><br>Figure 9. Shot of Actual Hardware Setup<br><br> </font></p>
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<font face="verdana, arial, helvetica, sans-serif" size="2" color="#000000"><B><a name="DataFlow"></a>Application-specific Data Flow</B><br>
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<p>
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<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000">Now that the GPIF interconnect has been presented, it's important to understand the overall data flow for this design example.
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Endpoint 2 OUT (EP2OUT) is used as the source endpoint for GPIF writes to the external FIFO, and Endpoint 6 IN (EP6IN) is used as the sink endpoint for
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GPIF reads from the external FIFO. Remember that the IN and OUT directions are USB host-centric, therefore EP2OUT contains the data packets sent by the
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USB host (in this case the PC) and EP6IN contains the data packets sent to the USB host. Figures 4-2 and 4-3 show the data flow models for this
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particular example.<br>
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<br>
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<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000"><br>
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<img src="images/flow-out.gif" width="300" height="110" align="center" border="0"><br>
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Figure 4-2. Data Flow Model in the <B>OUT</B> direction
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<br>
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<br>
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<img src="images/flow-in.gif" width="300" height="110" align="center" border="0"><br>
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Figure 4-3. Data Flow Model in the <B>IN</B> direction
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</font>
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<p> </p>
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<ul>
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<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000"><B>Manual mode versus Auto mode</B><br></font>
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</ul>
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<p>
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<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000">FX2 endpoints can basically operate in two modes, Manual (AUTOIN/AUTOOUT=0) or Auto (AUTOIN/AUTOOUT=1). In short, manual mode
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makes the CPU responsible for committing the USB packet to the peripheral domain and vice versa. In order to maximize the USB 2.0 bandwidth, auto mode
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should be used. This allows USB packets to be committed automatically to the peripheral domain and vice versa by removing the CPU from the data path.
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This example demonstrates the use of auto mode.<br><br> </font>
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</ul>
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<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000"><B>Two examples in one</B><br></font>
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</ul>
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<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000">The FIFO example is really two examples in one because two versions of the firmware are discussed. Sections 4.1.4-4.1.6 present
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a version that uses GPIF single transactions to read and write to the external FIFO, which then sets the stage for Sections 4.1.7-4.1.9. Sections
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4.1.7-4.1.9 discuss a version that uses GPIF FIFO transactions and the endpoints in auto mode, thus maximizing the USB 2.0 bandwidth. This two-phased
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approach is in line with the methodology presented in section 3.3, and by understanding the two approaches, the user should be able to discern what it
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takes to move from a simple working example to an example that utilizes the full USB 2.0 bandwidth capabilities of the FX2.<br><br> </font>
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<p align="left"><font face="Verdana" size="1"> </font></p>
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<p align="center"><font face="Verdana" size="1"> </font></p>
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