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44c68d04f9bb30ffaa9cbba283c941dda5b0fcfa
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roka
44c68d04f9
Added the generic include components. It scans model folders to add items to a simulation.
2026-06-26 16:59:08 +02:00
circuit
Added the generic include components. It scans model folders to add items to a simulation.
2026-06-26 16:59:08 +02:00
de
/ael
Added the generic include components. It scans model folders to add items to a simulation.
2026-06-26 16:59:08 +02:00
doc
/VerilogA
Added VerilogA reference manuals
2026-06-26 15:48:29 +02:00
mrModels
Added the generic include components. It scans model folders to add items to a simulation.
2026-06-26 16:59:08 +02:00
mrModels_tech
Added the generic include components. It scans model folders to add items to a simulation.
2026-06-26 16:59:08 +02:00
.gitignore
First absolute minimum check in
2026-06-25 20:20:38 +02:00
lib_ro.defs
First absolute minimum check in
2026-06-25 20:20:38 +02:00
lib_rw.defs
First absolute minimum check in
2026-06-25 20:20:38 +02:00
S
Description
Keysight Advanced Design System
16
MiB
Languages
DM
84.9%
Java
15.1%
