Expand verilog model search path with the folder where the cells are located

Then the verilog model can live with the cell itself

circuit/ael/mrmodels_include.ael

@@ -102,6 +102,7 @@ defun mrModels_process_netlist_cb( cbP, cbData, instH)
 	
 	net = strcat(net, "; veriloga models\n");
 	net	= strcat(net,scan_folder_va(MRMODELS_DIR_VERILOGA));
+	net	= strcat(net,scan_folder_va(MRMODELS_DIR_CELLS));
 	
 	fprintf(stderr, "%s",net);
 	return net;

de/ael/boot.ael

@@ -8,6 +8,7 @@ decl MRMODELS_PATH  = designKitRecord[1];
 decl MRMODELS_BOOT  = designKitRecord[2];
 decl MRMODELS_VER   = designKitRecord[3];
 
+decl MRMODELS_DIR_CELLS             = strcat(MRMODELS_PATH, MRMODELS_NAME, "/"  );
 decl MRMODELS_DIR_CIRCUIT_AEL       = strcat(MRMODELS_PATH, "circuit/ael/"      );
 decl MRMODELS_DIR_CIRCUIT_BITMAP    = strcat(MRMODELS_PATH, "circuit/bitmaps/"  );
 decl MRMODELS_DIR_CIRCUIT_ARTWORK   = strcat(MRMODELS_PATH, "circuit/artwork/"  );
@@ -16,9 +17,30 @@ decl MRMODELS_DIR_DE_AEL            = strcat(MRMODELS_PATH, "de/ael/"
 decl MRMODELS_DIR_DRC_RULES         = strcat(MRMODELS_PATH, "drc/rules/"        );
 decl MRMODELS_DIR_VERILOGA          = strcat(MRMODELS_PATH, "veriloga/"         );
 
-fprintf(stderr, "Loading %s design kit\n", MRMODELS_NAME);
+
+decl logFile = fopen("C:/temp/my_ads_log.txt", "a");   // "a" = append mode
+
+if (logFile != NULL)
+{
+    fprintf(logFile, "Loading %s design kit\n", MRMODELS_NAME);
+    fprintf(logFile, "Path  : %s\n", MRMODELS_PATH);
+    fprintf(logFile, "Boot  : %s\n", MRMODELS_BOOT);
+    fprintf(logFile, "Models: %s\n", MRMODELS_DIR_CELLS);
+
+
+    fclose( logFile);
+}
+
+else
+{
+    de_error("Failed to open log file!");
+}    
 
 // ----------------------------------------------------------------------------
 // Load
 // ----------------------------------------------------------------------------
 load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "mrmodels_include"));
+
+load( strcat( MRMODELS_DIR_CIRCUIT_AEL, "mr/mr_resistor"			));
+
+