Added palette JFET opamp

2026-07-01 13:27:32 +02:00
parent 15c03659da
commit efc9995164
23 changed files with 1061 additions and 0 deletions
@@ -0,0 +1,84 @@
+`include "constants.vams"
+`include "disciplines.vams"
+
+module bf862_noise (d, g, s);
+    inout d, g, s;
+    electrical d, g, s;
+
+    // ==================== BF862 Core Parameters ====================
+    parameter real VTO   = -0.70;       // Pinch-off voltage (typical)
+    parameter real BETA  = 0.030;       // Transconductance parameter (A/V²)
+    parameter real LAMBDA = 0.035;      // Channel length modulation (1/V)
+    parameter real RD    = 5.0;         // Drain resistance
+    parameter real RS    = 5.0;         // Source resistance
+
+    // Flicker noise
+    parameter real KF    = 5.0e-16;     // Flicker noise coefficient (drain current)
+    parameter real AF    = 1.0;
+
+    // Capacitances
+    parameter real CGS   = 3.5e-12;     // Gate-Source capacitance
+    parameter real CGD   = 1.8e-12;     // Gate-Drain capacitance
+
+    // ==================== Package Parameters (SOT-23) ====================
+    parameter real Ld = 1.1e-9;         // Drain lead inductance
+    parameter real Lg = 1.0e-9;         // Gate lead inductance
+    parameter real Ls = 1.25e-9;        // Source lead inductance
+    parameter real Rd_pkg = 0.08;       // Drain package resistance
+    parameter real Rg_pkg = 0.08;       // Gate package resistance
+    parameter real Rs_pkg = 0.08;       // Source package resistance
+
+    electrical di, gi, si;              // Internal chip nodes
+
+    real vgs, vds, id, gm;
+    real T;
+
+    analog begin
+        T = $temperature;
+
+        vgs = V(gi, si);
+        vds = V(di, si);
+
+        // ==================== JFET Current (Square Law + Early) ====================
+        if (vgs > VTO) begin
+            id = 0;                     // Cutoff
+        end else begin
+            id = BETA * (vgs - VTO)*(vgs - VTO) * (1 + LAMBDA * vds);
+        end
+
+        // Transconductance (for noise calculation)
+        gm = 2 * BETA * (vgs - VTO) * (1 + LAMBDA * vds);
+
+        // ==================== Package Parasitics ====================
+        V(d, di) <+ Ld * ddt(I(d, di)) + Rd_pkg * I(d, di);
+        V(g, gi) <+ Lg * ddt(I(g, gi)) + Rg_pkg * I(g, gi);
+        V(s, si) <+ Ls * ddt(I(s, si)) + Rs_pkg * I(s, si);
+
+        // ==================== Internal Resistances ====================
+        V(di, di) <+ RD * I(di);
+        V(si, si) <+ RS * I(si);
+
+        // ==================== Drain Current ====================
+        I(di, si) <+ id;
+
+        // ==================== NOISE SOURCES ====================
+
+        // 1. Thermal channel noise (dominant in JFETs)
+        if (gm > 0) begin
+            I(di, si) <+ white_noise( (4.0/3.0) * `P_K * T * gm , "thermal");
+        end
+
+        // 2. Flicker (1/f) noise on drain current
+        if (KF > 0 && id > 0) begin
+            I(di, si) <+ flicker_noise(KF * pow(id, AF), 1.0, "flicker");
+        end
+
+        // 3. Gate shot noise (very small in JFETs)
+        I(g, gi) <+ white_noise(2 * `P_Q * 1e-12, "gate_shot");   // ~1pA leakage
+
+        // ==================== Capacitances ====================
+        I(gi, si) <+ ddt( CGS * V(gi, si) );
+        I(gi, di) <+ ddt( CGD * V(gi, di) );
+
+    end
+endmodule