85 lines
3.0 KiB
Plaintext
85 lines
3.0 KiB
Plaintext
`include "constants.vams"
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`include "disciplines.vams"
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module bf862_noise (d, g, s);
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inout d, g, s;
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electrical d, g, s;
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// ==================== BF862 Core Parameters ====================
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parameter real VTO = -0.70; // Pinch-off voltage (typical)
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parameter real BETA = 0.030; // Transconductance parameter (A/V²)
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parameter real LAMBDA = 0.035; // Channel length modulation (1/V)
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parameter real RD = 5.0; // Drain resistance
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parameter real RS = 5.0; // Source resistance
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// Flicker noise
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parameter real KF = 5.0e-16; // Flicker noise coefficient (drain current)
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parameter real AF = 1.0;
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// Capacitances
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parameter real CGS = 3.5e-12; // Gate-Source capacitance
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parameter real CGD = 1.8e-12; // Gate-Drain capacitance
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// ==================== Package Parameters (SOT-23) ====================
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parameter real Ld = 1.1e-9; // Drain lead inductance
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parameter real Lg = 1.0e-9; // Gate lead inductance
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parameter real Ls = 1.25e-9; // Source lead inductance
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parameter real Rd_pkg = 0.08; // Drain package resistance
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parameter real Rg_pkg = 0.08; // Gate package resistance
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parameter real Rs_pkg = 0.08; // Source package resistance
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electrical di, gi, si; // Internal chip nodes
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real vgs, vds, id, gm;
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real T;
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analog begin
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T = $temperature;
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vgs = V(gi, si);
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vds = V(di, si);
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// ==================== JFET Current (Square Law + Early) ====================
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if (vgs > VTO) begin
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id = 0; // Cutoff
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end else begin
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id = BETA * (vgs - VTO)*(vgs - VTO) * (1 + LAMBDA * vds);
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end
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// Transconductance (for noise calculation)
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gm = 2 * BETA * (vgs - VTO) * (1 + LAMBDA * vds);
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// ==================== Package Parasitics ====================
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V(d, di) <+ Ld * ddt(I(d, di)) + Rd_pkg * I(d, di);
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V(g, gi) <+ Lg * ddt(I(g, gi)) + Rg_pkg * I(g, gi);
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V(s, si) <+ Ls * ddt(I(s, si)) + Rs_pkg * I(s, si);
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// ==================== Internal Resistances ====================
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V(di, di) <+ RD * I(di);
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V(si, si) <+ RS * I(si);
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// ==================== Drain Current ====================
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I(di, si) <+ id;
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// ==================== NOISE SOURCES ====================
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// 1. Thermal channel noise (dominant in JFETs)
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if (gm > 0) begin
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I(di, si) <+ white_noise( (4.0/3.0) * `P_K * T * gm , "thermal");
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end
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// 2. Flicker (1/f) noise on drain current
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if (KF > 0 && id > 0) begin
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I(di, si) <+ flicker_noise(KF * pow(id, AF), 1.0, "flicker");
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end
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// 3. Gate shot noise (very small in JFETs)
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I(g, gi) <+ white_noise(2 * `P_Q * 1e-12, "gate_shot"); // ~1pA leakage
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// ==================== Capacitances ====================
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I(gi, si) <+ ddt( CGS * V(gi, si) );
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I(gi, di) <+ ddt( CGD * V(gi, di) );
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end
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endmodule
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