Initial check in
This commit is contained in:
@@ -0,0 +1,49 @@
|
||||
### uVision2 Project, (C) Keil Software
|
||||
### Do not modify !
|
||||
|
||||
cExt (*.c)
|
||||
aExt (*.a*; *.src)
|
||||
oExt (*.obj)
|
||||
lExt (*.lib)
|
||||
tExt (*.txt)
|
||||
pExt (*.plm)
|
||||
CppX (*.cpp)
|
||||
DaveTm { 0,0,0,0,0,0,0,0 }
|
||||
|
||||
Target (Target 1), 0x0000 // Tools: 'MCS-51'
|
||||
GRPOPT 1,(Source Group 1),1,0,0
|
||||
|
||||
OPTFFF 1,1,1,0,0,327,327,0,<.\fw.c><fw.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,44,0,0,0,44,0,0,0,70,3,0,0,242,1,0,0 }
|
||||
OPTFFF 1,2,2,218103808,0,3,8,0,<.\dscr.a51><dscr.a51> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,22,0,0,0,22,0,0,0,44,3,0,0,216,1,0,0 }
|
||||
OPTFFF 1,3,1,419430400,0,353,369,0,<.\FX2_to_TI5416_HPI.c><FX2_to_TI5416_HPI.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,0,0,0,0,0,0,0,0,22,3,0,0,194,1,0,0 }
|
||||
OPTFFF 1,4,1,0,0,1,1,0,<.\int0.c><int0.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,88,0,0,0,88,0,0,0,114,3,0,0,12,2,0,0 }
|
||||
OPTFFF 1,5,3,0,0,0,0,0,<D:\Cypress\USB\Target\Lib\FX2\USBJmpTb.OBJ><USBJmpTb.OBJ>
|
||||
OPTFFF 1,6,4,0,0,0,0,0,<D:\Cypress\USB\Target\Lib\FX2\Ezusb.lib><Ezusb.lib>
|
||||
OPTFFF 1,7,1,989855746,0,216,232,0,<.\gpif.c><gpif.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,233,255,255,255,110,0,0,0,110,0,0,0,105,3,0,0,162,1,0,0 }
|
||||
|
||||
|
||||
TARGOPT 1, (Target 1)
|
||||
CLK51=48000000
|
||||
OPTTT 1,1,1,0
|
||||
OPTHX 0,65535,0,0,0
|
||||
OPTLX 120,65,8,<.\>
|
||||
OPTOX 16
|
||||
OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
|
||||
OPTXL 1,1,1,1,1,1,1,0,0
|
||||
OPTFL 1,0,1
|
||||
OPTDL (S8051.DLL)()(DP51.DLL)(-pFX2)(S8051.DLL)()(TP51.DLL)(-pFX2)
|
||||
OPTDBG 49150,0,()()()()()()()()()() ()()()()
|
||||
OPTKEY 0,(MON51)(-S1 -B38400 -O31)
|
||||
OPTWA 0,1,(Tcount)
|
||||
OPTWA 1,1,(EP6BCH)
|
||||
OPTWA 2,1,(EP6BCL)
|
||||
OPTWA 3,1,(GPIFTRIG)
|
||||
OPTWA 4,1,(GPIFTCB1)
|
||||
OPTWA 5,1,(GPIFTCB0)
|
||||
OPTWA 6,1,(EP6FIFOBCH)
|
||||
OPTWA 7,1,(EP6FIFOBCL)
|
||||
OPTDF 0x84
|
||||
OPTLE <>
|
||||
OPTLC <>
|
||||
EndOpt
|
||||
|
||||
@@ -0,0 +1,109 @@
|
||||
### uVision2 Project, (C) Keil Software
|
||||
### Do not modify !
|
||||
|
||||
Target (Target 1), 0x0000 // Tools: 'MCS-51'
|
||||
|
||||
Group (Source Group 1)
|
||||
|
||||
File 1,1,<.\fw.c><fw.c>
|
||||
File 1,2,<.\dscr.a51><dscr.a51>
|
||||
File 1,1,<.\FX2_to_TI5416_HPI.c><FX2_to_TI5416_HPI.c>
|
||||
File 1,1,<.\int0.c><int0.c>
|
||||
File 1,3,<D:\Cypress\USB\Target\Lib\FX2\USBJmpTb.OBJ><USBJmpTb.OBJ>
|
||||
File 1,4,<D:\Cypress\USB\Target\Lib\FX2\Ezusb.lib><Ezusb.lib>
|
||||
File 1,1,<.\gpif.c><gpif.c>
|
||||
|
||||
|
||||
Options 1,0,0 // Target 'Target 1'
|
||||
Device (EZ-USB FX2 (CY7C68XXX))
|
||||
Vendor (Cypress Semiconductor)
|
||||
Cpu (IRAM(0 - 0xFF) XRAM(0 - 0x3FF) CLOCK(48000000) MODDP2)
|
||||
Rgf (REG52.H)
|
||||
Mem ()
|
||||
C ()
|
||||
A ()
|
||||
RL ()
|
||||
OH ()
|
||||
UseEnv=1
|
||||
EnvBin (C:\Keil\C51\BIN\)
|
||||
EnvInc (c:\CYPRESS\USB\Target\Inc\;C:\Keil\C51\INC\)
|
||||
EnvLib (C:\Keil\C51\LIB\)
|
||||
EnvReg ()
|
||||
OrgReg ()
|
||||
TgStat=0
|
||||
OutDir (.\)
|
||||
OutName (FX2_to_TI5416_HPI)
|
||||
GenApp=1
|
||||
GenLib=0
|
||||
GenHex=1
|
||||
Debug=1
|
||||
Browse=0
|
||||
LstDir (.\)
|
||||
HexSel=0
|
||||
MG32K=0
|
||||
RunUsr 0 1 <c:\cypress\usb\bin\hex2bix -i -f 0xC2 -o FX2_to_TI5416_HPI.iic FX2_to_TI5416_HPI.hex>
|
||||
RunUsr 1 0 <>
|
||||
SVCSID <>
|
||||
MODEL5=0
|
||||
RTOS5=0
|
||||
ROMSZ5=2
|
||||
DHOLD5=0
|
||||
XHOLD5=0
|
||||
T51FL=304
|
||||
CBANKS5=0
|
||||
XBANKS5=0
|
||||
RCB51 { 0,0,0,0,0,255,255,0,0 }
|
||||
RXB51 { 0,0,0,0,0,0,0,0,0 }
|
||||
OCM51 { 0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
OCR51 { 0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
IRO51 { 0,0,0,0,0,0,0,0,0 }
|
||||
IRA51 { 0,0,0,0,0,0,1,0,0 }
|
||||
XRA51 { 0,0,0,0,0,0,4,0,0 }
|
||||
C51FL=21597456
|
||||
C51VA=0
|
||||
C51MSC ()
|
||||
C51DEF ()
|
||||
C51UDF ()
|
||||
INCC5 ()
|
||||
AX51FL=4
|
||||
AX51MSC ()
|
||||
AX51SET ()
|
||||
AX51RST ()
|
||||
INCA5 ()
|
||||
IncBld=1
|
||||
AlwaysBuild=0
|
||||
GenAsm=0
|
||||
AsmAsm=0
|
||||
PublicsOnly=0
|
||||
StopCode=3
|
||||
CustArgs ()
|
||||
LibMods ()
|
||||
BankNo=65535
|
||||
LX51FL=288
|
||||
LX51OVL ()
|
||||
LX51MSC ()
|
||||
LX51DWN (16)
|
||||
LX51LFI ()
|
||||
LX51ASN ()
|
||||
LX51RES ()
|
||||
LX51CCL ()
|
||||
LX51UCL ()
|
||||
LX51CSC ()
|
||||
LX51UCS ()
|
||||
LX51COB (0x80-0x0FFF)
|
||||
LX51XDB (0x1000)
|
||||
LX51PDB ()
|
||||
LX51BIB ()
|
||||
LX51DAB ()
|
||||
LX51IDB ()
|
||||
LX51PRC ()
|
||||
LX51STK ()
|
||||
LX51COS ()
|
||||
LX51XDS ()
|
||||
LX51BIS ()
|
||||
LX51DAS ()
|
||||
LX51IDS ()
|
||||
OPTDL (S8051.DLL)()(DP51.DLL)(-pFX2)(S8051.DLL)()(TP51.DLL)(-pFX2)
|
||||
OPTDBG 49150,0,()()()()()()()()()() ()()()()
|
||||
EndOpt
|
||||
|
||||
@@ -0,0 +1,643 @@
|
||||
#pragma NOIV // Do not generate interrupt vectors
|
||||
//-----------------------------------------------------------------------------
|
||||
// File: FX2_to_extsyncFIFO.c
|
||||
// Contents: Hooks required to implement FX2 GPIF interface to a TI
|
||||
// 5416 DSP via it's HPI (Host Port Interface)
|
||||
//
|
||||
// Copyright (c) 2002 Cypress Semiconductor, Inc. All rights reserved
|
||||
//-----------------------------------------------------------------------------
|
||||
#include "fx2.h"
|
||||
#include "fx2regs.h"
|
||||
#include "fx2sdly.h" // SYNCDELAY macro, see Section 15.14 of FX2 Tech.
|
||||
// Ref. Manual for usage details.
|
||||
|
||||
#define HPI_RDY GPIFREADYSTAT & bmBIT0 // RDY0
|
||||
#define LED_ALL (bmBIT0 | bmBIT1 | bmBIT2 | bmBIT3)
|
||||
#define bmEP0BSY 0x01
|
||||
#define bmEP1OUTBSY 0x02
|
||||
#define bmEP1INBSY 0x04
|
||||
|
||||
#define bmHPIC 0x00 // HCNTL[1:0] = 00
|
||||
#define bmHPID_AUTO 0x04 // HCNTL[1:0] = 01
|
||||
#define bmHPIA 0x08 // HCNTL[1:0] = 10
|
||||
#define bmHPID_MANUAL 0x0C // HCNTL[1:0] = 11
|
||||
|
||||
#define GPIFTRIGRD 4
|
||||
|
||||
#define GPIF_EP2 0
|
||||
#define GPIF_EP4 1
|
||||
#define GPIF_EP6 2
|
||||
#define GPIF_EP8 3
|
||||
|
||||
extern BOOL GotSUD; // Received setup data flag
|
||||
extern BOOL Sleep;
|
||||
extern BOOL Rwuen;
|
||||
extern BOOL Selfpwr;
|
||||
|
||||
BYTE Configuration; // Current configuration
|
||||
BYTE AlternateSetting; // Alternate settings
|
||||
static WORD xdata LED_Count = 0;
|
||||
static BYTE xdata LED_Status = 0;
|
||||
BOOL in_enable = FALSE; // flag to enable IN transfers
|
||||
BOOL hpi_int = FALSE; // HPI interrupt flag
|
||||
static WORD xdata Tcount = 0; // transaction count
|
||||
BOOL enum_high_speed = FALSE; // flag to let firmware know FX2 enumerated at high speed
|
||||
static WORD xFIFOBC_IN = 0x0000; // variable that contains EP6FIFOBCH/L value
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Task Dispatcher hooks
|
||||
// The following hooks are called by the task dispatcher.
|
||||
//-----------------------------------------------------------------------------
|
||||
void LED_Off (BYTE LED_Mask);
|
||||
void LED_On (BYTE LED_Mask);
|
||||
void GpifInit ();
|
||||
|
||||
void GPIF_SingleByteWrite (BYTE gdata)
|
||||
{
|
||||
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
|
||||
{
|
||||
;
|
||||
}
|
||||
|
||||
XGPIFSGLDATLX = gdata; // trigger GPIF Single Byte Write transaction
|
||||
}
|
||||
|
||||
|
||||
void TD_Init(void) // Called once at startup
|
||||
{
|
||||
// set the CPU clock to 48MHz
|
||||
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
|
||||
SYNCDELAY;
|
||||
|
||||
EP1OUTCFG = 0xA0; // always OUT, valid, bulk
|
||||
EP1INCFG = 0xA0; // always IN, valid, bulk
|
||||
SYNCDELAY;
|
||||
EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
|
||||
SYNCDELAY;
|
||||
EP4CFG = 0x00; // EP4 not valid
|
||||
SYNCDELAY;
|
||||
EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered
|
||||
SYNCDELAY;
|
||||
EP8CFG = 0x00; // EP8 not valid
|
||||
SYNCDELAY;
|
||||
|
||||
FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
|
||||
SYNCDELAY;
|
||||
FIFORESET = 0x02; // reset EP2 FIFO
|
||||
SYNCDELAY;
|
||||
FIFORESET = 0x06; // reset EP6 FIFO
|
||||
SYNCDELAY;
|
||||
FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
|
||||
SYNCDELAY;
|
||||
|
||||
EP2FIFOCFG = 0x00; // allow core to see zero to one transition of auto out bit
|
||||
SYNCDELAY;
|
||||
EP2FIFOCFG = 0x10; // auto out mode, disable PKTEND zero length send, byte ops
|
||||
SYNCDELAY;
|
||||
EP6FIFOCFG = 0x08; // auto in mode, disable PKTEND zero length send, byte ops
|
||||
SYNCDELAY;
|
||||
EP1OUTBC = 0x00; // arm EP1OUT by writing any value to EP1OUTBC register
|
||||
|
||||
GpifInit (); // initialize GPIF registers
|
||||
|
||||
PORTACFG = bmBIT0; // PA0 takes on INT0/ alternate function
|
||||
OEA |= 0x0C; // initialize PA3 and PA2 port i/o pins as outputs
|
||||
|
||||
EX0 = 1; // Enable INT0/ interrupt
|
||||
IT0 = 1; // Detect INT0/ on falling edge
|
||||
}
|
||||
|
||||
void TD_Poll(void)
|
||||
{
|
||||
|
||||
if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
|
||||
{
|
||||
if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there's a packet in the peripheral domain for EP2
|
||||
{
|
||||
IOA = bmHPID_AUTO; // select HPID register with address auto-increment
|
||||
while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer
|
||||
|
||||
SYNCDELAY;
|
||||
GPIFTCB1 = EP2FIFOBCH; // setup transaction count with number of bytes in the EP2 FIFO
|
||||
SYNCDELAY;
|
||||
GPIFTCB0 = EP2FIFOBCL;
|
||||
SYNCDELAY;
|
||||
GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
|
||||
SYNCDELAY;
|
||||
|
||||
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
|
||||
{
|
||||
;
|
||||
}
|
||||
SYNCDELAY;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
if(in_enable) // if IN transfers are enabled,
|
||||
{
|
||||
if(Tcount) // if Tcount is not zero
|
||||
{
|
||||
if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
|
||||
{
|
||||
if( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full
|
||||
{
|
||||
IOA = bmHPID_AUTO; // select HPID register with address auto-increment
|
||||
while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer
|
||||
|
||||
SYNCDELAY;
|
||||
GPIFTCB1 = MSB(Tcount); // setup transaction count with Tcount value
|
||||
SYNCDELAY;
|
||||
GPIFTCB0 = LSB(Tcount);
|
||||
SYNCDELAY;
|
||||
|
||||
GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6IN
|
||||
SYNCDELAY;
|
||||
|
||||
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
|
||||
{
|
||||
;
|
||||
}
|
||||
|
||||
SYNCDELAY;
|
||||
|
||||
xFIFOBC_IN = ( ( EP6FIFOBCH << 8 ) + EP6FIFOBCL ); // get EP6FIFOBCH/L value
|
||||
|
||||
if( xFIFOBC_IN < 0x0200 ) // if pkt is short,
|
||||
{
|
||||
INPKTEND = 0x06; // force a commit to the host
|
||||
}
|
||||
Tcount = 0; // set Tcount to zero to cease reading from DSP HPI RAM
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(!(EP01STAT & bmEP1OUTBSY))
|
||||
{
|
||||
// handle OUTs to EP1OUT
|
||||
}
|
||||
|
||||
if(!(EP01STAT & bmEP1INBSY))
|
||||
{
|
||||
// handle INs to EP1IN
|
||||
}
|
||||
|
||||
if (hpi_int)
|
||||
{
|
||||
hpi_int = FALSE; // clear HPI interrupt flag
|
||||
EX0 = 1; // enable INT0 interrupt again
|
||||
LED_On (bmBIT1); // turn on LED1 to alert user HPI interrupt occurred
|
||||
}
|
||||
|
||||
// blink LED0 to indicate firmware is running
|
||||
|
||||
if (++LED_Count == 10000)
|
||||
{
|
||||
if (LED_Status)
|
||||
{
|
||||
LED_Off (bmBIT0);
|
||||
LED_Status = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
LED_On (bmBIT0);
|
||||
LED_Status = 1;
|
||||
}
|
||||
LED_Count = 0;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
BOOL TD_Suspend(void) // Called before the device goes into suspend mode
|
||||
{
|
||||
return(TRUE);
|
||||
}
|
||||
|
||||
BOOL TD_Resume(void) // Called after the device resumes
|
||||
{
|
||||
return(TRUE);
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Device Request hooks
|
||||
// The following hooks are called by the end point 0 device request parser.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
BOOL DR_GetDescriptor(void)
|
||||
{
|
||||
return(TRUE);
|
||||
}
|
||||
|
||||
BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
|
||||
{
|
||||
|
||||
if( EZUSB_HIGHSPEED( ) )
|
||||
{ // FX2 enumerated at high speed
|
||||
SYNCDELAY;
|
||||
EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes
|
||||
SYNCDELAY;
|
||||
EP6AUTOINLENL = 0x00;
|
||||
SYNCDELAY;
|
||||
enum_high_speed = TRUE;
|
||||
}
|
||||
else
|
||||
{ // FX2 enumerated at full speed
|
||||
SYNCDELAY;
|
||||
EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes
|
||||
SYNCDELAY;
|
||||
EP6AUTOINLENL = 0x40;
|
||||
SYNCDELAY;
|
||||
enum_high_speed = FALSE;
|
||||
}
|
||||
|
||||
Configuration = SETUPDAT[2];
|
||||
return(TRUE); // Handled by user code
|
||||
}
|
||||
|
||||
BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
|
||||
{
|
||||
EP0BUF[0] = Configuration;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 1;
|
||||
return(TRUE); // Handled by user code
|
||||
}
|
||||
|
||||
BOOL DR_SetInterface(void) // Called when a Set Interface command is received
|
||||
{
|
||||
AlternateSetting = SETUPDAT[2];
|
||||
return(TRUE); // Handled by user code
|
||||
}
|
||||
|
||||
BOOL DR_GetInterface(void) // Called when a Set Interface command is received
|
||||
{
|
||||
EP0BUF[0] = AlternateSetting;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 1;
|
||||
return(TRUE); // Handled by user code
|
||||
}
|
||||
|
||||
BOOL DR_GetStatus(void)
|
||||
{
|
||||
return(TRUE);
|
||||
}
|
||||
|
||||
BOOL DR_ClearFeature(void)
|
||||
{
|
||||
return(TRUE);
|
||||
}
|
||||
|
||||
BOOL DR_SetFeature(void)
|
||||
{
|
||||
return(TRUE);
|
||||
}
|
||||
|
||||
#define VX_B2 0xB2 // turn off LED1
|
||||
#define VX_B3 0xB3 // enable IN transfers
|
||||
#define VX_B4 0xB4 // disable IN transfers
|
||||
#define VX_B5 0xB5 // set Tcount value
|
||||
#define VX_B6 0xB6 // write to HPIC register
|
||||
#define VX_B7 0xB7 // write to HPIA register
|
||||
#define VX_B8 0xB8 // reset EP6 FIFO
|
||||
#define VX_B9 0xB9 // read GPIFTRIG register
|
||||
#define VX_BA 0xBA // read GPIFTC registers
|
||||
|
||||
BOOL DR_VendorCmnd(void)
|
||||
{
|
||||
|
||||
switch (SETUPDAT[1])
|
||||
{
|
||||
case VX_B2: // turn off LED1
|
||||
{
|
||||
LED_Off (bmBIT1);
|
||||
|
||||
*EP0BUF = VX_B2;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 1; // Arm endpoint with # bytes to transfer
|
||||
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
|
||||
break;
|
||||
}
|
||||
case VX_B3: // enable IN transfers
|
||||
{
|
||||
in_enable = TRUE;
|
||||
|
||||
*EP0BUF = VX_B3;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 1;
|
||||
EP0CS |= bmHSNAK;
|
||||
break;
|
||||
}
|
||||
case VX_B4: // disable IN transfers
|
||||
{
|
||||
in_enable = FALSE;
|
||||
|
||||
*EP0BUF = VX_B4;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 1;
|
||||
EP0CS |= bmHSNAK;
|
||||
break;
|
||||
}
|
||||
case VX_B5: // set Tcount value
|
||||
{
|
||||
EP0BCL = 0;
|
||||
while(EP01STAT & bmEP0BSY); // wait until EP0 is available to be accessed by CPU
|
||||
Tcount = (EP0BUF[0] << 8) + EP0BUF[1]; // load transaction count with EP0 values
|
||||
|
||||
break;
|
||||
}
|
||||
case VX_B6: // write to HPIC register
|
||||
{
|
||||
EP0BCL = 0; // re-arm EP0
|
||||
while(EP01STAT & bmEP0BSY); // wait until EP0 is available to be accessed by CPU
|
||||
while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer
|
||||
IOA = bmHPIC; // select HPIC register
|
||||
GPIFWFSELECT = 0x1E; // point to waveforms that write first byte of HPI protocol
|
||||
GPIF_SingleByteWrite(EP0BUF[0]); // write LSB of DSP address
|
||||
GPIFWFSELECT = 0x4E; // point to waveforms that write second byte of HPI protocol
|
||||
GPIF_SingleByteWrite(EP0BUF[1]); // write MSB of DSP address
|
||||
|
||||
break;
|
||||
}
|
||||
case VX_B7: // write to HPIA register
|
||||
{
|
||||
EP0BCL = 0; // re-arm EP0
|
||||
while(EP01STAT & bmEP0BSY); // wait until EP0 is available to be accessed by CPU
|
||||
while(!HPI_RDY); // wait for HPI to complete internal portion of previous transfer
|
||||
IOA = bmHPIA; // select HPIA register
|
||||
GPIFWFSELECT = 0x1E; // point to waveforms that write first byte of HPI protocol
|
||||
GPIF_SingleByteWrite(EP0BUF[0]); // write LSB of DSP address
|
||||
GPIFWFSELECT = 0x4E; // point to waveforms that write second byte of HPI protocol
|
||||
GPIF_SingleByteWrite(EP0BUF[1]); // write MSB of DSP address
|
||||
|
||||
break;
|
||||
}
|
||||
case VX_B8: // reset EP6 FIFO
|
||||
{
|
||||
FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
|
||||
SYNCDELAY;
|
||||
FIFORESET = 0x06; // reset EP6 FIFO
|
||||
SYNCDELAY;
|
||||
FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
|
||||
SYNCDELAY;
|
||||
|
||||
*EP0BUF = VX_B8;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 1;
|
||||
EP0CS |= bmHSNAK;
|
||||
|
||||
break;
|
||||
}
|
||||
case VX_B9: // read GPIFTRIG register
|
||||
{
|
||||
EP0BUF[0] = VX_B9;
|
||||
EP0BUF[1] = GPIFTRIG;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 2;
|
||||
EP0CS |= bmHSNAK;
|
||||
break;
|
||||
}
|
||||
case VX_BA: // read GPIFTC registers
|
||||
{
|
||||
EP0BUF[0] = VX_BA;
|
||||
EP0BUF[1] = GPIFTCB1;
|
||||
EP0BUF[2] = GPIFTCB0;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 3;
|
||||
EP0CS |= bmHSNAK;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
return(TRUE);
|
||||
}
|
||||
|
||||
return(FALSE);
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// USB Interrupt Handlers
|
||||
// The following functions are called by the USB interrupt jump table.
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// Setup Data Available Interrupt Handler
|
||||
void ISR_Sudav(void) interrupt 0
|
||||
{
|
||||
GotSUD = TRUE; // Set flag
|
||||
EZUSB_IRQ_CLEAR();
|
||||
USBIRQ = bmSUDAV; // Clear SUDAV IRQ
|
||||
}
|
||||
|
||||
// Setup Token Interrupt Handler
|
||||
void ISR_Sutok(void) interrupt 0
|
||||
{
|
||||
EZUSB_IRQ_CLEAR();
|
||||
USBIRQ = bmSUTOK; // Clear SUTOK IRQ
|
||||
}
|
||||
|
||||
void ISR_Sof(void) interrupt 0
|
||||
{
|
||||
EZUSB_IRQ_CLEAR();
|
||||
USBIRQ = bmSOF; // Clear SOF IRQ
|
||||
}
|
||||
|
||||
void ISR_Ures(void) interrupt 0
|
||||
{
|
||||
// whenever we get a USB reset, we should revert to full speed mode
|
||||
pConfigDscr = pFullSpeedConfigDscr;
|
||||
((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
|
||||
pOtherConfigDscr = pHighSpeedConfigDscr;
|
||||
((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
|
||||
|
||||
EZUSB_IRQ_CLEAR();
|
||||
USBIRQ = bmURES; // Clear URES IRQ
|
||||
}
|
||||
|
||||
void ISR_Susp(void) interrupt 0
|
||||
{
|
||||
Sleep = TRUE;
|
||||
EZUSB_IRQ_CLEAR();
|
||||
USBIRQ = bmSUSP;
|
||||
}
|
||||
|
||||
void ISR_Highspeed(void) interrupt 0
|
||||
{
|
||||
if (EZUSB_HIGHSPEED())
|
||||
{
|
||||
pConfigDscr = pHighSpeedConfigDscr;
|
||||
((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
|
||||
pOtherConfigDscr = pFullSpeedConfigDscr;
|
||||
((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
|
||||
}
|
||||
|
||||
EZUSB_IRQ_CLEAR();
|
||||
USBIRQ = bmHSGRANT;
|
||||
}
|
||||
void ISR_Ep0ack(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Stub(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep0in(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep0out(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep1in(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep1out(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep2inout(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep4inout(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep6inout(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep8inout(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ibn(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep0pingnak(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep1pingnak(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep2pingnak(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep4pingnak(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep6pingnak(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep8pingnak(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Errorlimit(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep2piderror(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep4piderror(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep6piderror(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep8piderror(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep2pflag(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep4pflag(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep6pflag(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep8pflag(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep2eflag(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep4eflag(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep6eflag(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep8eflag(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep2fflag(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep4fflag(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep6fflag(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_Ep8fflag(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_GpifComplete(void) interrupt 0
|
||||
{
|
||||
}
|
||||
void ISR_GpifWaveform(void) interrupt 0
|
||||
{
|
||||
}
|
||||
|
||||
// ...debug LEDs: accessed via movx reads only ( through CPLD )
|
||||
// it may be worth noting here that the default monitor loads at 0xC000
|
||||
xdata volatile const BYTE LED0_ON _at_ 0x8000;
|
||||
xdata volatile const BYTE LED0_OFF _at_ 0x8100;
|
||||
xdata volatile const BYTE LED1_ON _at_ 0x9000;
|
||||
xdata volatile const BYTE LED1_OFF _at_ 0x9100;
|
||||
xdata volatile const BYTE LED2_ON _at_ 0xA000;
|
||||
xdata volatile const BYTE LED2_OFF _at_ 0xA100;
|
||||
xdata volatile const BYTE LED3_ON _at_ 0xB000;
|
||||
xdata volatile const BYTE LED3_OFF _at_ 0xB100;
|
||||
// use this global variable when (de)asserting debug LEDs...
|
||||
BYTE xdata ledX_rdvar = 0x00;
|
||||
BYTE xdata LED_State = 0;
|
||||
void LED_Off (BYTE LED_Mask)
|
||||
{
|
||||
if (LED_Mask & bmBIT0)
|
||||
{
|
||||
ledX_rdvar = LED0_OFF;
|
||||
LED_State &= ~bmBIT0;
|
||||
}
|
||||
if (LED_Mask & bmBIT1)
|
||||
{
|
||||
ledX_rdvar = LED1_OFF;
|
||||
LED_State &= ~bmBIT1;
|
||||
}
|
||||
if (LED_Mask & bmBIT2)
|
||||
{
|
||||
ledX_rdvar = LED2_OFF;
|
||||
LED_State &= ~bmBIT2;
|
||||
}
|
||||
if (LED_Mask & bmBIT3)
|
||||
{
|
||||
ledX_rdvar = LED3_OFF;
|
||||
LED_State &= ~bmBIT3;
|
||||
}
|
||||
}
|
||||
|
||||
void LED_On (BYTE LED_Mask)
|
||||
{
|
||||
if (LED_Mask & bmBIT0)
|
||||
{
|
||||
ledX_rdvar = LED0_ON;
|
||||
LED_State |= bmBIT0;
|
||||
}
|
||||
if (LED_Mask & bmBIT1)
|
||||
{
|
||||
ledX_rdvar = LED1_ON;
|
||||
LED_State |= bmBIT1;
|
||||
}
|
||||
if (LED_Mask & bmBIT2)
|
||||
{
|
||||
ledX_rdvar = LED2_ON;
|
||||
LED_State |= bmBIT2;
|
||||
}
|
||||
if (LED_Mask & bmBIT3)
|
||||
{
|
||||
ledX_rdvar = LED3_ON;
|
||||
LED_State |= bmBIT3;
|
||||
}
|
||||
}
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,300 @@
|
||||
:0A0EB7000001020203030404050514
|
||||
:10031900E4F513F512F511F510C203C200C202C2C9
|
||||
:1003290001120C447E087F008E238F24752B0875DB
|
||||
:100339002C1275210875221C752908752A4A752DF4
|
||||
:1003490008752E7890E680E030E70E852125852214
|
||||
:1003590026852927852A28800C852925852A268509
|
||||
:100369002127852228EE54E0700302048A751400BF
|
||||
:100379007515807E087F008E168F17C374FA9FFF4C
|
||||
:1003890074089ECF2402CF3400FEE48F0F8E0EF541
|
||||
:100399000DF50CF50BF50AF509F508AF0FAE0EAD25
|
||||
:1003A9000DAC0CAB0BAA0AA909A808C3120DF6508B
|
||||
:1003B9002AE515250BF582E514350AF58374CDF088
|
||||
:1003C900E4FAF9F8E50B2401F50BEA350AF50AE92F
|
||||
:1003D9003509F509E83508F50880C0E4F50BF50A93
|
||||
:1003E900F509F508AF0FAE0EAD0DAC0CAB0BAA0AB3
|
||||
:1003F900A909A808C3120DF65035AE0AAF0BE517C7
|
||||
:100409002FF582E5163EF583E0FDE5152FF582E52A
|
||||
:10041900143EF583EDF0E4FAF9F8EF2401F50BEA5F
|
||||
:100429003EF50AE93509F509E83508F50880B58585
|
||||
:10043900142385152474002480FF740834FFFEC337
|
||||
:10044900E52C9FF52CE52B9EF52BC3E5269FF5267C
|
||||
:10045900E5259EF525C3E5289FF528E5279EF5277F
|
||||
:10046900C3E5229FF522E5219EF521C3E52A9FF5E3
|
||||
:100479002AE5299EF529C3E52E9FF52EE52D9EF542
|
||||
:100489002DD2E843D82090E668E04409F090E65C74
|
||||
:10049900E0443DF0D2AF90E680E020E105D20712BA
|
||||
:1004A90007CD90E680E054F7F0538EF8C20330018F
|
||||
:1004B90005120080C201300329120ECE5024C20356
|
||||
:1004C900120E0720001690E682E030E704E020E1F2
|
||||
:1004D900EF90E682E030E604E020E0E4120AD4126C
|
||||
:0704E9000ED012068A80C745
|
||||
:0104F00022E9
|
||||
:1000800090E6B9E0700302015B14700302020424DD
|
||||
:10009000FE700302029924FB7003020155147003E1
|
||||
:1000A00002014F147003020143147003020149243A
|
||||
:1000B000056003020305120ED2400302031190E60D
|
||||
:1000C000BBE024FE602C14604724FD6016146031F0
|
||||
:1000D00024067065E52390E6B3F0E52490E6B4F0DD
|
||||
:1000E000020311E52B90E6B3F0E52C90E6B4F002A4
|
||||
:1000F0000311E52590E6B3F0E52690E6B4F002039F
|
||||
:1001000011E52790E6B3F0E52890E6B4F00203117C
|
||||
:1001100090E6BAE0FF120DB4AA06A9077B01EA49EE
|
||||
:10012000600DEE90E6B3F0EF90E6B4F002031190AC
|
||||
:10013000E6A0E04401F002031190E6A0E04401F0E3
|
||||
:10014000020311120E9A020311120EC102031112C0
|
||||
:100150000D04020311120E88020311120ED4400383
|
||||
:1001600002031190E6B8E0247F602B14603C240267
|
||||
:1001700060030201FAA200E433FF25E0FFA202E4DB
|
||||
:10018000334F90E740F0E4A3F090E68AF090E68BDE
|
||||
:100190007402F0020311E490E740F0A3F090E68AC5
|
||||
:1001A000F090E68B7402F002031190E6BCE0547EFE
|
||||
:1001B000FF7E00E0D3948040067C007D0180047CBB
|
||||
:1001C000007D00EC4EFEED4F24B7F582740E3EF537
|
||||
:1001D00083E493FF3395E0FEEF24A1FFEE34E68F36
|
||||
:1001E00082F583E0540190E740F0E4A3F090E68AC2
|
||||
:1001F000F090E68B7402F002031190E6A0E0440157
|
||||
:10020000F0020311120ED6400302031190E6B8E08B
|
||||
:1002100024FE601D2402600302031190E6BAE0B4DC
|
||||
:100220000105C20002031190E6A0E04401F00203C0
|
||||
:100230001190E6BAE0705990E6BCE0547EFF7E0073
|
||||
:10024000E0D3948040067C007D0180047C007D002A
|
||||
:10025000EC4EFEED4F24B7F582740E3EF583E49329
|
||||
:10026000FF3395E0FEEF24A1FFEE34E68F82F583A5
|
||||
:10027000E054FEF090E6BCE05480FF131313541FCB
|
||||
:10028000FFE0540F2F90E683F0E04420F0020311CA
|
||||
:1002900090E6A0E04401F08078120ED8507390E60A
|
||||
:1002A000B8E024FE60202402706790E6BAE0B40152
|
||||
:1002B00004D200805C90E6BAE06402605490E6A04C
|
||||
:1002C000E04401F0804B90E6BCE0547EFF7E00E00D
|
||||
:1002D000D3948040067C007D0180047C007D00EC8E
|
||||
:1002E0004EFEED4F24B7F582740E3EF583E493FF86
|
||||
:1002F0003395E0FEEF24A1FFEE34E68F82F583E034
|
||||
:100300004401F0800C1204F1500790E6A0E0440193
|
||||
:08031000F090E6A0E04480F04B
|
||||
:0103180022C2
|
||||
:030033000207FCC5
|
||||
:0407FC0053D8EF32AD
|
||||
:100800001201000200000040470502100000010232
|
||||
:1008100000010A06000200000040010009022E004B
|
||||
:1008200001010080320904000004FF0000000705F8
|
||||
:100830000102000200070581020002000705020212
|
||||
:100840000002000705860200020009022E000101D5
|
||||
:100850000080320904000004FF00000007050102C7
|
||||
:100860004000000705810240000007050202400029
|
||||
:10087000000705860240000004030904100343003A
|
||||
:100880007900700072006500730073006E0345000C
|
||||
:100890005A002D0055005300420020004600580029
|
||||
:1008A000320020004700500049004600200074003C
|
||||
:1008B0006F00200054004900200035003400310052
|
||||
:1008C00036002000480050004900200075007300E9
|
||||
:1008D00069006E00670020004600490046004F0096
|
||||
:1008E00020005400720061006E007300610063001C
|
||||
:0C08F000740069006F006E0073000000CF
|
||||
:1008FC004210B000004110AF00C104C1064210AB61
|
||||
:10090C000000C105021B00004110AD004110AE00FB
|
||||
:0B0EAC00E5BB30E7FB90E6F1EFF02221
|
||||
:100C440090E600E054E74410F000000090E61074D1
|
||||
:100C5400A0F090E611F000000090E612F000000011
|
||||
:100C6400E490E613F000000090E61474E0F0000055
|
||||
:100C740000E490E615F000000090E6047480F000B3
|
||||
:100C840000007402F00000007406F0000000E4F0BC
|
||||
:100C940000000090E618F00000007410F00000005E
|
||||
:100CA40090E61A7408F0000000E490E68DF0120952
|
||||
:0F0CB400D390E6707401F043B20CD2A8D288221C
|
||||
:10068A00E5BB30E73FE5AB20E13A75800490E6F43C
|
||||
:10069A00E070047F0180027F00EF20E0F00000009C
|
||||
:1006AA0090E6ABE090E6D0F000000090E6ACE09077
|
||||
:1006BA00E6D1F0000000E4F5BB000000E5BB30E73E
|
||||
:1006CA00FB0000003004739010ABE07002A3E060FE
|
||||
:1006DA0069E5BB30E764E5AC20E05F75800490E62D
|
||||
:1006EA00F4E070047F0180027F00EF20E0F0000058
|
||||
:1006FA00009010ABE090E6D0F00000009010ACE063
|
||||
:10070A0090E6D1F000000075BB06000000E5BB30A2
|
||||
:10071A00E7FB00000090E6AFE0FE90E6B0E07C0068
|
||||
:10072A002400F51CEC3EF51BC39402500690E648E3
|
||||
:10073A007406F0E49010ABF0A3F0300609C206D2BA
|
||||
:10074A00A87F02120A8F9010B0E475F001120DE032
|
||||
:10075A00AFF0FEBE2727BF10249010AFE0600C7FD9
|
||||
:10076A0001120788E49010AFF0800B7F01120A8F04
|
||||
:0E077A009010AF7401F0E49010B0F0A3F022E4
|
||||
:020ECE00D3222D
|
||||
:020ED000D3222B
|
||||
:020ED200D32229
|
||||
:100D040090E680E030E71800000090E6247402F0DA
|
||||
:100D1400000000E490E625F0000000D205801600F3
|
||||
:100D24000000E490E624F000000090E6257440F012
|
||||
:0D0D3400000000C20590E6BAE0F51DD322D4
|
||||
:100E880090E740E51DF0E490E68AF090E68B04F0E8
|
||||
:020E9800D32263
|
||||
:080EC10090E6BAE0F51AD32215
|
||||
:100E9A0090E740E51AF0E490E68AF090E68B04F0D9
|
||||
:020EAA00D32251
|
||||
:020ED400D32227
|
||||
:020ED600D32225
|
||||
:020ED800D32223
|
||||
:1004F10090E6B9E0244EB409004003020686900557
|
||||
:1005010006F828287302052102054002055C020550
|
||||
:100511007802059A0205D602061102063E02065C21
|
||||
:100521007F0212078890E74074B2F0E490E68AF007
|
||||
:1005310090E68B04F090E6A0E04480F0020688D2B9
|
||||
:100541000490E74074B3F0E490E68AF090E68B04FF
|
||||
:10055100F090E6A0E04480F0020688C20490E740F3
|
||||
:1005610074B4F0E490E68AF090E68B04F090E6A093
|
||||
:10057100E04480F0020688E490E68BF0E5BA20E0E2
|
||||
:10058100FB90E740E0FEA3E07C0024009010ACF07B
|
||||
:10059100EC3E9010ABF0020688E490E68BF0E5BAF1
|
||||
:1005A10020E0FB90E6F4E070047F0180027F00EF21
|
||||
:1005B10020E0F0E4F58090E6C0741EF090E740E0A2
|
||||
:1005C100FF120EAC90E6C0744EF090E741E0FF12CE
|
||||
:1005D1000EAC020688E490E68BF0E5BA20E0FB90D1
|
||||
:1005E100E6F4E070047F0180027F00EF20E0F07507
|
||||
:1005F100800890E6C0741EF090E740E0FF120EAC58
|
||||
:1006010090E6C0744EF090E741E0FF120EAC8077A7
|
||||
:1006110090E6047480F00000007406F0000000E42D
|
||||
:10062100F000000090E74074B8F0E490E68AF090A2
|
||||
:10063100E68B04F090E6A0E04480F0804A90E74029
|
||||
:1006410074B9F0A3E5BBF0E490E68AF090E68B7410
|
||||
:1006510002F090E6A0E04480F0802C90E74074BA6C
|
||||
:10066100F090E6D0E090E741F090E6D1E090E742EB
|
||||
:10067100F0E490E68AF090E68B7403F090E6A0E057
|
||||
:090681004480F08002D322C32260
|
||||
:100E2C00C0E0C083C082D2015391EF90E65D7401A3
|
||||
:080E3C00F0D082D083D0E03237
|
||||
:100E5C00C0E0C083C0825391EF90E65D7404F0D083
|
||||
:060E6C0082D083D0E032C9
|
||||
:100E7200C0E0C083C0825391EF90E65D7402F0D06F
|
||||
:060E820082D083D0E032B3
|
||||
:100D7E00C0E0C083C082852925852A2685268285E6
|
||||
:100D8E002583A37402F08521278522288528828554
|
||||
:100D9E002783A37407F05391EF90E65D7410F0D0A3
|
||||
:060DAE0082D083D0E03288
|
||||
:100E4400C0E0C083C082D2035391EF90E65D740882
|
||||
:080E5400F0D082D083D0E0321F
|
||||
:100D4100C0E0C083C08290E680E030E720852125A5
|
||||
:100D5100852226852682852583A37402F08529278D
|
||||
:100D6100852A28852882852783A37407F05391EF6C
|
||||
:0D0D710090E65D7420F0D082D083D0E03297
|
||||
:010EDA0032E5
|
||||
:010EDB0032E4
|
||||
:010EDC0032E3
|
||||
:010EDD0032E2
|
||||
:010EDE0032E1
|
||||
:010EDF0032E0
|
||||
:010EE00032DF
|
||||
:010EE10032DE
|
||||
:010EE20032DD
|
||||
:010EE30032DC
|
||||
:010EE40032DB
|
||||
:010EE50032DA
|
||||
:010EE60032D9
|
||||
:010EE70032D8
|
||||
:010EE80032D7
|
||||
:010EE90032D6
|
||||
:010EEA0032D5
|
||||
:010EEB0032D4
|
||||
:010EEC0032D3
|
||||
:010EED0032D2
|
||||
:010EEE0032D1
|
||||
:010EEF0032D0
|
||||
:010EF00032CF
|
||||
:010EF10032CE
|
||||
:010EF20032CD
|
||||
:010EF30032CC
|
||||
:010EF40032CB
|
||||
:010EF50032CA
|
||||
:010EF60032C9
|
||||
:010EF70032C8
|
||||
:010EF80032C7
|
||||
:010EF90032C6
|
||||
:010EFA0032C5
|
||||
:010EFB0032C4
|
||||
:010EFC0032C3
|
||||
:010EFD0032C2
|
||||
:10078800EF30E00D908100E09010ADF0A3E054FE52
|
||||
:10079800F0EF30E10D909100E09010ADF0A3E0543F
|
||||
:1007A800FDF0EF30E20D90A100E09010ADF0A3E075
|
||||
:1007B80054FBF0EF30E30D90B100E09010ADF0A3E2
|
||||
:0507C800E054F7F022EF
|
||||
:100A8F00EF30E00D908000E09010ADF0A3E0440156
|
||||
:100A9F00F0EF30E10D909000E09010ADF0A3E04446
|
||||
:100AAF0002F0EF30E20D90A000E09010ADF0A3E067
|
||||
:100ABF004404F0EF30E30D90B000E09010ADF0A3E0
|
||||
:050ACF00E04408F022E4
|
||||
:03000300020EC921
|
||||
:050EC900D206C2A832B0
|
||||
:03004300020B00AD
|
||||
:03005300020B009D
|
||||
:100B0000020E2C00020E7200020E5C00020E440067
|
||||
:100B1000020D7E00020D4100020EDA00020EDB0023
|
||||
:100B2000020EDC00020EDD00020EDE00020EDF000F
|
||||
:100B3000020EE000020EE100020EE200020EE300EF
|
||||
:100B4000020EE400020EDB00020EE500020EE600DB
|
||||
:100B5000020EE700020EE800020EE900020EEA00B3
|
||||
:100B6000020EEB00020EDB00020EDB00020EDB00C9
|
||||
:100B7000020EEC00020EED00020EEE00020EEF007F
|
||||
:100B8000020EF000020EF100020EF200020EF3005F
|
||||
:100B9000020EF400020EF500020EF600020EF7003F
|
||||
:100BA000020EF800020EF900020EFA00020EFB001F
|
||||
:080BB000020EFC00020EFD0024
|
||||
:100AD40090E682E030E004E020E60B90E682E0302D
|
||||
:100AE400E119E030E71590E680E04401F07F147EE0
|
||||
:0C0AF40000120CC390E680E054FEF022DB
|
||||
:100E070090E682E044C0F090E681F043870100005D
|
||||
:040E170000000022B5
|
||||
:1007CD0030070990E680E0440AF0800790E680E06B
|
||||
:1007DD004408F07FDC7E05120CC390E65D74FFF0DB
|
||||
:0F07ED0090E65FF05391EF90E680E054F7F02232
|
||||
:020DB400A9078D
|
||||
:100DB600AE2DAF2E8F828E83A3E064037017AD0134
|
||||
:100DC60019ED7001228F828E83E07C002FFDEC3EB0
|
||||
:090DD600FEAF0580DF7E007F0006
|
||||
:010DDF0022F1
|
||||
:100CC3008E188F1990E600E05418700DE518C313C1
|
||||
:100CD300F518E51913F519801590E600E05418FF8F
|
||||
:100CE300BF100BE51925E0F519E51833F518E519DB
|
||||
:100CF3001519AE18700215184E6005120E1B80EE02
|
||||
:010D030022CD
|
||||
:100E1B007400F58690FDA57C05A3E582458370F9EA
|
||||
:010E2B0022A4
|
||||
:10091C006080100001013F0101010107000201008C
|
||||
:10092C0000000000020002020202020700000000A8
|
||||
:10093C000000003F01013F0101010107000201001D
|
||||
:10094C00000000000604060606060607000000006C
|
||||
:10095C000000003F01010101013801070000020005
|
||||
:10096C00020100000301070507070707000000004C
|
||||
:10097C00002D003F010101010138010700020402B2
|
||||
:10098C00040100000200060406070707000000002F
|
||||
:10099C00002D003F602410870000000000000000C4
|
||||
:1009AC00000000000000000000000000000000003B
|
||||
:1009BC00000000000000000000000000471080E074
|
||||
:0609CC00000007CE4E0002
|
||||
:1009D30090E60174CEF090E6F574FFF0901080E09D
|
||||
:1009E30090E6F3F0901081E090E6C3F0901082E07F
|
||||
:1009F30090E6C1F0901083E090E6C2F0901085E09D
|
||||
:100A030090E6C0F0901086E090E6F4F075AF0774BE
|
||||
:100A130010F59A7400F59B759DE4E4F59EFF90E64E
|
||||
:100A23007BE090E67CF00FBF80F490E67174FFF0FA
|
||||
:100A3300F5B490E672E04480F043B680000000E431
|
||||
:100A430090E6C4F000000090E6C5F0901087E090B7
|
||||
:100A5300E6C6F0901088E090E6C7F0901089E09029
|
||||
:100A6300E6C8F090108AE090E6C9F090108BE09011
|
||||
:100A7300E6CAF090108CE090E6CBF090108DE090F9
|
||||
:0B0A8300E6CCF090108EE090E6CDF085
|
||||
:010A8E002245
|
||||
:03000000020BB838
|
||||
:0C0BB800787FE4F6D8FD75812E020BFF5B
|
||||
:100DE000C5F0F8A3E028F0C5F0F8E582158270029E
|
||||
:060DF0001583E038F0223B
|
||||
:100DF600EB9FF5F0EA9E42F0E99D42F0E89C45F053
|
||||
:010E060022C9
|
||||
:100BC400020319E493A3F8E493A34003F68001F22B
|
||||
:100BD40008DFF48029E493A3F85407240CC8C33332
|
||||
:100BE400C4540F4420C8834004F456800146F6DF01
|
||||
:100BF400E4800B01020408102040809008FCE47E8D
|
||||
:100C0400019360BCA3FF543F30E509541FFEE493F5
|
||||
:100C1400A360010ECF54C025E060A840B8E493A3BC
|
||||
:100C2400FAE493A3F8E493A3C8C582C8CAC583CAE7
|
||||
:100C3400F0A3C8C582C8CAC583CADFE9DEE780BE9F
|
||||
:0109D2000024
|
||||
:00000001FF
|
||||
Binary file not shown.
@@ -0,0 +1,21 @@
|
||||
<html>
|
||||
<head>
|
||||
<title>You need a browser that supports frame to veiw this page.</title>
|
||||
<meta name="GENERATOR" content="Namo WebEditor v5.0">
|
||||
|
||||
<meta name="description" content="Makes a banner frame in the top, menu frame in the left, and main frame in the right. Hyperlinks in the banner frame are targeted to the menu frame.">
|
||||
</head>
|
||||
<frameset rows="60, 78%" cols="1*" border="0">
|
||||
<frame name="banner" scrolling="no" marginwidth="10" marginheight="14" namo_target_frame="contents" src="app_note/Caption.htm">
|
||||
<frameset rows="1*" cols="200, 80%">
|
||||
<frame name="contents" scrolling="auto" marginwidth="10" marginheight="14" namo_target_frame="detail" src="app_note/mainmenu.htm">
|
||||
<frame name="detail" scrolling="yes" marginwidth="10" marginheight="14" src="app_note/intro.htm">
|
||||
</frameset>
|
||||
<noframes>
|
||||
<body bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000">
|
||||
|
||||
<p>You need a browser that supports frame to veiw this page.</p>
|
||||
</body>
|
||||
</noframes>
|
||||
</frameset>
|
||||
</html>
|
||||
@@ -0,0 +1,24 @@
|
||||
<html>
|
||||
|
||||
<head>
|
||||
<title>Index</title>
|
||||
<base target="contents"></head>
|
||||
|
||||
<body bgcolor="white" text="black" link="blue" vlink="purple" alink="red">
|
||||
<table cellpadding="0" cellspacing="0" width="100%" align="center">
|
||||
<tr>
|
||||
<td width="198" height="26">
|
||||
<p align="center"><span style="font-size:12pt;"><font face="Verdana"> </font></span></p>
|
||||
</td>
|
||||
<td width="441" height="26">
|
||||
<p align="center"><strong><samp><font color="black" face="Verdana"><span style="font-size:12pt;">DSP
|
||||
DESIGN EXAMPLE</span></font></samp></strong></p>
|
||||
</td>
|
||||
<td width="189" height="26">
|
||||
<p align="right"><strong><samp><font color="#0000CC" face="Verdana"><span style="font-size:12pt;"><img src="images/smalllogo.gif" width="95" height="30" border="0"> </span></font></samp></strong></p>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<hr></body>
|
||||
|
||||
</html>
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
After Width: | Height: | Size: 31 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 31 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 30 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 29 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 18 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 135 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 33 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 68 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 98 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 48 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 130 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 20 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 30 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 4.5 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 24 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 16 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 725 B |
Binary file not shown.
|
After Width: | Height: | Size: 725 B |
Binary file not shown.
|
After Width: | Height: | Size: 13 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 12 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 5.0 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 8.2 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 5.0 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 7.2 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 2.0 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 6.1 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 6.3 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 6.1 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 9.7 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 7.1 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 7.0 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 9.0 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 15 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 36 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 1.6 KiB |
@@ -0,0 +1,266 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"
|
||||
"http://www.w3.org/TR/1999/REC-html401-19991224/loose.dtd">
|
||||
<html lang="en">
|
||||
<head>
|
||||
<meta http-equiv="content-type" content="text/html; charset=iso-8859-1">
|
||||
<title>GPIF</title>
|
||||
<meta name="generator" content="BBEdit 6.0">
|
||||
<script language="Javascript">
|
||||
<!--
|
||||
function changeGPIF(html)
|
||||
{
|
||||
descriptionGPIF.innerHTML=html
|
||||
}
|
||||
//-->
|
||||
</script>
|
||||
</head>
|
||||
<body bgcolor="#FFFFFF">
|
||||
|
||||
|
||||
<table border="0" cellpadding="0" cellspacing="0" width="98%" align="center">
|
||||
<tr valign="top">
|
||||
<td colspan="1" align="left">
|
||||
<p align="center"><font face="Verdana,Arial" size="2" color="#000000"><B><a name="Overview"></a></B></font><font face="verdana, arial, helvetica, sans-serif" size="2" color="#000000"><B>Interfacing to a TI 5416 DSP via the Host Port Interface (HPI)</B><br></font><font size="2" face="Verdana">
|
||||
<br></font>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr valign="top">
|
||||
<td colspan="1" align="left">
|
||||
<font face="verdana, arial, helvetica, sans-serif" size="2" color="#000000"><B>Background on the TI 5416 DSP and Overview</B></font><font face="Verdana,Arial" size="2" color="#000000"> </font>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr valign="top">
|
||||
<td colspan="1" align="left">
|
||||
|
||||
<p>
|
||||
<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000">The Texas Instruments TI 5416 fixed-point DSP finds its home in many mid range DSP applications. It is supported by the TI 5416 DSK, which proved very
|
||||
attractive as the choice for this example because it exposes the HPI on one of the three expansion headers of the DSK board. The HPI allows a host processor
|
||||
access to the internal RAM of the 5416, thereby enabling the transfer of data between the host processor and the 5416.<br>
|
||||
<br>
|
||||
By interfacing the FX2 to the 5416's HPI, this allows developers of embedded audio and imaging applications to easily add a high
|
||||
speed USB port. The FX2 can also bootload the 5416 DSP code via the HPI. In this example, users will be shown how to interface
|
||||
the FX2 to the 5416 HPI using the GPIF to accomplish two things: 1) read and write to the internal RAM block of the 5416, and
|
||||
2) bootload the 5416 by downloading the DSP code from the PC. For detailed information about how the HPI block of the 5416
|
||||
works, please refer to the TI documentation mentioned in the references section at the end of this document. Note that the
|
||||
information presented here may also be applicable to other TI DSPs that expose the HPI port.<br>
|
||||
<br>
|
||||
</font>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr valign="top">
|
||||
<td colspan="1" align="left">
|
||||
<font face="verdana, arial, helvetica, sans-serif" size="2" color="#000000"><B><a name="Physical"></a>Hardware
|
||||
Connections</B></font>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr valign="top">
|
||||
<td colspan="1" align="left">
|
||||
|
||||
<p>
|
||||
<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000">This section discusses the definition of the GPIF interconnect which is shown below in Figure 13.<br>
|
||||
</font>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr valign="top">
|
||||
<td colspan="1" align="center">
|
||||
|
||||
<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000"><br>
|
||||
<img src="images/dsp-ic.gif" align="center" width="525" height="300" border="0" ismap usemap="#ic_map"><br>
|
||||
Figure 13. GPIF Interconnect to TI 5416 HPI<br>
|
||||
<br>
|
||||
</font>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr valign="top">
|
||||
<td colspan="1" align="left">
|
||||
<ul>
|
||||
<p><font face="Verdana" size="1"><b>PA3, PA2 ----> HCNTL[1:0]</b><br>Port
|
||||
pins PA3 and PA2 are used to provide address lines to select
|
||||
either the HPIC, HPIA, or HPID registers of the HPI. The FX2
|
||||
reads and writes data by accessing these registers.</font><font face="Verdana,Arial" size="1" color="#000000">
|
||||
</font></p>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td colspan="1" align="left">
|
||||
<ul>
|
||||
<p><font face="Verdana" size="1"><b>FD[7:0] <----> HD[7:0]</b><br>The
|
||||
lower portion of the GPIF data bus (FD[7:0]) is connected to
|
||||
the HPI data bus (HD[7:0]). The FX2 uses this connection for
|
||||
exchange of information between itself and the HPI. </font></p>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td colspan="1" align="left">
|
||||
<ul>
|
||||
<p><font face="Verdana" size="1"><b>CTL0 ----> HRNW</b><br>CTL0
|
||||
is connected to the HRNW signal of the HPI. If HRNW is a 1,
|
||||
this indicates a read access to the HPI. If HRNW is a 0, this
|
||||
indicates a write access to the HPI. </font></p>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td colspan="1" align="left">
|
||||
<ul>
|
||||
<p><font face="Verdana" size="1"><b>CTL1 ----> HDS1</b><br>CTL1
|
||||
is connected to the HDS1/ strobe of the HPI. The falling edge
|
||||
of HDS1/ marks the beginning of the HPI access, and samples
|
||||
the value of HRNW, HCNTL[1:0], and HBIL. The rising edge of
|
||||
HDS1/ marks the end of the HPI access. </font></p>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td colspan="1" align="left">
|
||||
<ul>
|
||||
<p><font face="Verdana" size="1"><b>CTL2 ----> HBIL</b><br>CTL2
|
||||
is connected to the HBIL signal of the HPI. A complete HPI access
|
||||
consists of a two byte transfer. If HBIL is 0, this indicates
|
||||
to the HPI that the first byte is being transferred. To indicate
|
||||
to the HPI that the second byte is being transferred, HBIL must
|
||||
be 1.</font></p>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td colspan="1" align="left">
|
||||
<ul>
|
||||
<p><font face="Verdana" size="1"><b>RDY0 <---- HRDY</b><br>RDY0
|
||||
is connected to the HRDY/ signal of the HPI. HRDY/ is low when
|
||||
the HPI is completing the internal portion of a complete HPI
|
||||
access. Another access to the HPI must not be performed until
|
||||
the internal portion of the transfer is complete. This signal
|
||||
is monitored by the GPIF.</font></p>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td colspan="1" align="left">
|
||||
<ul>
|
||||
<p><font face="Verdana" size="1"><b>INT0 <---- HINT, INT2</b><br>The
|
||||
INT0/ interrupt signal on the FX2 is conected the HINT/ output
|
||||
of the HPI. When the DSP is reset, the HINT/ will be asserted.
|
||||
The DSP can also use this as a general purpose interrupt to
|
||||
the FX2. The HINT/ signal is also tied to the 5416&rsquo;s
|
||||
INT2/ pin to allow the FX2 to be able to bootload the DSP code.</font></p>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td colspan="1" align="left">
|
||||
<ul>
|
||||
<p><font face="Verdana" size="1"><b>GND <----> GND</b><br>Ground</font></p>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr valign="top">
|
||||
<td colspan="1" align="left">
|
||||
<ul>
|
||||
<p><font face="Verdana" size="1"><b>HCS, HPI_16</b><br>HPI_16
|
||||
is tied to ground to make the HPI operate in 8-bit mode (HPI-8).
|
||||
The HPI can operate in 16-bit mode (HPI-16) if the 5416&rsquo;s
|
||||
external memory interface is not used (EMIF). For most DSP applications,
|
||||
the EMIF will already be used for memory expansion. Using the
|
||||
HPI in 8-bit mode also simplifies the GPIF interface. HCS/ is
|
||||
tied to ground to allow continuous access to the HPI.</font></p>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr valign="top">
|
||||
<td colspan="1" align="left">
|
||||
<ul>
|
||||
<p><font face="Verdana" size="1"><b>HDS2, HAS, HPI_EN</b><br>HPI_EN
|
||||
is tied to VCC to enable the HPI port. HAS/ and HDS2/ are tied
|
||||
to VCC since they are not necessary for this interface (attributed
|
||||
in part to the flexibility of the GPIF interface).</font></p>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr valign="top">
|
||||
<td colspan="1" align="left">
|
||||
|
||||
<p>
|
||||
<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000">The assignment of CTL and RDY lines was optimized for the FX2 56-pin package. The connection between the TI 5416
|
||||
DSK board and the FX2 development board was accomplished through the use of a ribbon cable set. The TI 5416 DSK board
|
||||
exposes headers that require breakout panels (available from <A href="http://www.dspglobal.com" target="resource window">www.dspglobal.com</A>) for prototyping purposes. The ribbon cables
|
||||
connect between a breakout panel installed on the DSK board's P3 and the FX2 prototype board mounted onto the FX2 development
|
||||
board. Figure 14 shows a snap of the actual hardware setup.<br>
|
||||
<br></font> <p align="center">
|
||||
<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000"><br><img src="images/setup.jpg" align="center" width="298" height="200" border="0"><br>Figure 14. Shot of Actual Hardware Setup<br><br> </font></p>
|
||||
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr valign="top">
|
||||
<td colspan="1" align="left">
|
||||
<font face="verdana, arial, helvetica, sans-serif" size="2" color="#000000"><B><a name="DataFlow"></a>Application-specific Data Flow</B><br>
|
||||
|
||||
</font>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr valign="top">
|
||||
<td colspan="1" align="left">
|
||||
|
||||
<p>
|
||||
<font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000">Now that the GPIF interconnect has been presented, it's important to understand the overall data flow for this design example.
|
||||
EP2OUT (4x buffered) is the source endpoint used for data writes to the HPI and EP6IN (4x buffered) is the sink endpoint used
|
||||
for data reads from the HPI. EP0, the FX2's control endpoint, is used for writes to the HPIC and HPIA registers.<br>
|
||||
<br>
|
||||
Before a data read or write can commence to and from a specific address in the DSP, the HPIA needs to be setup with the
|
||||
appropriate source or destination address. The HPIC also needs to be setup to set the BOB bit to 1, which allows the first byte
|
||||
of transfer to be the LSB and the second byte of the transfer to be the MSB (as organized in the DSP memory). Since the 5416
|
||||
supports an extended address scheme, the XPHIA bit in the HPIC register needs to be set if FX2 wants to access the upper
|
||||
seven bits of the HPIA register. The XPHIA bit also needs to be set if proper auto-increment of the address is to occur when
|
||||
consecutive data read and write accesses are made.<br>
|
||||
<br>
|
||||
Figure 15 and Figure 16 show the data flow models for this example. GPIF single transactions are used to write out the data from EP0 to the
|
||||
HPIC and HPIA registers. GPIF FIFO transactions are used for data reads and writes using EP6IN and EP2OUT in auto mode, respectively.<br></font>
|
||||
<ul>
|
||||
<ul>
|
||||
<p><font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000"><img src="images/dsp-out.gif" width="300" height="180" align="center" border="0"> <br>Figure 15. Data Flow Model in the <B>OUT</B> direction </font></p>
|
||||
</ul>
|
||||
</ul>
|
||||
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td colspan="1" align="center">
|
||||
<ul>
|
||||
<ul>
|
||||
<p align="left"><font face="Verdana" size="1"><br> </font><font face="verdana, arial, helvetica, sans-serif" size="1" color="#000000"><img src="images/dsp-in.gif" width="300" height="180" align="center" border="0"><br>Figure 16. Data Flow Model in the <B>IN</B> direction </font></p>
|
||||
|
||||
</ul>
|
||||
</ul>
|
||||
<p align="left"> </p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td colspan="1" align="center">
|
||||
<p align="left"><font face="Verdana" size="1"> </font></p>
|
||||
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td colspan="1" align="center">
|
||||
<p align="left"><font face="Verdana" size="1"> </font></p>
|
||||
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
@@ -0,0 +1,33 @@
|
||||
<html>
|
||||
|
||||
<head>
|
||||
<title>Contents</title>
|
||||
<base target="detail"></head>
|
||||
|
||||
<body bgcolor="#CCCCCC" text="black" link="blue" vlink="purple" alink="red">
|
||||
<p align="left"><font face="Verdana" size="1"><b><a href="intro.htm#Overview">Overview</a><br>
|
||||
</b><a href="intro.htm#Physical">Hardware Connections</a><br> <a href="intro.htm#DataFlow">App-specific
|
||||
Data Flow</a><br><br> <b><a href="DSPXactions.htm#DSPXactions">GPIF
|
||||
Transactions<br></a> </b> <a href="DSPXactions.htm#WaveformDescriptors">Waveform Descriptors<br></a> <a href="DSPXactions.htm#FW">Firmware</a><br>
|
||||
<a href="DSPXactions.htm#Files">FW
|
||||
Files<br></a> <a href="DSPXactions.htm#TD_Init(">TD_Init()
|
||||
function</a><br> <a href="DSPXactions.htm#IFCONFIG">IFCONFIG
|
||||
Register</a><br> <a href="DSPXactions.htm#WritingHPIC">Writing
|
||||
HPIC and HPIA</a><br> <a href="DSPXactions.htm#HPIRdWr">Read
|
||||
/ Write the HPI</a><br> <a href="DSPXactions.htm#INT0">Handling
|
||||
INT0</a><br> <a href="DSPXactions.htm#Running">Running the example</a><b><br>
|
||||
</b> <a href="DSPXactions.htm#Running">Step
|
||||
1: Download FW</a><br> <a href="DSPXactions.htm#Step2">Step
|
||||
2: Write to the HPI</a><br> <a href="DSPXactions.htm#Step3">Step
|
||||
3: Read from HPI</a><br> <a href="DSPXactions.htm#Step4">Step
|
||||
4: Load DSP code</a><br> <a href="DSPXactions.htm#Traces">Logic
|
||||
Analyzer Traces</a><br> <a href="DSPXactions.htm#WriteHPIC1">Write
|
||||
HPIC</a><br> <a href="DSPXactions.htm#WriteHPIC2">Write
|
||||
HPIC: 1st Byte</a><br> <a href="DSPXactions.htm#WriteHPIC3">Write
|
||||
HPIC: 2nd Byte</a><br> <a href="DSPXactions.htm#FIFOWrHPI1">FIFO
|
||||
Write HPI</a><br> <a href="DSPXactions.htm#FIFOWrHPI2">FIFOWr HPI:
|
||||
Close-up</a><br> <a href="DSPXactions.htm#FIFORdHPI">FIFORd HPI:
|
||||
Close-up</a><br> <a href="DSPXactions.htm#DnLoadDSP">Download
|
||||
DSP Code</a><br> </font></p>
|
||||
</body>
|
||||
|
||||
@@ -0,0 +1,30 @@
|
||||
const char xdata WaveData[128] =
|
||||
{
|
||||
// Wave 0
|
||||
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x38, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x00, 0x02, 0x00, 0x02, 0x01, 0x00, 0x00,
|
||||
/* Output*/ 0xFB, 0xF9, 0xFF, 0xFD, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* LFun */ 0x00, 0x12, 0x12, 0x12, 0x00, 0x2D, 0x12, 0x3F,
|
||||
// Wave 1
|
||||
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x38, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x02, 0x04, 0x02, 0x04, 0x01, 0x00, 0x00,
|
||||
/* Output*/ 0xFA, 0xF8, 0xFE, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF,
|
||||
/* LFun */ 0x00, 0x12, 0x12, 0x12, 0x00, 0x2D, 0x12, 0x3F,
|
||||
// Wave 2
|
||||
/* LenBr */ 0x01, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* Output*/ 0xFE, 0xFC, 0xFE, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF,
|
||||
/* LFun */ 0x00, 0x12, 0x12, 0x12, 0x00, 0x2D, 0x12, 0x3F,
|
||||
// Wave 3
|
||||
/* LenBr */ 0x01, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* Output*/ 0xFA, 0xF8, 0xFA, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF,
|
||||
/* LFun */ 0x00, 0x12, 0x12, 0x12, 0x00, 0x2D, 0x12, 0x3F
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char xdata InitData[7] =
|
||||
{
|
||||
/* Regs */ 0xC0,0x80,0x00,0xFF,0x06,0xE4,0x11
|
||||
};
|
||||
@@ -0,0 +1,265 @@
|
||||
;;-----------------------------------------------------------------------------
|
||||
;; File: dscr.a51
|
||||
;; Contents: This file contains descriptor data tables.
|
||||
;;
|
||||
;; Copyright (c) 2002 Cypress Semiconductor, Inc. All rights reserved
|
||||
;;-----------------------------------------------------------------------------
|
||||
|
||||
DSCR_DEVICE equ 1 ;; Descriptor type: Device
|
||||
DSCR_CONFIG equ 2 ;; Descriptor type: Configuration
|
||||
DSCR_STRING equ 3 ;; Descriptor type: String
|
||||
DSCR_INTRFC equ 4 ;; Descriptor type: Interface
|
||||
DSCR_ENDPNT equ 5 ;; Descriptor type: Endpoint
|
||||
DSCR_DEVQUAL equ 6 ;; Descriptor type: Device Qualifier
|
||||
|
||||
DSCR_DEVICE_LEN equ 18
|
||||
DSCR_CONFIG_LEN equ 9
|
||||
DSCR_INTRFC_LEN equ 9
|
||||
DSCR_ENDPNT_LEN equ 7
|
||||
DSCR_DEVQUAL_LEN equ 10
|
||||
|
||||
ET_CONTROL equ 0 ;; Endpoint type: Control
|
||||
ET_ISO equ 1 ;; Endpoint type: Isochronous
|
||||
ET_BULK equ 2 ;; Endpoint type: Bulk
|
||||
ET_INT equ 3 ;; Endpoint type: Interrupt
|
||||
|
||||
public DeviceDscr, DeviceQualDscr, HighSpeedConfigDscr, FullSpeedConfigDscr, StringDscr, UserDscr
|
||||
|
||||
DSCR SEGMENT CODE PAGE
|
||||
|
||||
;;-----------------------------------------------------------------------------
|
||||
;; Global Variables
|
||||
;;-----------------------------------------------------------------------------
|
||||
rseg DSCR ;; locate the descriptor table in on-part memory.
|
||||
|
||||
DeviceDscr:
|
||||
db DSCR_DEVICE_LEN ;; Descriptor length
|
||||
db DSCR_DEVICE ;; Decriptor type
|
||||
dw 0002H ;; Specification Version (BCD)
|
||||
db 00H ;; Device class
|
||||
db 00H ;; Device sub-class
|
||||
db 00H ;; Device sub-sub-class
|
||||
db 64 ;; Maximum packet size
|
||||
dw 4705H ;; Vendor ID
|
||||
dw 0210H ;; Product ID (Sample Device)
|
||||
dw 0000H ;; Product version ID
|
||||
db 1 ;; Manufacturer string index
|
||||
db 2 ;; Product string index
|
||||
db 0 ;; Serial number string index
|
||||
db 1 ;; Number of configurations
|
||||
|
||||
DeviceQualDscr:
|
||||
db DSCR_DEVQUAL_LEN ;; Descriptor length
|
||||
db DSCR_DEVQUAL ;; Decriptor type
|
||||
dw 0002H ;; Specification Version (BCD)
|
||||
db 00H ;; Device class
|
||||
db 00H ;; Device sub-class
|
||||
db 00H ;; Device sub-sub-class
|
||||
db 64 ;; Maximum packet size
|
||||
db 1 ;; Number of configurations
|
||||
db 0 ;; Reserved
|
||||
|
||||
HighSpeedConfigDscr:
|
||||
db DSCR_CONFIG_LEN ;; Descriptor length
|
||||
db DSCR_CONFIG ;; Descriptor type
|
||||
db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) mod 256 ;; Total Length (LSB)
|
||||
db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) / 256 ;; Total Length (MSB)
|
||||
db 1 ;; Number of interfaces
|
||||
db 1 ;; Configuration number
|
||||
db 0 ;; Configuration string
|
||||
db 10000000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
|
||||
db 50 ;; Power requirement (div 2 ma)
|
||||
|
||||
;; Interface Descriptor
|
||||
db DSCR_INTRFC_LEN ;; Descriptor length
|
||||
db DSCR_INTRFC ;; Descriptor type
|
||||
db 0 ;; Zero-based index of this interface
|
||||
db 0 ;; Alternate setting
|
||||
db 4 ;; Number of end points
|
||||
db 0ffH ;; Interface class
|
||||
db 00H ;; Interface sub class
|
||||
db 00H ;; Interface sub sub class
|
||||
db 0 ;; Interface descriptor string index
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 01H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 00H ;; Maximum packet size (LSB)
|
||||
db 02H ;; Maximum packet size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 81H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 00H ;; Maximum packet size (LSB)
|
||||
db 02H ;; Maximum packet size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 02H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 00H ;; Maximum packet size (LSB)
|
||||
db 02H ;; Maximum packet size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 86H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 00H ;; Maximum packet size (LSB)
|
||||
db 02H ;; Maximum packet size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
HighSpeedConfigDscrEnd:
|
||||
|
||||
FullSpeedConfigDscr:
|
||||
db DSCR_CONFIG_LEN ;; Descriptor length
|
||||
db DSCR_CONFIG ;; Descriptor type
|
||||
db (FullSpeedConfigDscrEnd-FullSpeedConfigDscr) mod 256 ;; Total Length (LSB)
|
||||
db (FullSpeedConfigDscrEnd-FullSpeedConfigDscr) / 256 ;; Total Length (MSB)
|
||||
db 1 ;; Number of interfaces
|
||||
db 1 ;; Configuration number
|
||||
db 0 ;; Configuration string
|
||||
db 10000000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
|
||||
db 50 ;; Power requirement (div 2 ma)
|
||||
|
||||
;; Interface Descriptor
|
||||
db DSCR_INTRFC_LEN ;; Descriptor length
|
||||
db DSCR_INTRFC ;; Descriptor type
|
||||
db 0 ;; Zero-based index of this interface
|
||||
db 0 ;; Alternate setting
|
||||
db 4 ;; Number of end points
|
||||
db 0ffH ;; Interface class
|
||||
db 00H ;; Interface sub class
|
||||
db 00H ;; Interface sub sub class
|
||||
db 0 ;; Interface descriptor string index
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 01H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 40H ;; Maximum packet size (LSB)
|
||||
db 00H ;; Maximum packet size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 81H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 40H ;; Maximum packet size (LSB)
|
||||
db 00H ;; Maximum packet size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 02H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 40H ;; Maximun packet size (LSB)
|
||||
db 00H ;; Maximum packet size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
;; Endpoint Descriptor
|
||||
db DSCR_ENDPNT_LEN ;; Descriptor length
|
||||
db DSCR_ENDPNT ;; Descriptor type
|
||||
db 86H ;; Endpoint number, and direction
|
||||
db ET_BULK ;; Endpoint type
|
||||
db 40H ;; Maximum packet size (LSB)
|
||||
db 00H ;; Maximum packet size (MSB)
|
||||
db 00H ;; Polling interval
|
||||
|
||||
FullSpeedConfigDscrEnd:
|
||||
|
||||
StringDscr:
|
||||
|
||||
StringDscr0:
|
||||
db StringDscr0End-StringDscr0 ;; String descriptor length
|
||||
db DSCR_STRING
|
||||
db 09H,04H
|
||||
StringDscr0End:
|
||||
|
||||
StringDscr1:
|
||||
db StringDscr1End-StringDscr1 ;; String descriptor length
|
||||
db DSCR_STRING
|
||||
db 'C',00
|
||||
db 'y',00
|
||||
db 'p',00
|
||||
db 'r',00
|
||||
db 'e',00
|
||||
db 's',00
|
||||
db 's',00
|
||||
StringDscr1End:
|
||||
|
||||
StringDscr2:
|
||||
db StringDscr2End-StringDscr2 ;; Descriptor length
|
||||
db DSCR_STRING
|
||||
db 'E',00
|
||||
db 'Z',00
|
||||
db '-',00
|
||||
db 'U',00
|
||||
db 'S',00
|
||||
db 'B',00
|
||||
db ' ',00
|
||||
db 'F',00
|
||||
db 'X',00
|
||||
db '2',00
|
||||
db ' ',00
|
||||
db 'G',00
|
||||
db 'P',00
|
||||
db 'I',00
|
||||
db 'F',00
|
||||
db ' ',00
|
||||
db 't',00
|
||||
db 'o',00
|
||||
db ' ',00
|
||||
db 'T',00
|
||||
db 'I',00
|
||||
db ' ',00
|
||||
db '5',00
|
||||
db '4',00
|
||||
db '1',00
|
||||
db '6',00
|
||||
db ' ',00
|
||||
db 'H',00
|
||||
db 'P',00
|
||||
db 'I',00
|
||||
db ' ',00
|
||||
db 'u',00
|
||||
db 's',00
|
||||
db 'i',00
|
||||
db 'n',00
|
||||
db 'g',00
|
||||
db ' ',00
|
||||
db 'F',00
|
||||
db 'I',00
|
||||
db 'F',00
|
||||
db 'O',00
|
||||
db ' ',00
|
||||
db 'T',00
|
||||
db 'r',00
|
||||
db 'a',00
|
||||
db 'n',00
|
||||
db 's',00
|
||||
db 'a',00
|
||||
db 'c',00
|
||||
db 't',00
|
||||
db 'i',00
|
||||
db 'o',00
|
||||
db 'n',00
|
||||
db 's',00
|
||||
StringDscr2End:
|
||||
|
||||
UserDscr:
|
||||
dw 0000H
|
||||
end
|
||||
|
||||
@@ -0,0 +1,366 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// File: fw.c
|
||||
// Contents: Firmware frameworks task dispatcher and device request parser
|
||||
// source.
|
||||
//
|
||||
// indent 3. NO TABS!
|
||||
//
|
||||
// $Revision: 17 $
|
||||
// $Date: 11/15/01 5:45p $
|
||||
//
|
||||
// Copyright (c) 2002 Cypress Semiconductor, Inc. All rights reserved
|
||||
//-----------------------------------------------------------------------------
|
||||
#include "fx2.h"
|
||||
#include "fx2regs.h"
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Constants
|
||||
//-----------------------------------------------------------------------------
|
||||
#define DELAY_COUNT 0x9248*8L // Delay for 8 sec at 24Mhz, 4 sec at 48
|
||||
#define _IFREQ 48000 // IFCLK constant for Synchronization Delay
|
||||
#define _CFREQ 48000 // CLKOUT constant for Synchronization Delay
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Random Macros
|
||||
//-----------------------------------------------------------------------------
|
||||
#define min(a,b) (((a)<(b))?(a):(b))
|
||||
#define max(a,b) (((a)>(b))?(a):(b))
|
||||
|
||||
// Registers which require a synchronization delay, see section 15.14
|
||||
// FIFORESET FIFOPINPOLAR
|
||||
// INPKTEND OUTPKTEND
|
||||
// EPxBCH:L REVCTL
|
||||
// GPIFTCB3 GPIFTCB2
|
||||
// GPIFTCB1 GPIFTCB0
|
||||
// EPxFIFOPFH:L EPxAUTOINLENH:L
|
||||
// EPxFIFOCFG EPxGPIFFLGSEL
|
||||
// PINFLAGSxx EPxFIFOIRQ
|
||||
// EPxFIFOIE GPIFIRQ
|
||||
// GPIFIE GPIFADRH:L
|
||||
// UDMACRCH:L EPxGPIFTRIG
|
||||
// GPIFTRIG
|
||||
|
||||
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
|
||||
// ...these have been replaced by GPIFTC[B3:B0] registers
|
||||
|
||||
#include "fx2sdly.h" // Define _IFREQ and _CFREQ above this #include
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Global Variables
|
||||
//-----------------------------------------------------------------------------
|
||||
volatile BOOL GotSUD;
|
||||
BOOL Rwuen;
|
||||
BOOL Selfpwr;
|
||||
volatile BOOL Sleep; // Sleep mode enable flag
|
||||
|
||||
WORD pDeviceDscr; // Pointer to Device Descriptor; Descriptors may be moved
|
||||
WORD pDeviceQualDscr;
|
||||
WORD pHighSpeedConfigDscr;
|
||||
WORD pFullSpeedConfigDscr;
|
||||
WORD pConfigDscr;
|
||||
WORD pOtherConfigDscr;
|
||||
WORD pStringDscr;
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Prototypes
|
||||
//-----------------------------------------------------------------------------
|
||||
void SetupCommand(void);
|
||||
void TD_Init(void);
|
||||
void TD_Poll(void);
|
||||
BOOL TD_Suspend(void);
|
||||
BOOL TD_Resume(void);
|
||||
|
||||
BOOL DR_GetDescriptor(void);
|
||||
BOOL DR_SetConfiguration(void);
|
||||
BOOL DR_GetConfiguration(void);
|
||||
BOOL DR_SetInterface(void);
|
||||
BOOL DR_GetInterface(void);
|
||||
BOOL DR_GetStatus(void);
|
||||
BOOL DR_ClearFeature(void);
|
||||
BOOL DR_SetFeature(void);
|
||||
BOOL DR_VendorCmnd(void);
|
||||
|
||||
// this table is used by the epcs macro
|
||||
const char code EPCS_Offset_Lookup_Table[] =
|
||||
{
|
||||
0, // EP1OUT
|
||||
1, // EP1IN
|
||||
2, // EP2OUT
|
||||
2, // EP2IN
|
||||
3, // EP4OUT
|
||||
3, // EP4IN
|
||||
4, // EP6OUT
|
||||
4, // EP6IN
|
||||
5, // EP8OUT
|
||||
5, // EP8IN
|
||||
};
|
||||
|
||||
// macro for generating the address of an endpoint's control and status register (EPnCS)
|
||||
#define epcs(EP) (EPCS_Offset_Lookup_Table[(EP & 0x7E) | (EP > 128)] + 0xE6A1)
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Code
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
// Task dispatcher
|
||||
void main(void)
|
||||
{
|
||||
DWORD i;
|
||||
WORD offset;
|
||||
DWORD DevDescrLen;
|
||||
DWORD j=0;
|
||||
WORD IntDescrAddr;
|
||||
WORD ExtDescrAddr;
|
||||
|
||||
// Initialize Global States
|
||||
Sleep = FALSE; // Disable sleep mode
|
||||
Rwuen = FALSE; // Disable remote wakeup
|
||||
Selfpwr = FALSE; // Disable self powered
|
||||
GotSUD = FALSE; // Clear "Got setup data" flag
|
||||
|
||||
// Initialize user device
|
||||
TD_Init();
|
||||
|
||||
// The following section of code is used to relocate the descriptor table.
|
||||
// Since the SUDPTRH and SUDPTRL are assigned the address of the descriptor
|
||||
// table, the descriptor table must be located in on-part memory.
|
||||
// The 4K demo tools locate all code sections in external memory.
|
||||
// The descriptor table is relocated by the frameworks ONLY if it is found
|
||||
// to be located in external memory.
|
||||
pDeviceDscr = (WORD)&DeviceDscr;
|
||||
pDeviceQualDscr = (WORD)&DeviceQualDscr;
|
||||
pHighSpeedConfigDscr = (WORD)&HighSpeedConfigDscr;
|
||||
pFullSpeedConfigDscr = (WORD)&FullSpeedConfigDscr;
|
||||
pStringDscr = (WORD)&StringDscr;
|
||||
|
||||
if (EZUSB_HIGHSPEED())
|
||||
{
|
||||
pConfigDscr = pHighSpeedConfigDscr;
|
||||
pOtherConfigDscr = pFullSpeedConfigDscr;
|
||||
}
|
||||
else
|
||||
{
|
||||
pConfigDscr = pFullSpeedConfigDscr;
|
||||
pOtherConfigDscr = pHighSpeedConfigDscr;
|
||||
}
|
||||
|
||||
if ((WORD)&DeviceDscr & 0xe000)
|
||||
{
|
||||
IntDescrAddr = INTERNAL_DSCR_ADDR;
|
||||
ExtDescrAddr = (WORD)&DeviceDscr;
|
||||
DevDescrLen = (WORD)&UserDscr - (WORD)&DeviceDscr + 2;
|
||||
for (i = 0; i < DevDescrLen; i++)
|
||||
*((BYTE xdata *)IntDescrAddr+i) = 0xCD;
|
||||
for (i = 0; i < DevDescrLen; i++)
|
||||
*((BYTE xdata *)IntDescrAddr+i) = *((BYTE xdata *)ExtDescrAddr+i);
|
||||
pDeviceDscr = IntDescrAddr;
|
||||
offset = (WORD)&DeviceDscr - INTERNAL_DSCR_ADDR;
|
||||
pDeviceQualDscr -= offset;
|
||||
pConfigDscr -= offset;
|
||||
pOtherConfigDscr -= offset;
|
||||
pHighSpeedConfigDscr -= offset;
|
||||
pFullSpeedConfigDscr -= offset;
|
||||
pStringDscr -= offset;
|
||||
}
|
||||
|
||||
EZUSB_IRQ_ENABLE(); // Enable USB interrupt (INT2)
|
||||
EZUSB_ENABLE_RSMIRQ(); // Wake-up interrupt
|
||||
|
||||
INTSETUP |= (bmAV2EN | bmAV4EN); // Enable INT 2 & 4 autovectoring
|
||||
|
||||
USBIE |= bmSUDAV | bmSUTOK | bmSUSP | bmURES | bmHSGRANT; // Enable selected interrupts
|
||||
EA = 1; // Enable 8051 interrupts
|
||||
|
||||
#ifndef NO_RENUM
|
||||
// Renumerate if necessary. Do this by checking the renum bit. If it
|
||||
// is already set, there is no need to renumerate. The renum bit will
|
||||
// already be set if this firmware was loaded from an eeprom.
|
||||
if(!(USBCS & bmRENUM))
|
||||
{
|
||||
EZUSB_Discon(TRUE); // renumerate
|
||||
}
|
||||
#endif
|
||||
|
||||
// unconditionally re-connect. If we loaded from eeprom we are
|
||||
// disconnected and need to connect. If we just renumerated this
|
||||
// is not necessary but doesn't hurt anything
|
||||
USBCS &=~bmDISCON;
|
||||
|
||||
CKCON = (CKCON&(~bmSTRETCH)) | FW_STRETCH_VALUE; // Set stretch to 0 (after renumeration)
|
||||
|
||||
// clear the Sleep flag.
|
||||
Sleep = FALSE;
|
||||
|
||||
// Task Dispatcher
|
||||
while(TRUE) // Main Loop
|
||||
{
|
||||
if(GotSUD) // Wait for SUDAV
|
||||
{
|
||||
SetupCommand(); // Implement setup command
|
||||
GotSUD = FALSE; // Clear SUDAV flag
|
||||
}
|
||||
|
||||
// Poll User Device
|
||||
// NOTE: Idle mode stops the processor clock. There are only two
|
||||
// ways out of idle mode, the WAKEUP pin, and detection of the USB
|
||||
// resume state on the USB bus. The timers will stop and the
|
||||
// processor will not wake up on any other interrupts.
|
||||
if (Sleep)
|
||||
{
|
||||
if(TD_Suspend())
|
||||
{
|
||||
Sleep = FALSE; // Clear the "go to sleep" flag. Do it here to prevent any race condition between wakeup and the next sleep.
|
||||
do
|
||||
{
|
||||
EZUSB_Susp(); // Place processor in idle mode.
|
||||
}
|
||||
while(!Rwuen && EZUSB_EXTWAKEUP());
|
||||
// Must continue to go back into suspend if the host has disabled remote wakeup
|
||||
// *and* the wakeup was caused by the external wakeup pin.
|
||||
|
||||
// 8051 activity will resume here due to USB bus or Wakeup# pin activity.
|
||||
EZUSB_Resume(); // If source is the Wakeup# pin, signal the host to Resume.
|
||||
TD_Resume();
|
||||
}
|
||||
}
|
||||
TD_Poll();
|
||||
}
|
||||
}
|
||||
|
||||
// Device request parser
|
||||
void SetupCommand(void)
|
||||
{
|
||||
void *dscr_ptr;
|
||||
|
||||
switch(SETUPDAT[1])
|
||||
{
|
||||
case SC_GET_DESCRIPTOR: // *** Get Descriptor
|
||||
if(DR_GetDescriptor())
|
||||
switch(SETUPDAT[3])
|
||||
{
|
||||
case GD_DEVICE: // Device
|
||||
SUDPTRH = MSB(pDeviceDscr);
|
||||
SUDPTRL = LSB(pDeviceDscr);
|
||||
break;
|
||||
case GD_DEVICE_QUALIFIER: // Device Qualifier
|
||||
SUDPTRH = MSB(pDeviceQualDscr);
|
||||
SUDPTRL = LSB(pDeviceQualDscr);
|
||||
break;
|
||||
case GD_CONFIGURATION: // Configuration
|
||||
SUDPTRH = MSB(pConfigDscr);
|
||||
SUDPTRL = LSB(pConfigDscr);
|
||||
break;
|
||||
case GD_OTHER_SPEED_CONFIGURATION: // Other Speed Configuration
|
||||
SUDPTRH = MSB(pOtherConfigDscr);
|
||||
SUDPTRL = LSB(pOtherConfigDscr);
|
||||
break;
|
||||
case GD_STRING: // String
|
||||
if(dscr_ptr = (void *)EZUSB_GetStringDscr(SETUPDAT[2]))
|
||||
{
|
||||
SUDPTRH = MSB(dscr_ptr);
|
||||
SUDPTRL = LSB(dscr_ptr);
|
||||
}
|
||||
else
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
break;
|
||||
default: // Invalid request
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
}
|
||||
break;
|
||||
case SC_GET_INTERFACE: // *** Get Interface
|
||||
DR_GetInterface();
|
||||
break;
|
||||
case SC_SET_INTERFACE: // *** Set Interface
|
||||
DR_SetInterface();
|
||||
break;
|
||||
case SC_SET_CONFIGURATION: // *** Set Configuration
|
||||
DR_SetConfiguration();
|
||||
break;
|
||||
case SC_GET_CONFIGURATION: // *** Get Configuration
|
||||
DR_GetConfiguration();
|
||||
break;
|
||||
case SC_GET_STATUS: // *** Get Status
|
||||
if(DR_GetStatus())
|
||||
switch(SETUPDAT[0])
|
||||
{
|
||||
case GS_DEVICE: // Device
|
||||
EP0BUF[0] = ((BYTE)Rwuen << 1) | (BYTE)Selfpwr;
|
||||
EP0BUF[1] = 0;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 2;
|
||||
break;
|
||||
case GS_INTERFACE: // Interface
|
||||
EP0BUF[0] = 0;
|
||||
EP0BUF[1] = 0;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 2;
|
||||
break;
|
||||
case GS_ENDPOINT: // End Point
|
||||
EP0BUF[0] = *(BYTE xdata *) epcs(SETUPDAT[4]) & bmEPSTALL;
|
||||
EP0BUF[1] = 0;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 2;
|
||||
break;
|
||||
default: // Invalid Command
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
}
|
||||
break;
|
||||
case SC_CLEAR_FEATURE: // *** Clear Feature
|
||||
if(DR_ClearFeature())
|
||||
switch(SETUPDAT[0])
|
||||
{
|
||||
case FT_DEVICE: // Device
|
||||
if(SETUPDAT[2] == 1)
|
||||
Rwuen = FALSE; // Disable Remote Wakeup
|
||||
else
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
break;
|
||||
case FT_ENDPOINT: // End Point
|
||||
if(SETUPDAT[2] == 0)
|
||||
{
|
||||
*(BYTE xdata *) epcs(SETUPDAT[4]) &= ~bmEPSTALL;
|
||||
EZUSB_RESET_DATA_TOGGLE( SETUPDAT[4] );
|
||||
}
|
||||
else
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case SC_SET_FEATURE: // *** Set Feature
|
||||
if(DR_SetFeature())
|
||||
switch(SETUPDAT[0])
|
||||
{
|
||||
case FT_DEVICE: // Device
|
||||
if(SETUPDAT[2] == 1)
|
||||
Rwuen = TRUE; // Enable Remote Wakeup
|
||||
else if(SETUPDAT[2] == 2)
|
||||
// Set Feature Test Mode. The core handles this request. However, it is
|
||||
// necessary for the firmware to complete the handshake phase of the
|
||||
// control transfer before the chip will enter test mode. It is also
|
||||
// necessary for FX2 to be physically disconnected (D+ and D-)
|
||||
// from the host before it will enter test mode.
|
||||
break;
|
||||
else
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
break;
|
||||
case FT_ENDPOINT: // End Point
|
||||
*(BYTE xdata *) epcs(SETUPDAT[4]) |= bmEPSTALL;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default: // *** Invalid Command
|
||||
if(DR_VendorCmnd())
|
||||
EZUSB_STALL_EP0(); // Stall End Point 0
|
||||
}
|
||||
|
||||
// Acknowledge handshake phase of device request
|
||||
EP0CS |= bmHSNAK;
|
||||
}
|
||||
|
||||
// Wake-up interrupt handler
|
||||
void resume_isr(void) interrupt WKUP_VECT
|
||||
{
|
||||
EZUSB_CLEAR_RSMIRQ();
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,292 @@
|
||||
// This program configures the General Programmable Interface (GPIF) for FX2.
|
||||
// Please do not modify sections of text which are marked as "DO NOT EDIT ...".
|
||||
//
|
||||
// DO NOT EDIT ...
|
||||
// GPIF Initialization
|
||||
// Interface Timing Sync
|
||||
// Internal Ready Init IntRdy=1
|
||||
// CTL Out Tristate-able Binary
|
||||
// SingleWrite WF Select 1
|
||||
// SingleRead WF Select 0
|
||||
// FifoWrite WF Select 3
|
||||
// FifoRead WF Select 2
|
||||
// Data Bus Idle Drive Tristate
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
// GPIF Wave Names
|
||||
// Wave 0 = SnglWr1
|
||||
// Wave 1 = SnglWr2
|
||||
// Wave 2 = FIFORd
|
||||
// Wave 3 = FIFOWr
|
||||
|
||||
// GPIF Ctrl Outputs Level
|
||||
// CTL 0 = HR/W* CMOS
|
||||
// CTL 1 = HDS1* CMOS
|
||||
// CTL 2 = HBIL CMOS
|
||||
// CTL 3 = CTL3 CMOS
|
||||
// CTL 4 = CTL4 CMOS
|
||||
// CTL 5 = CTL5 CMOS
|
||||
|
||||
// GPIF Rdy Inputs
|
||||
// RDY0 = HRDY*
|
||||
// RDY1 = HDS1*
|
||||
// RDY2 = HBIL
|
||||
// RDY3 = RDY3
|
||||
// RDY4 = RDY4
|
||||
// RDY5 = TCXpire
|
||||
// FIFOFlag = FIFOFlag
|
||||
// IntReady = IntReady
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 0: SnglWr1
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data Activate NO Data NO Data NO Data NO Data NO Data
|
||||
// NextData SameData SameData NextData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A HRDY*
|
||||
// LFunc AND
|
||||
// Term B HRDY*
|
||||
// Branch1 ThenIdle
|
||||
// Branch0 ElseIdle
|
||||
// Re-Exec No
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// HR/W* 0 0 0 0 0 0 0 1
|
||||
// HDS1* 1 0 1 1 1 1 1 1
|
||||
// HBIL 0 0 0 0 0 0 0 1
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 1: SnglWr2
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data Activate NO Data NO Data NO Data NO Data NO Data
|
||||
// NextData SameData SameData NextData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A HRDY*
|
||||
// LFunc AND
|
||||
// Term B HRDY*
|
||||
// Branch1 ThenIdle
|
||||
// Branch0 ElseIdle
|
||||
// Re-Exec No
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// HR/W* 0 0 0 0 0 0 0 1
|
||||
// HDS1* 1 0 1 1 1 1 1 1
|
||||
// HBIL 1 1 1 1 1 1 1 1
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 2: FIFORd
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data NO Data Activate NO Data Activate NO Data NO Data
|
||||
// NextData SameData SameData SameData SameData SameData NextData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 IF Wait 1
|
||||
// Term A TCXpire
|
||||
// LFunc AND
|
||||
// Term B TCXpire
|
||||
// Branch1 ThenIdle
|
||||
// Branch0 Else 0
|
||||
// Re-Exec No
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// HR/W* 1 1 1 1 1 1 1 1
|
||||
// HDS1* 1 0 1 0 1 1 1 1
|
||||
// HBIL 0 0 1 1 1 1 1 1
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 3: FIFOWr
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data Activate NO Data Activate NO Data NO Data NO Data
|
||||
// NextData SameData SameData NextData SameData NextData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 IF Wait 1
|
||||
// Term A TCXpire
|
||||
// LFunc AND
|
||||
// Term B TCXpire
|
||||
// Branch1 ThenIdle
|
||||
// Branch0 Else 0
|
||||
// Re-Exec No
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// HR/W* 0 0 0 0 0 1 1 1
|
||||
// HDS1* 1 0 1 0 1 1 1 1
|
||||
// HBIL 0 0 1 1 1 1 1 1
|
||||
// CTL3 0 0 0 0 0 0 0 0
|
||||
// CTL4 0 0 0 0 0 0 0 0
|
||||
// CTL5 0 0 0 0 0 0 0 0
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
|
||||
// GPIF Program Code
|
||||
|
||||
// DO NOT EDIT ...
|
||||
#include "fx2.h"
|
||||
#include "fx2regs.h"
|
||||
#include "fx2sdly.h" // SYNCDELAY macro
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char xdata WaveData[128] =
|
||||
{
|
||||
// Wave 0
|
||||
/* LenBr */ 0x01, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* Output*/ 0x02, 0x00, 0x02, 0x02, 0x02, 0x02, 0x02, 0x07,
|
||||
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
// Wave 1
|
||||
/* LenBr */ 0x01, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* Output*/ 0x06, 0x04, 0x06, 0x06, 0x06, 0x06, 0x06, 0x07,
|
||||
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
// Wave 2
|
||||
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x38, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x00, 0x02, 0x00, 0x02, 0x05, 0x00, 0x00,
|
||||
/* Output*/ 0x03, 0x01, 0x07, 0x05, 0x07, 0x07, 0x07, 0x07,
|
||||
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x2D, 0x00, 0x3F,
|
||||
// Wave 3
|
||||
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x38, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x02, 0x04, 0x02, 0x04, 0x01, 0x00, 0x00,
|
||||
/* Output*/ 0x02, 0x00, 0x06, 0x04, 0x06, 0x07, 0x07, 0x07,
|
||||
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x2D, 0x00, 0x3F,
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char xdata FlowStates[36] =
|
||||
{
|
||||
/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
/* Wave 2 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
/* Wave 3 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char xdata InitData[7] =
|
||||
{
|
||||
/* Regs */ 0xE0,0x00,0x00,0x07,0xCE,0x4E,0x00
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// TO DO: You may add additional code below.
|
||||
|
||||
void GpifInit( void )
|
||||
{
|
||||
BYTE i;
|
||||
|
||||
// Registers which require a synchronization delay, see section 15.14
|
||||
// FIFORESET FIFOPINPOLAR
|
||||
// INPKTEND OUTPKTEND
|
||||
// EPxBCH:L REVCTL
|
||||
// GPIFTCB3 GPIFTCB2
|
||||
// GPIFTCB1 GPIFTCB0
|
||||
// EPxFIFOPFH:L EPxAUTOINLENH:L
|
||||
// EPxFIFOCFG EPxGPIFFLGSEL
|
||||
// PINFLAGSxx EPxFIFOIRQ
|
||||
// EPxFIFOIE GPIFIRQ
|
||||
// GPIFIE GPIFADRH:L
|
||||
// UDMACRCH:L EPxGPIFTRIG
|
||||
// GPIFTRIG
|
||||
|
||||
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
|
||||
// ...these have been replaced by GPIFTC[B3:B0] registers
|
||||
|
||||
// 8051 doesn't have access to waveform memories 'til
|
||||
// the part is in GPIF mode.
|
||||
|
||||
IFCONFIG = 0xCE;
|
||||
// IFCLKSRC=1 , FIFOs executes on internal clk source
|
||||
// xMHz=1 , 48MHz internal clk rate
|
||||
// IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
|
||||
// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
|
||||
// ASYNC=1 , master samples asynchronous
|
||||
// GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
|
||||
// IFCFG[1:0]=10, FX2 in GPIF master mode
|
||||
|
||||
GPIFABORT = 0xFF; // abort any waveforms pending
|
||||
|
||||
GPIFREADYCFG = InitData[ 0 ];
|
||||
GPIFCTLCFG = InitData[ 1 ];
|
||||
GPIFIDLECS = InitData[ 2 ];
|
||||
GPIFIDLECTL = InitData[ 3 ];
|
||||
GPIFWFSELECT = InitData[ 5 ];
|
||||
GPIFREADYSTAT = InitData[ 6 ];
|
||||
|
||||
// use dual autopointer feature...
|
||||
AUTOPTRSETUP = 0x07; // inc both pointers,
|
||||
// ...warning: this introduces pdata hole(s)
|
||||
// ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
|
||||
|
||||
// source
|
||||
AUTOPTRH1 = MSB( &WaveData );
|
||||
AUTOPTRL1 = LSB( &WaveData );
|
||||
|
||||
// destination
|
||||
AUTOPTRH2 = 0xE4;
|
||||
AUTOPTRL2 = 0x00;
|
||||
|
||||
// transfer
|
||||
for ( i = 0x00; i < 128; i++ )
|
||||
{
|
||||
EXTAUTODAT2 = EXTAUTODAT1;
|
||||
}
|
||||
|
||||
// Configure GPIF Address pins, output initial value,
|
||||
PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
|
||||
OEC = 0xFF; // and as outputs
|
||||
PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
|
||||
OEE |= 0x80; // and as output
|
||||
|
||||
// ...OR... tri-state GPIFADR[8:0] pins
|
||||
// PORTCCFG = 0x00; // [7:0] as port I/O
|
||||
// OEC = 0x00; // and as inputs
|
||||
// PORTECFG &= 0x7F; // [8] as port I/O
|
||||
// OEE &= 0x7F; // and as input
|
||||
|
||||
// GPIF address pins update when GPIFADRH/L written
|
||||
SYNCDELAY; //
|
||||
GPIFADRH = 0x00; // bits[7:1] always 0
|
||||
SYNCDELAY; //
|
||||
GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
|
||||
|
||||
// Configure GPIF FlowStates registers for Wave 0 of WaveData
|
||||
FLOWSTATE = FlowStates[ 0 ];
|
||||
FLOWLOGIC = FlowStates[ 1 ];
|
||||
FLOWEQ0CTL = FlowStates[ 2 ];
|
||||
FLOWEQ1CTL = FlowStates[ 3 ];
|
||||
FLOWHOLDOFF = FlowStates[ 4 ];
|
||||
FLOWSTB = FlowStates[ 5 ];
|
||||
FLOWSTBEDGE = FlowStates[ 6 ];
|
||||
FLOWSTBHPERIOD = FlowStates[ 7 ];
|
||||
}
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
#include "fx2.h"
|
||||
#include "fx2regs.h"
|
||||
|
||||
extern BOOL hpi_int;
|
||||
|
||||
void int0_isr (void) interrupt 0
|
||||
{
|
||||
hpi_int = TRUE; // HPI interrupted the FX2
|
||||
EX0 = 0; // disable INT0/ interrupt, let foreground re-enable it
|
||||
}
|
||||
@@ -0,0 +1,6 @@
|
||||
readme.txt for FX2_to_TI5416 GPIF FIFO Transactions Auto mode
|
||||
-------------------------------------------------------------
|
||||
|
||||
see GPIF Primer section on design examples for operating instructions
|
||||
and details
|
||||
|
||||
@@ -0,0 +1,292 @@
|
||||
// This program configures the General Programmable Interface (GPIF) for FX2.
|
||||
// Please do not modify sections of text which are marked as "DO NOT EDIT ...".
|
||||
//
|
||||
// DO NOT EDIT ...
|
||||
// GPIF Initialization
|
||||
// Interface Timing Async
|
||||
// Internal Ready Init IntRdy=1
|
||||
// CTL Out Tristate-able Tristate
|
||||
// SingleWrite WF Select 3
|
||||
// SingleRead WF Select 2
|
||||
// FifoWrite WF Select 1
|
||||
// FifoRead WF Select 0
|
||||
// Data Bus Idle Drive Tristate
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
// GPIF Wave Names
|
||||
// Wave 0 = FIFORd
|
||||
// Wave 1 = FIFOWr
|
||||
// Wave 2 = SnglWr2
|
||||
// Wave 3 = SnglWr1
|
||||
|
||||
// GPIF Ctrl Outputs Level
|
||||
// CTL 0 = HR/W* CMOS
|
||||
// CTL 1 = HDS1* CMOS
|
||||
// CTL 2 = HBIL CMOS
|
||||
// CTL 3 = unused CMOS
|
||||
// CTL 4 = unused CMOS
|
||||
// CTL 5 = unused CMOS
|
||||
|
||||
// GPIF Rdy Inputs
|
||||
// RDY0 = HRDY*
|
||||
// RDY1 = unused
|
||||
// RDY2 = unused
|
||||
// RDY3 = unused
|
||||
// RDY4 = unused
|
||||
// RDY5 = TCXpire
|
||||
// FIFOFlag = FIFOFlag
|
||||
// IntReady = IntReady
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 0: FIFORd
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data NO Data Activate NO Data Activate NO Data NO Data
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 IF Wait 3
|
||||
// Term A TCXpire
|
||||
// LFunc AND
|
||||
// Term B TCXpire
|
||||
// Branch1 ThenIdle
|
||||
// Branch0 Else 0
|
||||
// Re-Exec No
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// HR/W* 1 1 1 1 1 1 1 1
|
||||
// HDS1* 1 0 1 0 0 0 1 1
|
||||
// HBIL 0 0 1 1 1 1 1 1
|
||||
// unused 1 1 1 1 1 1 1 1
|
||||
// unused
|
||||
// unused
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 1: FIFOWr
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data Activate NO Data Activate NO Data NO Data NO Data
|
||||
// NextData SameData SameData NextData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 IF Wait 1
|
||||
// Term A TCXpire
|
||||
// LFunc AND
|
||||
// Term B TCXpire
|
||||
// Branch1 ThenIdle
|
||||
// Branch0 Else 0
|
||||
// Re-Exec No
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// HR/W* 0 0 0 0 0 1 1 1
|
||||
// HDS1* 1 0 1 0 1 1 1 1
|
||||
// HBIL 0 0 1 1 1 1 1 1
|
||||
// unused 1 1 1 1 1 1 1 1
|
||||
// unused
|
||||
// unused
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 2: SnglWr2
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data Activate NO Data NO Data NO Data NO Data NO Data
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A unused
|
||||
// LFunc AND
|
||||
// Term B unused
|
||||
// Branch1 ThenIdle
|
||||
// Branch0 ElseIdle
|
||||
// Re-Exec No
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// HR/W* 0 0 0 0 0 0 0 1
|
||||
// HDS1* 1 0 1 0 1 1 1 1
|
||||
// HBIL 1 1 1 1 1 1 1 1
|
||||
// unused 1 1 1 1 1 1 1 1
|
||||
// unused
|
||||
// unused
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
// DO NOT EDIT ...
|
||||
//
|
||||
// GPIF Waveform 3: SnglWr1
|
||||
//
|
||||
// Interval 0 1 2 3 4 5 6 Idle (7)
|
||||
// _________ _________ _________ _________ _________ _________ _________ _________
|
||||
//
|
||||
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
|
||||
// DataMode NO Data Activate NO Data NO Data NO Data NO Data NO Data
|
||||
// NextData SameData SameData SameData SameData SameData SameData SameData
|
||||
// Int Trig No Int No Int No Int No Int No Int No Int No Int
|
||||
// IF/Wait Wait 1 Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1
|
||||
// Term A unused
|
||||
// LFunc AND
|
||||
// Term B unused
|
||||
// Branch1 ThenIdle
|
||||
// Branch0 ElseIdle
|
||||
// Re-Exec No
|
||||
// Sngl/CRC Default Default Default Default Default Default Default
|
||||
// HR/W* 0 0 0 0 0 0 0 1
|
||||
// HDS1* 1 0 1 0 1 1 1 1
|
||||
// HBIL 0 0 0 1 1 1 1 1
|
||||
// unused 1 1 1 1 1 1 1 1
|
||||
// unused
|
||||
// unused
|
||||
//
|
||||
// END DO NOT EDIT
|
||||
|
||||
// GPIF Program Code
|
||||
|
||||
// DO NOT EDIT ...
|
||||
#include "fx2.h"
|
||||
#include "fx2regs.h"
|
||||
#include "fx2sdly.h" // SYNCDELAY macro
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char xdata WaveData[128] =
|
||||
{
|
||||
// Wave 0
|
||||
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x38, 0x03, 0x07,
|
||||
/* Opcode*/ 0x00, 0x00, 0x02, 0x00, 0x02, 0x01, 0x00, 0x00,
|
||||
/* Output*/ 0xFB, 0xF9, 0xFF, 0xFD, 0xFD, 0xFD, 0xFF, 0xFF,
|
||||
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x2D, 0x00, 0x3F,
|
||||
// Wave 1
|
||||
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x38, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x02, 0x04, 0x02, 0x00, 0x01, 0x00, 0x00,
|
||||
/* Output*/ 0xFA, 0xF8, 0xFE, 0xFC, 0xFE, 0xFF, 0xFF, 0xFF,
|
||||
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x2D, 0x00, 0x3F,
|
||||
// Wave 2
|
||||
/* LenBr */ 0x01, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* Output*/ 0xFE, 0xFC, 0xFE, 0xFC, 0xFE, 0xFE, 0xFE, 0xFF,
|
||||
/* LFun */ 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
// Wave 3
|
||||
/* LenBr */ 0x01, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x07,
|
||||
/* Opcode*/ 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/* Output*/ 0xFA, 0xF8, 0xFA, 0xFC, 0xFE, 0xFE, 0xFE, 0xFF,
|
||||
/* LFun */ 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x3F,
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char xdata FlowStates[36] =
|
||||
{
|
||||
/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
/* Wave 2 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
/* Wave 3 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// DO NOT EDIT ...
|
||||
const char xdata InitData[7] =
|
||||
{
|
||||
/* Regs */ 0xA0,0x80,0x00,0xFF,0xEA,0xE4,0x00
|
||||
};
|
||||
// END DO NOT EDIT
|
||||
|
||||
// TO DO: You may add additional code below.
|
||||
|
||||
void GpifInit( void )
|
||||
{
|
||||
BYTE i;
|
||||
|
||||
// Registers which require a synchronization delay, see section 15.14
|
||||
// FIFORESET FIFOPINPOLAR
|
||||
// INPKTEND OUTPKTEND
|
||||
// EPxBCH:L REVCTL
|
||||
// GPIFTCB3 GPIFTCB2
|
||||
// GPIFTCB1 GPIFTCB0
|
||||
// EPxFIFOPFH:L EPxAUTOINLENH:L
|
||||
// EPxFIFOCFG EPxGPIFFLGSEL
|
||||
// PINFLAGSxx EPxFIFOIRQ
|
||||
// EPxFIFOIE GPIFIRQ
|
||||
// GPIFIE GPIFADRH:L
|
||||
// UDMACRCH:L EPxGPIFTRIG
|
||||
// GPIFTRIG
|
||||
|
||||
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
|
||||
// ...these have been replaced by GPIFTC[B3:B0] registers
|
||||
|
||||
// 8051 doesn't have access to waveform memories 'til
|
||||
// the part is in GPIF mode.
|
||||
|
||||
IFCONFIG = 0xEA;
|
||||
// IFCLKSRC=1 , FIFOs executes on internal clk source
|
||||
// xMHz=1 , 48MHz internal clk rate
|
||||
// IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
|
||||
// IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
|
||||
// ASYNC=1 , master samples asynchronous
|
||||
// GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
|
||||
// IFCFG[1:0]=10, FX2 in GPIF master mode
|
||||
|
||||
GPIFABORT = 0xFF; // abort any waveforms pending
|
||||
|
||||
GPIFREADYCFG = InitData[ 0 ];
|
||||
GPIFCTLCFG = InitData[ 1 ];
|
||||
GPIFIDLECS = InitData[ 2 ];
|
||||
GPIFIDLECTL = InitData[ 3 ];
|
||||
GPIFWFSELECT = InitData[ 5 ];
|
||||
GPIFREADYSTAT = InitData[ 6 ];
|
||||
|
||||
// use dual autopointer feature...
|
||||
AUTOPTRSETUP = 0x07; // inc both pointers,
|
||||
// ...warning: this introduces pdata hole(s)
|
||||
// ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
|
||||
|
||||
// source
|
||||
AUTOPT1RH = MSB( &WaveData );
|
||||
AUTOPT1RL = LSB( &WaveData );
|
||||
|
||||
// destination
|
||||
AUTOPTRH2 = 0xE4;
|
||||
AUTOPTRL2 = 0x00;
|
||||
|
||||
// transfer
|
||||
for ( i = 0x00; i < 128; i++ )
|
||||
{
|
||||
EXTAUTODAT2 = EXTAUTODAT1;
|
||||
}
|
||||
|
||||
// Configure GPIF Address pins, output initial value,
|
||||
PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
|
||||
OEC = 0xFF; // and as outputs
|
||||
PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
|
||||
OEE |= 0x80; // and as output
|
||||
|
||||
// ...OR... tri-state GPIFADR[8:0] pins
|
||||
// PORTCCFG = 0x00; // [7:0] as port I/O
|
||||
// OEC = 0x00; // and as inputs
|
||||
// PORTECFG &= 0x7F; // [8] as port I/O
|
||||
// OEE &= 0x7F; // and as input
|
||||
|
||||
// GPIF address pins update when GPIFADRH/L written
|
||||
SYNCDELAY; //
|
||||
GPIFADRH = 0x00; // bits[7:1] always 0
|
||||
SYNCDELAY; //
|
||||
GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
|
||||
|
||||
// Configure GPIF FlowStates registers for Wave 0 of WaveData
|
||||
FLOWSTATE = FlowStates[ 0 ];
|
||||
FLOWLOGIC = FlowStates[ 1 ];
|
||||
FLOWEQ0CTL = FlowStates[ 2 ];
|
||||
FLOWEQ1CTL = FlowStates[ 3 ];
|
||||
FLOWHOLDOFF = FlowStates[ 4 ];
|
||||
FLOWSTB = FlowStates[ 5 ];
|
||||
FLOWSTBEDGE = FlowStates[ 6 ];
|
||||
FLOWSTBHPERIOD = FlowStates[ 7 ];
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user