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-I
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./inc
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#ifndef FX2_H
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#define FX2_H
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// ----------------------------------------------------------------------------
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// Constants
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// ----------------------------------------------------------------------------
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#define TRUE 1
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#define FALSE 0
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#define true 1
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#define false 0
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typedef unsigned char bool;
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typedef unsigned char BYTE;
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typedef unsigned short WORD;
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typedef unsigned long DWORD;
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#define DSCR_DEVICE 1 // Descriptor type: Device
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#define DSCR_CONFIG 2 // Descriptor type: Configuration
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#define DSCR_STRING 3 // Descriptor type: String
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#define DSCR_INTRFC 4 // Descriptor type: Interface
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#define DSCR_ENDPNT 5 // Descriptor type: Endpoint
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#define DSCR_DEVQUAL 6 // Descriptor type: Device Qualifier
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#define DSCR_OTHERSPEED 7 // Descriptor type: Other Speed Configuration
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#define bmBIT0 0x01
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#define bmBIT1 0x02
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#define bmBIT2 0x04
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#define bmBIT3 0x08
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#define bmBIT4 0x10
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#define bmBIT5 0x20
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#define bmBIT6 0x40
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#define bmBIT7 0x80
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#define bmBUSPWR bmBIT7
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#define bmSELFPWR bmBIT6
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#define bmRWU bmBIT5
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#define bmEPOUT bmBIT7
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#define bmEPIN 0
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#define EP_VALID 0x80
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#define EP_INVALID 0x00
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#define EP_IN 0x40
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#define EP_OUT 0x00
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#define EP_INT 0x30
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#define EP_BULK 0x20
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#define EP_ISO 0x10
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#define EP_1024 0x08
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#define EP_512 0x00
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#define EP_64 0x00
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#define EP_3x 0x03
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#define EP_2x 0x02
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#define EP_4x 0x00
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#define IRQ_EP0IN bmBIT0
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#define IRQ_EP0OUT bmBIT1
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#define IRQ_EP1IN bmBIT2
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#define IRQ_EP1OUT bmBIT3
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#define IRQ_EP2 bmBIT4
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#define IRQ_EP4 bmBIT5
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#define IRQ_EP6 bmBIT6
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#define IRQ_EP8 bmBIT7
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#define SUD_SIZE 8 // Setup data size
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#define VECT_INT0 0
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#define VECT_TMR0 1
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#define VECT_INT1 2
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#define VECT_TMR1 3
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#define VECT_COM0 4
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#define VECT_TMR2 5
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#define VECT_WKUP 6
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#define VECT_COM1 7
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#define VECT_USB 8
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#define VECT_I2C 9
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#define VECT_INT4 10
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#define VECT_INT5 11
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#define VECT_INT6 12
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// ----------------------------------------------------------------------------
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// USB interrupt INT2IVEC values
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// ----------------------------------------------------------------------------
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#define INT2_SUDAV 0x00
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#define INT2_SOF 0x04
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#define INT2_SUTOK 0x08
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#define INT2_SUSPEND 0x0C
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#define INT2_RESET 0x10
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#define INT2_HISPEED 0x14
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#define INT2_EP0ACK 0x18
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#define INT2_EP0IN 0x20
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#define INT2_EP0OUT 0x24
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#define INT2_EP1IN 0x28
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#define INT2_EP1OUT 0x2C
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#define INT2_EP2 0x30
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#define INT2_EP4 0x34
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#define INT2_EP6 0x38
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#define INT2_EP8 0x3C
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#define INT2_IBN 0x40
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#define INT2_EP0PING 0x48
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#define INT2_EP1PING 0x4C
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#define INT2_EP2PING 0x50
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#define INT2_EP4PING 0x54
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#define INT2_EP6PING 0x58
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#define INT2_EP8PING 0x5C
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#define INT2_ERRLIMIT 0x60
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#define INT2_EP2ISOERR 0x70
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#define INT2_EP4ISOERR 0x74
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#define INT2_EP6ISOERR 0x78
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#define INT2_EP8ISOERR 0x7C
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// ----------------------------------------------------------------------------
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// GPIF/FIFO interrupt INT4IVEC values
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// ----------------------------------------------------------------------------
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#define INT4_EP2PF 0x80
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#define INT4_EP4PF 0x84
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#define INT4_EP6PF 0x88
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#define INT4_EP8PF 0x8C
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#define INT4_EP2EF 0x90
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#define INT4_EP4EF 0x94
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#define INT4_EP6EF 0x98
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#define INT4_EP8EF 0x9C
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#define INT4_EP2FF 0xA0
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#define INT4_EP4FF 0xA4
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#define INT4_EP6FF 0xA8
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#define INT4_EP8FF 0xAC
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#define INT4_GPIF_DONE 0xB0
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#define INT4_GPIF_WF 0xB4
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// ----------------------------------------------------------------------------
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// HID constants
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// ----------------------------------------------------------------------------
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#define SETUP_MASK 0x60 // Used to mask off request type
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#define SETUP_REQ_STANDARD 0x00 // Standard request
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#define SETUP_REQ_CLASS 0x20 // Class request
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#define SETUP_REQ_VENDOR 0x40 // Vendor request
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#define SETUP_REQ_RESERVED 0x60 // Reserved or illegal request
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// ----------------------------------------------------------------------------
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// Setup commands
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// ----------------------------------------------------------------------------
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#define SC_GET_STATUS 0x00
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#define SC_CLEAR_FEATURE 0x01
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#define SC_RESERVED 0x02
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#define SC_SET_FEATURE 0x03
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#define SC_SET_ADDRESS 0x05
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#define SC_GET_DESCRIPTOR 0x06
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#define SC_SET_DESCRIPTOR 0x07
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#define SC_GET_CONFIGURATION 0x08
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#define SC_SET_CONFIGURATION 0x09
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#define SC_GET_INTERFACE 0x0a
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#define SC_SET_INTERFACE 0x0b
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#define SC_SYNC_FRAME 0x0c
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#define SC_ANCHOR_LOAD 0xa0
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#define GD_DEVICE 0x01
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#define GD_CONFIGURATION 0x02
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#define GD_STRING 0x03
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#define GD_INTERFACE 0x04
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#define GD_ENDPOINT 0x05
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#define GD_DEVICE_QUALIFIER 0x06
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#define GD_OTHER_SPEED_CONFIG 0x07
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#define GD_INTERFACE_POWER 0x08
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#define GD_HID 0x21
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#define GD_REPORT 0x22
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#define GS_DEVICE 0x80 // Get Status: Device
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#define GS_INTERFACE 0x81 // Get Status: Interface
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#define GS_ENDPOINT 0x82 // Get Status: Endpoint
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#define FT_DEVICE 0x00 // Feature: Device
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#define FT_ENDPOINT 0x02 // Feature: Endpoint
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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// Data types
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ----------------------------------------------------------------------------
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// Descriptor header
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// ----------------------------------------------------------------------------
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typedef struct
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{
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BYTE length;
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BYTE type;
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} DSCR;
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// ----------------------------------------------------------------------------
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// Device descriptor [type=1]
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// ----------------------------------------------------------------------------
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typedef struct
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{
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BYTE length; // descriptor length ( = sizeof(DEVICE_DSCR) )
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BYTE type; // descriptor type ( Device = 1)
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BYTE spec_ver_minor; // specification version (BCD) minor
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BYTE spec_ver_major; // specification version (BCD) major
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BYTE dev_class; // device class
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BYTE dev_subclass; // device subclass
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BYTE dev_protocol; // device protocol
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BYTE max_packet; // maximum packet size
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WORD id_vendor; // vendor ID
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WORD id_product; // product ID
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WORD id_version; // product version ID
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BYTE str_manufacturer; // manufacturer string index
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BYTE str_product; // product string index
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BYTE str_serial; // serial number string index
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BYTE configs; // number of configurations
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} DEVICE_DSCR;
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// ----------------------------------------------------------------------------
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// Device qualifier descriptor [type=6]
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// ----------------------------------------------------------------------------
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typedef struct
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{
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BYTE length; // descriptor length ( = sizeof(DEVICEQUAL_DSCR) )
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BYTE type; // descriptor type ( Device Qualifier = 6)
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BYTE spec_ver_minor; // specification version (BCD) minor
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BYTE spec_ver_major; // specification version (BCD) major
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BYTE dev_class; // device class
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BYTE dev_subclass; // device subclass
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BYTE dev_protocol; // device protocol
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BYTE max_packet; // maximum packet size
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BYTE configs; // number of configurations
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BYTE reserved;
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} DEVICEQUAL_DSCR;
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// ----------------------------------------------------------------------------
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// Configuration descriptor [type=2]
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// ----------------------------------------------------------------------------
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typedef struct
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{
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BYTE length; // descriptor length ( = sizeof(CONFIG_DSCR) )
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BYTE type; // descriptor type ( Configuration = 2)
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WORD config_length; // configuration + endpoints length
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BYTE interfaces; // number of interfaces
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BYTE index; // configuration number
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BYTE str_config; // configuration string index
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BYTE attrib; // attributes (buspwr,selfpwr,rwu)
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BYTE power; // power requirement (div 2 mA)
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} CONFIG_DSCR;
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// ----------------------------------------------------------------------------
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// Interface descriptor [type=4]
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// ----------------------------------------------------------------------------
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typedef struct
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{
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BYTE length; // descriptor length ( = sizeof(INTERFACE_DSCR) )
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BYTE type; // descriptor type ( Interface = 4)
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BYTE index; // zero-based index of this interface
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BYTE alt_setting; // alternate setting
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BYTE ep_count; // number of endpoints
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BYTE if_class; // interface class
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BYTE if_subclass; // interface subclass
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BYTE if_protocol; // interface protocol
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BYTE str_interface; // interface string index
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} INTERFACE_DSCR;
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// ----------------------------------------------------------------------------
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// Endpoint descriptor [type=5]
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// ----------------------------------------------------------------------------
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typedef struct
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{
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BYTE length; // descriptor length ( = sizeof(ENDPOINT_DSCR) )
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BYTE type; // descriptor type ( Endpoint = 5)
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BYTE ep_address; // endpoint address
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BYTE ep_type; // endpoint type
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BYTE mp_low; // maximum packet size (LOW)
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BYTE mp_high; // maximum packet size (HIGH)
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BYTE interval; // interrupt polling interval
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} ENDPOINT_DSCR;
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// ----------------------------------------------------------------------------
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// String descriptor [type=3]
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// ----------------------------------------------------------------------------
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typedef struct
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{
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BYTE length; // descriptor length ( = sizeof(STRING_DSCR) )
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BYTE type; // descriptor type ( String = 3)
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} STRING_DSCR;
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// ----------------------------------------------------------------------------
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// Setup Data Valid structure
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// ----------------------------------------------------------------------------
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typedef struct SUDAV
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{
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BYTE RequestType;
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BYTE Request;
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union
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{
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WORD Word;
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struct
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{
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BYTE Hi;
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BYTE Lo;
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} Byte;
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} Value;
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union
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{
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WORD Word;
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struct
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{
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BYTE Hi;
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BYTE Lo;
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} Byte;
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} Index;
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} SUDAV;
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typedef SUDAV xdata* PSUDAV;
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// ----------------------------------------------------------------------------
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// Macros
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// ----------------------------------------------------------------------------
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#define min(a,b) (((a)<(b))?(a):(b))
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#define max(a,b) (((a)>(b))?(a):(b))
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#define MSB(word) (BYTE)(((WORD)(word) >> 8) & 0xff)
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#define LSB(word) (BYTE)(((WORD)(word) >> 0) & 0xff)
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#define SWAP(word) ((BYTE*)&word)[0] ^= ((BYTE*)&word)[1]; \
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((BYTE*)&word)[1] ^= ((BYTE*)&word)[0]; \
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((BYTE*)&word)[0] ^= ((BYTE*)&word)[1]
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#define I2C_IRQ_ENABLE() (EI2C = 1)
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#define I2C_IRQ_DISABLE() (EI2C = 0)
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#define I2C_IRQ_CLEAR() (EXIF &= ~0x20)
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#define I2C_IRQ_FIRE() (EXIF |= 0x20)
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#define USB_IRQ_ENABLE() EUSB = 1
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#define USB_IRQ_DISABLE() EUSB = 0
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#define USB_IRQ_CLEAR() EXIF &= ~0x10
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#define USB_IRQ_CLEAR_EP0IN() EPIRQ = IRQ_EP0IN
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#define USB_IRQ_CLEAR_EP0OUT() EPIRQ = IRQ_EP0OUT
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#define USB_IRQ_CLEAR_EP1IN() EPIRQ = IRQ_EP1IN
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#define USB_IRQ_CLEAR_EP1OUT() EPIRQ = IRQ_EP1OUT
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#define USB_IRQ_CLEAR_EP2() EPIRQ = IRQ_EP2
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#define USB_IRQ_CLEAR_EP4() EPIRQ = IRQ_EP4
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#define USB_IRQ_CLEAR_EP6() EPIRQ = IRQ_EP6
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#define USB_IRQ_CLEAR_EP8() EPIRQ = IRQ_EP8
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#define FX2_TOG_CLEAR( a) TOGCTL = a & 0x1F; TOGCTL = (a | 0x20) & 0x3F
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#define RSM_IRQ_ENABLE() (EICON |= 0x20)
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#define RSM_IRQ_DISABLE() (EICON &= ~0x20)
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#define RSM_IRQ_CLEAR() (EICON &= ~0x10)
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#define FX2_STALL_EP0() EP0CS |= bmEPSTALL
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#define FX2_STALL_EP1IN() EP1INCS |= bmEPSTALL
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#define FX2_STALL_EP1OUT() EP1OUTCS |= bmEPSTALL
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#define FX2_STALL_EP2() EP2CS |= bmEPSTALL
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#define FX2_STALL_EP4() EP4CS |= bmEPSTALL
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#define FX2_STALL_EP6() EP6CS |= bmEPSTALL
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#define FX2_STALL_EP8() EP8CS |= bmEPSTALL
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extern const DEVICE_DSCR code DscrDevice;
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extern const DEVICEQUAL_DSCR code DscrDeviceQual;
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extern const CONFIG_DSCR code DscrHsConfig;
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extern const CONFIG_DSCR code DscrFsConfig;
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extern const STRING_DSCR code DscrString;
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extern void FX2_Disconnect(bool renum);
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extern void FX2_Delay(WORD ms);
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extern bool FX2_Init();
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extern void FX2_Suspend();
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extern void FX2_Resume();
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#endif
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@@ -0,0 +1,14 @@
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#ifndef FX2_EEPROM_H
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#define FX2_EEPROM_H
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#include <fx2.h>
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extern BYTE FX2_EEPROM_Read( WORD page, BYTE offset, BYTE length, BYTE xdata *dat);
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extern BYTE FX2_EEPROM_Write( WORD page, BYTE offset, BYTE length, BYTE xdata *dat);
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extern BYTE FX2_EEPROM_ReadPage( WORD page, BYTE length, BYTE xdata *dat);
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extern BYTE FX2_EEPROM_WritePage( WORD page, BYTE length, BYTE xdata *dat);
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extern BYTE FX2_EEPROM_ReadPage0( BYTE addr, BYTE length, BYTE xdata *dat);
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extern BYTE FX2_EEPROM_WritePage0( BYTE addr, BYTE length, BYTE xdata *dat);
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#endif
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@@ -0,0 +1,19 @@
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#ifndef FX2_GLOBALS_H
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#define FX2_GLOBALS_H
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#include <fx2.h>
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extern xdata bool Sleep;
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extern xdata bool GotSUD;
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extern xdata bool Rwuen;
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extern xdata bool SelfPower;
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||||
extern bool (*fx2_ep0_hook)();
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extern bool (*fx2_ep1_hook)();
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extern bool (*fx2_ep2_hook)();
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extern bool (*fx2_ep4_hook)();
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extern bool (*fx2_ep6_hook)();
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extern bool (*fx2_ep8_hook)();
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#endif
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@@ -0,0 +1,7 @@
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#ifndef FX2_GPIF_H
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||||
#define FX2_GPIF_H
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||||
|
||||
extern void fx2_gpif_init();
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extern void fx2_gpif_flowstate( int sel);
|
||||
|
||||
#endif
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@@ -0,0 +1,68 @@
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#ifndef FX2_IIC_H
|
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#define FX2_IIC_H
|
||||
|
||||
#include <fx2.h>
|
||||
|
||||
// I2C error codes
|
||||
// -----------------------------------------------------------------------------
|
||||
#define I2C_OK 0x00
|
||||
#define I2C_ERROR 0x80
|
||||
#define I2C_ABORT 0xFF
|
||||
#define SMB_ERROR 0xC0
|
||||
|
||||
|
||||
// I2C state machine states
|
||||
// -----------------------------------------------------------------------------
|
||||
#define I2C_IDLE 0x00
|
||||
#define I2C_SENDING 0x01
|
||||
#define I2C_RECEIVING 0x02
|
||||
#define I2C_PRIME 0x03
|
||||
#define I2C_BERROR 0x04
|
||||
#define I2C_NACK 0x05
|
||||
#define I2C_STOP 0x06
|
||||
#define I2C_WAITSTOP 0x07
|
||||
|
||||
|
||||
// I2C state machine states for read operation with repeated start condition
|
||||
// -----------------------------------------------------------------------------
|
||||
#define I2C_SUBADDR_HI 0x10 // sending HI(subaddr)
|
||||
#define I2C_SUBADDR_LO 0x11 // sending LO(subaddr)
|
||||
#define I2C_RESTART 0x12 //
|
||||
|
||||
|
||||
// SMBus state machine states
|
||||
// -----------------------------------------------------------------------------
|
||||
#define SMB_SENDING 0x40
|
||||
#define SMB_RECEIVING 0x41
|
||||
#define SMB_PRIME 0x43
|
||||
#define SMB_BERROR 0x44
|
||||
#define SMB_NACK 0x45
|
||||
#define SMB_STOP 0x46
|
||||
#define SMB_WAITSTOP 0x47
|
||||
#define SMB_PEC 0x48
|
||||
#define SMB_CMD_READWORD 0x50
|
||||
#define SMB_READWORD 0x51
|
||||
|
||||
|
||||
extern void fx2_i2c_init();
|
||||
|
||||
extern BYTE fx2_i2c_wait( BYTE addr);
|
||||
|
||||
extern BYTE fx2_i2c_read( BYTE addr,
|
||||
BYTE length,
|
||||
BYTE xdata *dat);
|
||||
|
||||
extern BYTE fx2_i2c_write( BYTE addr,
|
||||
BYTE length,
|
||||
BYTE xdata *dat);
|
||||
|
||||
extern BYTE fx2_i2c_read_rsw( BYTE addr,
|
||||
WORD subaddr,
|
||||
BYTE length,
|
||||
BYTE xdata *dat);
|
||||
|
||||
extern BYTE fx2_sm_readword( BYTE addr,
|
||||
BYTE command,
|
||||
BYTE xdata *dat);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,518 @@
|
||||
#ifndef FX2_REGS_H
|
||||
#define FX2_REGS_H
|
||||
|
||||
#ifdef ALLOCATE_EXTERN
|
||||
#define XBYTE( name, addr) xdata volatile unsigned char name _at_ addr
|
||||
#else
|
||||
#define XBYTE( name, addr) extern xdata volatile unsigned char name
|
||||
#endif
|
||||
|
||||
// ============================================================================
|
||||
// General configuration
|
||||
// ============================================================================
|
||||
XBYTE( CPUCS , 0xE600); // Control & Status
|
||||
XBYTE( IFCONFIG , 0xE601); // Interface Configuration
|
||||
XBYTE( PINFLAGSAB , 0xE602); // FIFO FLAGA and FLAGB Assignments
|
||||
XBYTE( PINFLAGSCD , 0xE603); // FIFO FLAGC and FLAGD Assignments
|
||||
XBYTE( FIFORESET , 0xE604); // Restore FIFOS to default state
|
||||
XBYTE( BREAKPT , 0xE605); // Breakpoint
|
||||
XBYTE( BPADDRH , 0xE606); // Breakpoint Address H
|
||||
XBYTE( BPADDRL , 0xE607); // Breakpoint Address L
|
||||
XBYTE( UART230 , 0xE608); // 230 Kbaud clock for T0,T1,T2
|
||||
XBYTE( FIFOPINPOLAR , 0xE609); // FIFO polarities
|
||||
XBYTE( REVID , 0xE60A); // Chip Revision
|
||||
XBYTE( REVCTL , 0xE60B); // Chip Revision Control
|
||||
|
||||
// ============================================================================
|
||||
// Endpoint configuration registers
|
||||
// ============================================================================
|
||||
XBYTE( EP1OUTCFG , 0xE610); // Endpoint 1-OUT Configuration
|
||||
XBYTE( EP1INCFG , 0xE611); // Endpoint 1-IN Configuration
|
||||
XBYTE( EP2CFG , 0xE612); // Endpoint 2 Configuration
|
||||
XBYTE( EP4CFG , 0xE613); // Endpoint 4 Configuration
|
||||
XBYTE( EP6CFG , 0xE614); // Endpoint 6 Configuration
|
||||
XBYTE( EP8CFG , 0xE615); // Endpoint 8 Configuration
|
||||
XBYTE( EP2FIFOCFG , 0xE618); // Endpoint 2 FIFO configuration
|
||||
XBYTE( EP4FIFOCFG , 0xE619); // Endpoint 4 FIFO configuration
|
||||
XBYTE( EP6FIFOCFG , 0xE61A); // Endpoint 6 FIFO configuration
|
||||
XBYTE( EP8FIFOCFG , 0xE61B); // Endpoint 8 FIFO configuration
|
||||
XBYTE( EP2AUTOINLENH , 0xE620); // Endpoint 2 Packet Length H (IN only)
|
||||
XBYTE( EP2AUTOINLENL , 0xE621); // Endpoint 2 Packet Length L (IN only)
|
||||
XBYTE( EP4AUTOINLENH , 0xE622); // Endpoint 4 Packet Length H (IN only)
|
||||
XBYTE( EP4AUTOINLENL , 0xE623); // Endpoint 4 Packet Length L (IN only)
|
||||
XBYTE( EP6AUTOINLENH , 0xE624); // Endpoint 6 Packet Length H (IN only)
|
||||
XBYTE( EP6AUTOINLENL , 0xE625); // Endpoint 6 Packet Length L (IN only)
|
||||
XBYTE( EP8AUTOINLENH , 0xE626); // Endpoint 8 Packet Length H (IN only)
|
||||
XBYTE( EP8AUTOINLENL , 0xE627); // Endpoint 8 Packet Length L (IN only)
|
||||
XBYTE( EP2FIFOPFH , 0xE630); // EP2 Programmable Flag trigger H
|
||||
XBYTE( EP2FIFOPFL , 0xE631); // EP2 Programmable Flag trigger L
|
||||
XBYTE( EP4FIFOPFH , 0xE632); // EP4 Programmable Flag trigger H
|
||||
XBYTE( EP4FIFOPFL , 0xE633); // EP4 Programmable Flag trigger L
|
||||
XBYTE( EP6FIFOPFH , 0xE634); // EP6 Programmable Flag trigger H
|
||||
XBYTE( EP6FIFOPFL , 0xE635); // EP6 Programmable Flag trigger L
|
||||
XBYTE( EP8FIFOPFH , 0xE636); // EP8 Programmable Flag trigger H
|
||||
XBYTE( EP8FIFOPFL , 0xE637); // EP8 Programmable Flag trigger L
|
||||
XBYTE( EP2ISOINPKTS , 0xE640); // EP2 (if ISO) IN Packets per frame (1-3)
|
||||
XBYTE( EP4ISOINPKTS , 0xE641); // EP4 (if ISO) IN Packets per frame (1-3)
|
||||
XBYTE( EP6ISOINPKTS , 0xE642); // EP6 (if ISO) IN Packets per frame (1-3)
|
||||
XBYTE( EP8ISOINPKTS , 0xE643); // EP8 (if ISO) IN Packets per frame (1-3)
|
||||
XBYTE( INPKTEND , 0xE648); // Force IN Packet End
|
||||
XBYTE( OUTPKTEND , 0xE649); // Force OUT Packet End
|
||||
|
||||
// ============================================================================
|
||||
// Interrupts
|
||||
// ============================================================================
|
||||
XBYTE( EP2FIFOIE , 0xE650); // Endpoint 2 Flag Interrupt Enable
|
||||
XBYTE( EP2FIFOIRQ , 0xE651); // Endpoint 2 Flag Interrupt Request
|
||||
XBYTE( EP4FIFOIE , 0xE652); // Endpoint 4 Flag Interrupt Enable
|
||||
XBYTE( EP4FIFOIRQ , 0xE653); // Endpoint 4 Flag Interrupt Request
|
||||
XBYTE( EP6FIFOIE , 0xE654); // Endpoint 6 Flag Interrupt Enable
|
||||
XBYTE( EP6FIFOIRQ , 0xE655); // Endpoint 6 Flag Interrupt Request
|
||||
XBYTE( EP8FIFOIE , 0xE656); // Endpoint 8 Flag Interrupt Enable
|
||||
XBYTE( EP8FIFOIRQ , 0xE657); // Endpoint 8 Flag Interrupt Request
|
||||
|
||||
XBYTE( IBNIE , 0xE658); // IN-BULK-NAK Interrupt Enable
|
||||
XBYTE( IBNIRQ , 0xE659); // IN-BULK-NAK interrupt Request
|
||||
|
||||
XBYTE( NAKIE , 0xE65A); // Endpoint Ping NAK interrupt Enable
|
||||
XBYTE( NAKIRQ , 0xE65B); // Endpoint Ping NAK interrupt Request
|
||||
|
||||
XBYTE( USBIE , 0xE65C); // USB Int Enables
|
||||
XBYTE( USBIRQ , 0xE65D); // USB Interrupt Requests
|
||||
|
||||
XBYTE( EPIE , 0xE65E); // Endpoint Interrupt Enables
|
||||
XBYTE( EPIRQ , 0xE65F); // Endpoint Interrupt Requests
|
||||
|
||||
XBYTE( GPIFIE , 0xE660); // GPIF Interrupt Enable
|
||||
XBYTE( GPIFIRQ , 0xE661); // GPIF Interrupt Request
|
||||
|
||||
XBYTE( USBERRIE , 0xE662); // USB Error Interrupt Enables
|
||||
XBYTE( USBERRIRQ , 0xE663); // USB Error Interrupt Requests
|
||||
XBYTE( ERRCNTLIM , 0xE664); // USB Error counter and limit
|
||||
|
||||
XBYTE( CLRERRCNT , 0xE665); // Clear Error Counter EC[3..0]
|
||||
|
||||
XBYTE( INT2IVEC , 0xE666); // Interupt 2 (USB) Autovector
|
||||
XBYTE( INT4IVEC , 0xE667); // Interupt 4 (FIFOS & GPIF) Autovector
|
||||
XBYTE( INTSETUP , 0xE668); // Interrupt 2&4 Setup
|
||||
|
||||
// ============================================================================
|
||||
// Input/Output
|
||||
// ============================================================================
|
||||
XBYTE( PORTACFG , 0xE670); // I/O Port A Alternate Configuration
|
||||
XBYTE( PORTCCFG , 0xE671); // I/O Port C Alternate Configuration
|
||||
XBYTE( PORTECFG , 0xE672); // I/O Port E Alternate Configuration
|
||||
|
||||
XBYTE( I2CS , 0xE678); // I2C Control & Status
|
||||
XBYTE( I2DAT , 0xE679); // I2C Data
|
||||
XBYTE( I2CTL , 0xE67A); // I2C Control
|
||||
|
||||
XBYTE( XAUTODAT1 , 0xE67B); // Autopointer1 MOVX access
|
||||
XBYTE( XAUTODAT2 , 0xE67C); // Autopointer2 MOVX access
|
||||
|
||||
// ============================================================================
|
||||
// USB Control
|
||||
// ============================================================================
|
||||
XBYTE( USBCS , 0xE680); // USB Control & Status
|
||||
XBYTE( SUSPEND , 0xE681); // Put chip into suspend
|
||||
XBYTE( WAKEUPCS , 0xE682); // Wakeup source and polarity
|
||||
XBYTE( TOGCTL , 0xE683); // Toggle Control
|
||||
XBYTE( USBFRAMEH , 0xE684); // USB Frame count H
|
||||
XBYTE( USBFRAMEL , 0xE685); // USB Frame count L
|
||||
XBYTE( MICROFRAME , 0xE686); // Microframe count, 0-7
|
||||
XBYTE( FNADDR , 0xE687); // USB Function address
|
||||
|
||||
// ============================================================================
|
||||
// Endpoints
|
||||
// ============================================================================
|
||||
XBYTE( EP0BCH , 0xE68A); // Endpoint 0 Byte Count H
|
||||
XBYTE( EP0BCL , 0xE68B); // Endpoint 0 Byte Count L
|
||||
XBYTE( EP1OUTBC , 0xE68D); // Endpoint 1 OUT Byte Count
|
||||
XBYTE( EP1INBC , 0xE68F); // Endpoint 1 IN Byte Count
|
||||
XBYTE( EP2BCH , 0xE690); // Endpoint 2 Byte Count H
|
||||
XBYTE( EP2BCL , 0xE691); // Endpoint 2 Byte Count L
|
||||
XBYTE( EP4BCH , 0xE694); // Endpoint 4 Byte Count H
|
||||
XBYTE( EP4BCL , 0xE695); // Endpoint 4 Byte Count L
|
||||
XBYTE( EP6BCH , 0xE698); // Endpoint 6 Byte Count H
|
||||
XBYTE( EP6BCL , 0xE699); // Endpoint 6 Byte Count L
|
||||
XBYTE( EP8BCH , 0xE69C); // Endpoint 8 Byte Count H
|
||||
XBYTE( EP8BCL , 0xE69D); // Endpoint 8 Byte Count L
|
||||
|
||||
XBYTE( EP0CS , 0xE6A0); // Endpoint Control and Status
|
||||
XBYTE( EP1OUTCS , 0xE6A1); // Endpoint 1 OUT Control and Status
|
||||
XBYTE( EP1INCS , 0xE6A2); // Endpoint 1 IN Control and Status
|
||||
XBYTE( EP2CS , 0xE6A3); // Endpoint 2 Control and Status
|
||||
XBYTE( EP4CS , 0xE6A4); // Endpoint 4 Control and Status
|
||||
XBYTE( EP6CS , 0xE6A5); // Endpoint 6 Control and Status
|
||||
XBYTE( EP8CS , 0xE6A6); // Endpoint 8 Control and Status
|
||||
|
||||
XBYTE( EP2FIFOFLGS , 0xE6A7); // Endpoint 2 Flags
|
||||
XBYTE( EP4FIFOFLGS , 0xE6A8); // Endpoint 4 Flags
|
||||
XBYTE( EP6FIFOFLGS , 0xE6A9); // Endpoint 6 Flags
|
||||
XBYTE( EP8FIFOFLGS , 0xE6AA); // Endpoint 8 Flags
|
||||
|
||||
XBYTE( EP2FIFOBCH , 0xE6AB); // EP2 FIFO total byte count H
|
||||
XBYTE( EP2FIFOBCL , 0xE6AC); // EP2 FIFO total byte count L
|
||||
XBYTE( EP4FIFOBCH , 0xE6AD); // EP4 FIFO total byte count H
|
||||
XBYTE( EP4FIFOBCL , 0xE6AE); // EP4 FIFO total byte count L
|
||||
XBYTE( EP6FIFOBCH , 0xE6AF); // EP6 FIFO total byte count H
|
||||
XBYTE( EP6FIFOBCL , 0xE6B0); // EP6 FIFO total byte count L
|
||||
XBYTE( EP8FIFOBCH , 0xE6B1); // EP8 FIFO total byte count H
|
||||
XBYTE( EP8FIFOBCL , 0xE6B2); // EP8 FIFO total byte count L
|
||||
|
||||
XBYTE( SUDPTRH , 0xE6B3); // Setup Data Pointer high address byte
|
||||
XBYTE( SUDPTRL , 0xE6B4); // Setup Data Pointer low address byte
|
||||
XBYTE( SUDPTRCTL , 0xE6B5); // Setup Data Pointer Auto Mode
|
||||
|
||||
XBYTE( SETUPDAT[8] , 0xE6B8); // 8 bytes of SETUP data
|
||||
|
||||
// ============================================================================
|
||||
// GPIF
|
||||
// ============================================================================
|
||||
XBYTE( GPIFWFSELECT , 0xE6C0); // Waveform Selector
|
||||
XBYTE( GPIFIDLECS , 0xE6C1); // GPIF Done, GPIF IDLE drive mode
|
||||
XBYTE( GPIFIDLECTL , 0xE6C2); // Inactive Bus, CTL states
|
||||
XBYTE( GPIFCTLCFG , 0xE6C3); // CTL OUT pin drive
|
||||
XBYTE( GPIFADRH , 0xE6C4); // GPIF Address H
|
||||
XBYTE( GPIFADRL , 0xE6C5); // GPIF Address L
|
||||
|
||||
XBYTE( GPIFTCB3 , 0xE6CE); // GPIF Transaction Count Byte 3
|
||||
XBYTE( GPIFTCB2 , 0xE6CF); // GPIF Transaction Count Byte 2
|
||||
XBYTE( GPIFTCB1 , 0xE6D0); // GPIF Transaction Count Byte 1
|
||||
XBYTE( GPIFTCB0 , 0xE6D1); // GPIF Transaction Count Byte 0
|
||||
|
||||
#define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility
|
||||
#define EP2GPIFTCL GPIFTCB0 //
|
||||
#define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility
|
||||
#define EP4GPIFTCL GPIFTCB0 //
|
||||
#define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility
|
||||
#define EP6GPIFTCL GPIFTCB0 //
|
||||
#define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility
|
||||
#define EP8GPIFTCL GPIFTCB0 //
|
||||
|
||||
XBYTE( EP2GPIFFLGSEL , 0xE6D2); // EP2 GPIF Flag select
|
||||
XBYTE( EP2GPIFPFSTOP , 0xE6D3); // Stop GPIF EP2 transaction on prog. flag
|
||||
XBYTE( EP2GPIFTRIG , 0xE6D4); // EP2 FIFO Trigger
|
||||
XBYTE( EP4GPIFFLGSEL , 0xE6DA); // EP4 GPIF Flag select
|
||||
XBYTE( EP4GPIFPFSTOP , 0xE6DB); // Stop GPIF EP4 transaction on prog. flag
|
||||
XBYTE( EP4GPIFTRIG , 0xE6DC); // EP4 FIFO Trigger
|
||||
XBYTE( EP6GPIFFLGSEL , 0xE6E2); // EP6 GPIF Flag select
|
||||
XBYTE( EP6GPIFPFSTOP , 0xE6E3); // Stop GPIF EP6 transaction on prog. flag
|
||||
XBYTE( EP6GPIFTRIG , 0xE6E4); // EP6 FIFO Trigger
|
||||
XBYTE( EP8GPIFFLGSEL , 0xE6EA); // EP8 GPIF Flag select
|
||||
XBYTE( EP8GPIFPFSTOP , 0xE6EB); // Stop GPIF EP8 transaction on prog. flag
|
||||
XBYTE( EP8GPIFTRIG , 0xE6EC); // EP8 FIFO Trigger
|
||||
XBYTE( XGPIFSGLDATH , 0xE6F0); // GPIF Data H (16-bit mode only)
|
||||
XBYTE( XGPIFSGLDATLX , 0xE6F1); // Read/Write GPIF Data L & trigger transac
|
||||
XBYTE( XGPIFSGLDATLNOX , 0xE6F2); // Read GPIF Data L, no transac trigger
|
||||
XBYTE( GPIFREADYCFG , 0xE6F3); // Internal RDY,Sync/Async, RDY5CFG
|
||||
XBYTE( GPIFREADYSTAT , 0xE6F4); // RDY pin states
|
||||
XBYTE( GPIFABORT , 0xE6F5); // Abort GPIF cycles
|
||||
|
||||
// ============================================================================
|
||||
// UDMA
|
||||
// ============================================================================
|
||||
XBYTE( FLOWSTATE , 0xE6C6); // Defines GPIF flow state
|
||||
XBYTE( FLOWLOGIC , 0xE6C7); // Defines flow/hold decision criteria
|
||||
XBYTE( FLOWEQ0CTL , 0xE6C8); // CTL states during active flow state
|
||||
XBYTE( FLOWEQ1CTL , 0xE6C9); // CTL states during hold flow state
|
||||
XBYTE( FLOWHOLDOFF , 0xE6CA);
|
||||
XBYTE( FLOWSTB , 0xE6CB); // CTL/RDY Signal to use as master data strobe
|
||||
XBYTE( FLOWSTBEDGE , 0xE6CC); // Defines active master strobe edge
|
||||
XBYTE( FLOWSTBHPERIOD , 0xE6CD); // Half Period of output master strobe
|
||||
XBYTE( GPIFHOLDAMOUNT , 0xE60C); // Data delay shift
|
||||
XBYTE( UDMACRCH , 0xE67D); // CRC Upper byte
|
||||
XBYTE( UDMACRCL , 0xE67E); // CRC Lower byte
|
||||
XBYTE( UDMACRCQUAL , 0xE67F); // UDMA In only, host terminated use only
|
||||
|
||||
// ============================================================================
|
||||
// Endpoint Buffers
|
||||
// ============================================================================
|
||||
XBYTE( EP0BUF [64] , 0xE740); // EP0 IN-OUT buffer
|
||||
XBYTE( EP1OUTBUF [64] , 0xE780); // EP1-OUT buffer
|
||||
XBYTE( EP1INBUF [64] , 0xE7C0); // EP1-IN buffer
|
||||
XBYTE( EP2FIFOBUF [1024] , 0xF000); // 512/1024-byte EP2 buffer (IN or OUT)
|
||||
XBYTE( EP4FIFOBUF [1024] , 0xF400); // 512 byte EP4 buffer (IN or OUT)
|
||||
XBYTE( EP6FIFOBUF [1024] , 0xF800); // 512/1024-byte EP6 buffer (IN or OUT)
|
||||
XBYTE( EP8FIFOBUF [1024] , 0xFC00); // 512 byte EP8 buffer (IN or OUT)
|
||||
|
||||
// ============================================================================
|
||||
// Error Correction Code (ECC) Registers (FX2LP/FX1 only)
|
||||
// ============================================================================
|
||||
XBYTE( ECCCFG , 0xE628); // ECC Configuration
|
||||
XBYTE( ECCRESET , 0xE629); // ECC Reset
|
||||
XBYTE( ECC1B0 , 0xE62A); // ECC1 Byte 0
|
||||
XBYTE( ECC1B1 , 0xE62B); // ECC1 Byte 1
|
||||
XBYTE( ECC1B2 , 0xE62C); // ECC1 Byte 2
|
||||
XBYTE( ECC2B0 , 0xE62D); // ECC2 Byte 0
|
||||
XBYTE( ECC2B1 , 0xE62E); // ECC2 Byte 1
|
||||
XBYTE( ECC2B2 , 0xE62F); // ECC2 Byte 2
|
||||
|
||||
// ============================================================================
|
||||
// Feature Registers (FX2LP/FX1 only)
|
||||
// ============================================================================
|
||||
XBYTE( GPCR2 , 0xE50D); // Chip Features
|
||||
|
||||
// ============================================================================
|
||||
// Special Function Registers (sfr)
|
||||
// ============================================================================
|
||||
#include <fx2_regs_sfr8x.h>
|
||||
#include <fx2_regs_sfr9x.h>
|
||||
#include <fx2_regs_sfrAx.h>
|
||||
#include <fx2_regs_sfrBx.h>
|
||||
#include <fx2_regs_sfrCx.h>
|
||||
#include <fx2_regs_sfrDx.h>
|
||||
#include <fx2_regs_sfrEx.h>
|
||||
#include <fx2_regs_sfrFx.h>
|
||||
|
||||
// ============================================================================
|
||||
// Bit masks
|
||||
// ============================================================================
|
||||
// ----------------------------------------------------------------------------
|
||||
// CPU Control & Status Register (CPUCS)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmPRTCSTB bmBIT5
|
||||
#define bmCLKSPD (bmBIT4 | bmBIT3)
|
||||
#define bmCLKSPD1 bmBIT4
|
||||
#define bmCLKSPD0 bmBIT3
|
||||
#define bmCLKINV bmBIT2
|
||||
#define bmCLKOE bmBIT1
|
||||
#define bm8051RES bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Port A (PORTACFG)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmFLAGD bmBIT7
|
||||
#define bmINT1 bmBIT1
|
||||
#define bmINT0 bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Port C (PORTCCFG)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmGPIFA7 bmBIT7
|
||||
#define bmGPIFA6 bmBIT6
|
||||
#define bmGPIFA5 bmBIT5
|
||||
#define bmGPIFA4 bmBIT4
|
||||
#define bmGPIFA3 bmBIT3
|
||||
#define bmGPIFA2 bmBIT2
|
||||
#define bmGPIFA1 bmBIT1
|
||||
#define bmGPIFA0 bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Port E (PORTECFG)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmGPIFA8 bmBIT7
|
||||
#define bmT2EX bmBIT6
|
||||
#define bmINT6 bmBIT5
|
||||
#define bmRXD1OUT bmBIT4
|
||||
#define bmRXD0OUT bmBIT3
|
||||
#define bmT2OUT bmBIT2
|
||||
#define bmT1OUT bmBIT1
|
||||
#define bmT0OUT bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// I2C Control & Status Register (I2CS)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmSTART bmBIT7
|
||||
#define bmSTOP bmBIT6
|
||||
#define bmLASTRD bmBIT5
|
||||
#define bmID (bmBIT4 | bmBIT3)
|
||||
#define bmBERR bmBIT2
|
||||
#define bmACK bmBIT1
|
||||
#define bmDONE bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// I2C Control Register (I2CTL)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmSTOPIE bmBIT1
|
||||
#define bm400KHZ bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Interrupt 2 (USB) Autovector Register (INT2IVEC)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmIV4 bmBIT6
|
||||
#define bmIV3 bmBIT5
|
||||
#define bmIV2 bmBIT4
|
||||
#define bmIV1 bmBIT3
|
||||
#define bmIV0 bmBIT2
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// USB Interrupt Request & Enable Registers (USBIE/USBIRQ)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmEP0ACK bmBIT6
|
||||
#define bmHSGRANT bmBIT5
|
||||
#define bmURES bmBIT4
|
||||
#define bmSUSP bmBIT3
|
||||
#define bmSUTOK bmBIT2
|
||||
#define bmSOF bmBIT1
|
||||
#define bmSUDAV bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// USB Interrupt Request & Enable Registers (EPIE/EPIRQ)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmEP8 bmBIT7
|
||||
#define bmEP6 bmBIT6
|
||||
#define bmEP4 bmBIT5
|
||||
#define bmEP2 bmBIT4
|
||||
#define bmEP1OUT bmBIT3
|
||||
#define bmEP1IN bmBIT2
|
||||
#define bmEP0OUT bmBIT1
|
||||
#define bmEP0IN bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// GPIF Interrupt Request & Enable Registers (GPIFIE/GPIFIRQ)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmGPIFWF bmBIT1
|
||||
#define bmGPIFDONE bmBIT0
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Breakpoint register (BREAKPT)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmBREAK bmBIT3
|
||||
#define bmBPPULSE bmBIT2
|
||||
#define bmBPEN bmBIT1
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Interrupt 2 & 4 Setup (INTSETUP)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmAV2EN bmBIT3
|
||||
#define INT4IN bmBIT1
|
||||
#define bmAV4EN bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// USB Control & Status Register (USBCS)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmHSM bmBIT7
|
||||
#define bmDISCON bmBIT3
|
||||
#define bmNOSYNSOF bmBIT2
|
||||
#define bmRENUM bmBIT1
|
||||
#define bmSIGRESUME bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Wakeup Control and Status Register (WAKEUPCS)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmWU2 bmBIT7
|
||||
#define bmWU bmBIT6
|
||||
#define bmWU2POL bmBIT5
|
||||
#define bmWUPOL bmBIT4
|
||||
#define bmDPEN bmBIT2
|
||||
#define bmWU2EN bmBIT1
|
||||
#define bmWUEN bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// End Point 0 Control & Status Register (EP0CS)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmHSNAK bmBIT7
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmEPBUSY bmBIT1
|
||||
#define bmEPSTALL bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
|
||||
#define bmEPFULL bmBIT3
|
||||
#define bmEPEMPTY bmBIT2
|
||||
|
||||
/* Endpoint Status (EP2468STAT) SFR bits */
|
||||
#define bmEP8FULL bmBIT7
|
||||
#define bmEP8EMPTY bmBIT6
|
||||
#define bmEP6FULL bmBIT5
|
||||
#define bmEP6EMPTY bmBIT4
|
||||
#define bmEP4FULL bmBIT3
|
||||
#define bmEP4EMPTY bmBIT2
|
||||
#define bmEP2FULL bmBIT1
|
||||
#define bmEP2EMPTY bmBIT0
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// SETUP Data Pointer Auto Mode (SUDPTRCTL)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmSDPAUTO bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Endpoint Data Toggle Control (TOGCTL)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmQUERYTOGGLE bmBIT7
|
||||
#define bmSETTOGGLE bmBIT6
|
||||
#define bmRESETTOGGLE bmBIT5
|
||||
#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmEP8IBN bmBIT5
|
||||
#define bmEP6IBN bmBIT4
|
||||
#define bmEP4IBN bmBIT3
|
||||
#define bmEP2IBN bmBIT2
|
||||
#define bmEP1IBN bmBIT1
|
||||
#define bmEP0IBN bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// PING-NAK enable and request bits (NAKIE/NAKIRQ)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmEP8PING bmBIT7
|
||||
#define bmEP6PING bmBIT6
|
||||
#define bmEP4PING bmBIT5
|
||||
#define bmEP2PING bmBIT4
|
||||
#define bmEP1PING bmBIT3
|
||||
#define bmEP0PING bmBIT2
|
||||
#define bmIBN bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Interface Configuration bits (IFCONFIG)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmIFCLKSRC bmBIT7
|
||||
#define bm3048MHZ bmBIT6
|
||||
#define bmIFCLKOE bmBIT5
|
||||
#define bmIFCLKPOL bmBIT4
|
||||
#define bmASYNC bmBIT3
|
||||
#define bmGSTATE bmBIT2
|
||||
#define bmIFCFG1 bmBIT1
|
||||
#define bmIFCFG0 bmBIT0
|
||||
|
||||
#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
|
||||
#define bmIFGPIF bmIFCFG1
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmINFM bmBIT6
|
||||
#define bmOEP bmBIT5
|
||||
#define bmAUTOOUT bmBIT4
|
||||
#define bmAUTOIN bmBIT3
|
||||
#define bmZEROLENIN bmBIT2
|
||||
#define bmWORDWIDE bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Chip Revision Control Bits (REVCTL) - used to ebable/disable revision
|
||||
// specific features.
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmNOAUTOARM bmBIT1
|
||||
#define bmSKIPCOMMIT bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// FIFO polarity (FIFOPINPOLAR)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmPKTEND bmBIT5
|
||||
#define bmSLOE bmBIT4
|
||||
#define bmSLRD bmBIT3
|
||||
#define bmSLWR bmBIT2
|
||||
#define bmEF bmBIT1
|
||||
#define bmFF bmBIT0
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// FIFO Reset bits (FIFORESET)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmNAKALL bmBIT7
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Chip Feature Register (GPCR2)
|
||||
// ----------------------------------------------------------------------------
|
||||
#define bmFULLSPEEDONLY bmBIT4
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,106 @@
|
||||
// ============================================================================
|
||||
// FX2LP SFR Registers at 0x80 - 0x8F
|
||||
// ----------------------------------------------------------------------------
|
||||
// 0x80 - IOA
|
||||
// 0x81 - SP
|
||||
// 0x82 - DPL0
|
||||
// 0x83 - DPH0
|
||||
// 0x84 - DPL1
|
||||
// 0x85 - DPH1
|
||||
// 0x86 - DPS
|
||||
// 0x87 - PCON
|
||||
// 0x88 - TCON
|
||||
// 0x89 - TMOD
|
||||
// 0x8A - TL0
|
||||
// 0x8B - TL1
|
||||
// 0x8C - TH0
|
||||
// 0x8D - TH1
|
||||
// 0x8E - CKCON
|
||||
// 0x8F - (SFUNC) ????
|
||||
//
|
||||
// TODO: check documentation!!!
|
||||
// ============================================================================
|
||||
#ifndef FX2REGS_SFR8X_H
|
||||
#define FX2REGS_SFR8X_H
|
||||
|
||||
sfr IOA = 0x80;
|
||||
sfr SP = 0x81;
|
||||
sfr DPL = 0x82;
|
||||
sfr DPH = 0x83;
|
||||
sfr DPL1 = 0x84;
|
||||
sfr DPH1 = 0x85;
|
||||
sfr DPS = 0x86;
|
||||
sfr PCON = 0x87;
|
||||
sfr TCON = 0x88;
|
||||
sfr TMOD = 0x89;
|
||||
sfr TL0 = 0x8A;
|
||||
sfr TL1 = 0x8B;
|
||||
sfr TH0 = 0x8C;
|
||||
sfr TH1 = 0x8D;
|
||||
sfr CKCON = 0x8E;
|
||||
sfr SFUNC = 0x8F;
|
||||
|
||||
sfr16 DP0 = 0x82;
|
||||
sfr16 DP1 = 0x84;
|
||||
|
||||
// ------------------------------------
|
||||
// PortA (0x80)
|
||||
// ------------------------------------
|
||||
sbit PA0 = 0x80 + 0;
|
||||
sbit PA1 = 0x80 + 1;
|
||||
sbit PA2 = 0x80 + 2;
|
||||
sbit PA3 = 0x80 + 3;
|
||||
sbit PA4 = 0x80 + 4;
|
||||
sbit PA5 = 0x80 + 5;
|
||||
sbit PA6 = 0x80 + 6;
|
||||
sbit PA7 = 0x80 + 7;
|
||||
|
||||
// ------------------------------------
|
||||
// TCON (0x88)
|
||||
// ------------------------------------
|
||||
sbit IT0 = 0x88 +0;
|
||||
sbit IE0 = 0x88 +1;
|
||||
sbit IT1 = 0x88 +2;
|
||||
sbit IE1 = 0x88 +3;
|
||||
sbit TR0 = 0x88 +4;
|
||||
sbit TF0 = 0x88 +5;
|
||||
sbit TR1 = 0x88 +6;
|
||||
sbit TF1 = 0x88 +7;
|
||||
|
||||
// ------------------------------------
|
||||
// PCON bits (0x87)
|
||||
// ------------------------------------
|
||||
#define bmIDLE 0x01
|
||||
//#define bmSTOP 0x02 // ??
|
||||
//#define bmGF0 0x04 // ??
|
||||
//#define bmGF1 0x08 // ??
|
||||
#define bmSMOD0 0x80
|
||||
|
||||
// ------------------------------------
|
||||
// TMOD bits (0x89)
|
||||
// ------------------------------------
|
||||
#define bmM00 0x01
|
||||
#define bmM10 0x02
|
||||
#define bmCT0 0x04
|
||||
#define bmGATE0 0x08
|
||||
#define bmM01 0x10
|
||||
#define bmM11 0x20
|
||||
#define bmCT1 0x40
|
||||
#define bmGATE1 0x80
|
||||
|
||||
// ------------------------------------
|
||||
// CKCON bits (0x8E)
|
||||
// ------------------------------------
|
||||
#define bmMD0 0x01
|
||||
#define bmMD1 0x02
|
||||
#define bmMD2 0x04
|
||||
#define bmT0M 0x08
|
||||
#define bmT1M 0x10
|
||||
#define bmT2M 0x20
|
||||
|
||||
// ------------------------------------
|
||||
// SFUNC bits
|
||||
// ------------------------------------
|
||||
//sbit WRS = 0x8F +0;
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,67 @@
|
||||
// ============================================================================
|
||||
// FX2LP SFR Registers at 0x90 - 0x9F
|
||||
// ----------------------------------------------------------------------------
|
||||
// 0x90 - IOB
|
||||
// 0x91 - EXIF
|
||||
// 0x92 - MPAGE
|
||||
// 0x93 -
|
||||
// 0x94 -
|
||||
// 0x95 -
|
||||
// 0x96 -
|
||||
// 0x97 -
|
||||
// 0x98 - SCON0
|
||||
// 0x99 - SBUF0
|
||||
// 0x9A - AUTOPTRH1
|
||||
// 0x9B - AUTOPTRL1
|
||||
// 0x9C -
|
||||
// 0x9D - AUTOPTRH2
|
||||
// 0x9E - AUTOPTRL2
|
||||
// 0x9F -
|
||||
// ============================================================================
|
||||
#ifndef FX2REGS_SFR9X_H
|
||||
#define FX2REGS_SFR9X_H
|
||||
|
||||
sfr IOB = 0x90;
|
||||
sfr EXIF = 0x91;
|
||||
sfr MPAGE = 0x92;
|
||||
sfr SCON0 = 0x98;
|
||||
sfr SBUF0 = 0x99;
|
||||
sfr AUTOPTRH1 = 0x9A;
|
||||
sfr AUTOPTRL1 = 0x9B;
|
||||
sfr AUTOPTRH2 = 0x9D;
|
||||
sfr AUTOPTRL2 = 0x9E;
|
||||
|
||||
// ------------------------------------
|
||||
// PortB (0x90)
|
||||
// ------------------------------------
|
||||
sbit PB0 = 0x90 +0;
|
||||
sbit PB1 = 0x90 +1;
|
||||
sbit PB2 = 0x90 +2;
|
||||
sbit PB3 = 0x90 +3;
|
||||
sbit PB4 = 0x90 +4;
|
||||
sbit PB5 = 0x90 +5;
|
||||
sbit PB6 = 0x90 +6;
|
||||
sbit PB7 = 0x90 +7;
|
||||
|
||||
// ------------------------------------
|
||||
// SCON0 (0x98)
|
||||
// ------------------------------------
|
||||
sbit RI = 0x98 +0;
|
||||
sbit TI = 0x98 +1;
|
||||
sbit RB8 = 0x98 +2;
|
||||
sbit TB8 = 0x98 +3;
|
||||
sbit REN = 0x98 +4;
|
||||
sbit SM2 = 0x98 +5;
|
||||
sbit SM1 = 0x98 +6;
|
||||
sbit SM0 = 0x98 +7;
|
||||
|
||||
// ------------------------------------
|
||||
// EXIF (0x91)
|
||||
// ------------------------------------
|
||||
#define bmUSBINT 0x10
|
||||
#define bmI2CINT 0x20
|
||||
#define bmIE4 0x40
|
||||
#define bmIE5 0x80
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,102 @@
|
||||
// ============================================================================
|
||||
// FX2LP SFR Registers at 0xA0 - 0xAF
|
||||
// ----------------------------------------------------------------------------
|
||||
// 0xA0 - IOC
|
||||
// 0xA1 - INT2CLR
|
||||
// 0xA2 - INT4CLR
|
||||
// 0xA3 -
|
||||
// 0xA4 -
|
||||
// 0xA5 -
|
||||
// 0xA6 -
|
||||
// 0xA7 -
|
||||
// 0xA8 - IE
|
||||
// 0xA9 -
|
||||
// 0xAA - EP2468STAT
|
||||
// 0xAB - EP24FIFOFLGS
|
||||
// 0xAC - EP68FIFOFLGS
|
||||
// 0xAD -
|
||||
// 0xAE -
|
||||
// 0xAF - AUTOPTRSETUP
|
||||
// ============================================================================
|
||||
#ifndef FX2REGS_SFRAX_H
|
||||
#define FX2REGS_SFRAX_H
|
||||
|
||||
sfr IOC = 0xA0;
|
||||
sfr INT2CLR = 0xA1;
|
||||
sfr INT4CLR = 0xA2;
|
||||
sfr IE = 0xA8;
|
||||
sfr EP2468STAT = 0xAA;
|
||||
sfr EP24FIFOFLGS= 0xAB;
|
||||
sfr EP68FIFOFLGS= 0xAC;
|
||||
sfr AUTOPTRSETUP= 0xAF;
|
||||
|
||||
|
||||
// ------------------------------------
|
||||
// IOC (0xA0)
|
||||
// ------------------------------------
|
||||
sbit PC0 = 0xA0 +0;
|
||||
sbit PC1 = 0xA0 +1;
|
||||
sbit PC2 = 0xA0 +2;
|
||||
sbit PC3 = 0xA0 +3;
|
||||
sbit PC4 = 0xA0 +4;
|
||||
sbit PC5 = 0xA0 +5;
|
||||
sbit PC6 = 0xA0 +6;
|
||||
sbit PC7 = 0xA0 +7;
|
||||
|
||||
|
||||
// ------------------------------------
|
||||
// IE (0xA8)
|
||||
// ------------------------------------
|
||||
sbit EX0 = 0xA8 +0;
|
||||
sbit ET0 = 0xA8 +1;
|
||||
sbit EX1 = 0xA8 +2;
|
||||
sbit ET1 = 0xA8 +3;
|
||||
sbit ES0 = 0xA8 +4;
|
||||
sbit ET2 = 0xA8 +5;
|
||||
sbit ES1 = 0xA8 +6;
|
||||
sbit EA = 0xA8 +7;
|
||||
|
||||
// ------------------------------------
|
||||
// EP2468STAT (0xAA)
|
||||
// ------------------------------------
|
||||
#define bmEP2E 0x01
|
||||
#define bmEP2F 0x02
|
||||
#define bmEP4E 0x04
|
||||
#define bmEP4F 0x08
|
||||
#define bmEP6E 0x10
|
||||
#define bmEP6F 0x20
|
||||
#define bmEP8E 0x40
|
||||
#define bmEP8F 0x80
|
||||
|
||||
// ------------------------------------
|
||||
// EP24FIFOFLGS (0XAB)
|
||||
// ------------------------------------
|
||||
#define bmEP2FF 0x01
|
||||
#define bmEP2EF 0x02
|
||||
#define bmEP2PF 0x04
|
||||
#define bmEP4FF 0x10
|
||||
#define bmEP4EF 0x20
|
||||
#define bmEP4PF 0x40
|
||||
|
||||
// ------------------------------------
|
||||
// EP68FIFOFLGS (0XAC)
|
||||
// ------------------------------------
|
||||
#define bmEP6FF 0x01
|
||||
#define bmEP6EF 0x02
|
||||
#define bmEP6PF 0x04
|
||||
#define bmEP8FF 0x10
|
||||
#define bmEP8EF 0x20
|
||||
#define bmEP8PF 0x40
|
||||
|
||||
// ------------------------------------
|
||||
// AUTOPTRSETUP (0xAF)
|
||||
// ------------------------------------
|
||||
#define bmAPTREN 0x01
|
||||
#define bmAPTR1INC 0x02
|
||||
#define bmAPTR2INC 0x04
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
// ============================================================================
|
||||
// FX2LP SFR Registers at 0xB0 - 0xBF
|
||||
// ----------------------------------------------------------------------------
|
||||
// 0xB0 - IOD
|
||||
// 0xB1 - IOE
|
||||
// 0xB2 - OEA
|
||||
// 0xB3 - OEB
|
||||
// 0xB4 - OEC
|
||||
// 0xB5 - OED
|
||||
// 0xB6 - OEE
|
||||
// 0xB7 -
|
||||
// 0xB8 - IP
|
||||
// 0xB9 -
|
||||
// 0xBA - EP01STAT
|
||||
// 0xBB - GPIFTRIG
|
||||
// 0xBC -
|
||||
// 0xBD - GPIFSGL_DATH
|
||||
// 0xBE - GPIFSGL_DATLX
|
||||
// 0xBF - GPIFSGL_DATLNOX
|
||||
// ============================================================================
|
||||
#ifndef FX2REGS_SFRBX_H
|
||||
#define FX2REGS_SFRBX_H
|
||||
|
||||
sfr IOD = 0xB0;
|
||||
sfr IOE = 0xB1;
|
||||
sfr OEA = 0xB2;
|
||||
sfr OEB = 0xB3;
|
||||
sfr OEC = 0xB4;
|
||||
sfr OED = 0xB5;
|
||||
sfr OEE = 0xB6;
|
||||
sfr IP = 0xB8;
|
||||
|
||||
sfr EP01STAT = 0xBA;
|
||||
sfr GPIFTRIG = 0xBB;
|
||||
sfr GPIFSGLDATH = 0xBD;
|
||||
sfr GPIFSGLDATLX = 0xBE;
|
||||
sfr GPIFSGLDATLNOX = 0xBF;
|
||||
|
||||
|
||||
// ------------------------------------
|
||||
// PortD (0xB0)
|
||||
// ------------------------------------
|
||||
sbit PD0 = 0xB0 +0;
|
||||
sbit PD1 = 0xB0 +1;
|
||||
sbit PD2 = 0xB0 +2;
|
||||
sbit PD3 = 0xB0 +3;
|
||||
sbit PD4 = 0xB0 +4;
|
||||
sbit PD5 = 0xB0 +5;
|
||||
sbit PD6 = 0xB0 +6;
|
||||
sbit PD7 = 0xB0 +7;
|
||||
|
||||
// ------------------------------------
|
||||
// IP bits
|
||||
// ------------------------------------
|
||||
sbit PX0 = 0xB8 +0;
|
||||
sbit PT0 = 0xB8 +1;
|
||||
sbit PX1 = 0xB8 +2;
|
||||
sbit PT1 = 0xB8 +3;
|
||||
sbit PS0 = 0xB8 +4;
|
||||
sbit PT2 = 0xB8 +5;
|
||||
sbit PS1 = 0xB8 +6;
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,59 @@
|
||||
// ============================================================================
|
||||
// FX2LP SFR Registers at 0xC0 - 0xCF
|
||||
// ----------------------------------------------------------------------------
|
||||
// 0xC0 - SCON1
|
||||
// 0xC1 - SBUF1
|
||||
// 0xC2 -
|
||||
// 0xC3 -
|
||||
// 0xC4 -
|
||||
// 0xC5 -
|
||||
// 0xC6 -
|
||||
// 0xC7 -
|
||||
// 0xC8 - T2CON
|
||||
// 0xC9 -
|
||||
// 0xCA - RCAP2L
|
||||
// 0xCB - RCAP2H
|
||||
// 0xCC - TL2
|
||||
// 0xCD - TH2
|
||||
// 0xCE -
|
||||
// 0xCF -
|
||||
// ============================================================================
|
||||
#ifndef FX2REGS_SFRCX_H
|
||||
#define FX2REGS_SFRCX_H
|
||||
|
||||
sfr SCON1 = 0xC0;
|
||||
sfr SBUF1 = 0xC1;
|
||||
sfr T2CON = 0xC8;
|
||||
sfr RCAP2L = 0xCA;
|
||||
sfr RCAP2H = 0xCB;
|
||||
sfr TL2 = 0xCC;
|
||||
sfr TH2 = 0xCD;
|
||||
|
||||
|
||||
// ------------------------------------
|
||||
// SCON1 (0xC0)
|
||||
// ------------------------------------
|
||||
sbit RI1 = 0xC0 +0;
|
||||
sbit TI1 = 0xC0 +1;
|
||||
sbit RB81 = 0xC0 +2;
|
||||
sbit TB81 = 0xC0 +3;
|
||||
sbit REN1 = 0xC0 +4;
|
||||
sbit SM21 = 0xC0 +5;
|
||||
sbit SM11 = 0xC0 +6;
|
||||
sbit SM01 = 0xC0 +7;
|
||||
|
||||
|
||||
// ------------------------------------
|
||||
// T2CON (0xC8)
|
||||
// ------------------------------------
|
||||
sbit CP_RL2 = 0xC8 +0;
|
||||
sbit C_T2 = 0xC8 +1;
|
||||
sbit TR2 = 0xC8 +2;
|
||||
sbit EXEN2 = 0xC8 +3;
|
||||
sbit TCLK = 0xC8 +4;
|
||||
sbit RCLK = 0xC8 +5;
|
||||
sbit EXF2 = 0xC8 +6;
|
||||
sbit TF2 = 0xC8 +7;
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,49 @@
|
||||
// ============================================================================
|
||||
// FX2LP SFR Registers at 0xD0 - 0xDF
|
||||
// ----------------------------------------------------------------------------
|
||||
// 0xD0 - PSW
|
||||
// 0xD1 -
|
||||
// 0xD2 -
|
||||
// 0xD3 -
|
||||
// 0xD4 -
|
||||
// 0xD5 -
|
||||
// 0xD6 -
|
||||
// 0xD7 -
|
||||
// 0xD8 - EICON
|
||||
// 0xD9 -
|
||||
// 0xDA -
|
||||
// 0xDB -
|
||||
// 0xDC -
|
||||
// 0xDD -
|
||||
// 0xDE -
|
||||
// 0xDF -
|
||||
// ============================================================================
|
||||
#ifndef FX2REGS_SFRDX_H
|
||||
#define FX2REGS_SFRDX_H
|
||||
|
||||
sfr PSW = 0xD0;
|
||||
sfr EICON = 0xD8;
|
||||
|
||||
// ------------------------------------
|
||||
// PSW bits
|
||||
// ------------------------------------
|
||||
sbit P = 0xD0 +0;
|
||||
sbit FL = 0xD0 +1;
|
||||
sbit OV = 0xD0 +2;
|
||||
sbit RS0 = 0xD0 +3;
|
||||
sbit RS1 = 0xD0 +4;
|
||||
sbit F0 = 0xD0 +5;
|
||||
sbit AC = 0xD0 +6;
|
||||
sbit CY = 0xD0 +7;
|
||||
|
||||
|
||||
// ------------------------------------
|
||||
// EICON bits
|
||||
// ------------------------------------
|
||||
sbit INT6 = 0xD8 +3;
|
||||
sbit RESI = 0xD8 +4;
|
||||
sbit ERESI = 0xD8 +5;
|
||||
sbit SMOD1 = 0xD8 +7;
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,37 @@
|
||||
// ============================================================================
|
||||
// FX2LP SFR Registers at 0xE0 - 0xEF
|
||||
// ----------------------------------------------------------------------------
|
||||
// 0xE0 - ACC
|
||||
// 0xE1 -
|
||||
// 0xE2 -
|
||||
// 0xE3 -
|
||||
// 0xE4 -
|
||||
// 0xE5 -
|
||||
// 0xE6 -
|
||||
// 0xE7 -
|
||||
// 0xE8 - EIE
|
||||
// 0xE9 -
|
||||
// 0xEA -
|
||||
// 0xEB -
|
||||
// 0xEC -
|
||||
// 0xED -
|
||||
// 0xEE -
|
||||
// 0xEF -
|
||||
// ============================================================================
|
||||
#ifndef FX2REGS_SFREX_H
|
||||
#define FX2REGS_SFREX_H
|
||||
|
||||
sfr ACC = 0xE0;
|
||||
sfr EIE = 0xE8;
|
||||
|
||||
// ------------------------------------
|
||||
// EIE bits
|
||||
// ------------------------------------
|
||||
sbit EUSB = 0xE8 +0;
|
||||
sbit EI2C = 0xE8 +1;
|
||||
sbit EIEX4 = 0xE8 +2;
|
||||
sbit EIEX5 = 0xE8 +3;
|
||||
sbit EIEX6 = 0xE8 +4;
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,37 @@
|
||||
// ============================================================================
|
||||
// FX2LP SFR Registers at 0xF0 - 0xFF
|
||||
// ----------------------------------------------------------------------------
|
||||
// 0xF0 - B
|
||||
// 0xF1 -
|
||||
// 0xF2 -
|
||||
// 0xF3 -
|
||||
// 0xF4 -
|
||||
// 0xF5 -
|
||||
// 0xF6 -
|
||||
// 0xF7 -
|
||||
// 0xF8 - EIP
|
||||
// 0xF9 -
|
||||
// 0xFA -
|
||||
// 0xFB -
|
||||
// 0xFC -
|
||||
// 0xFD -
|
||||
// 0xFE -
|
||||
// 0xFF -
|
||||
// ============================================================================
|
||||
#ifndef FX2REGS_SFRFX_H
|
||||
#define FX2REGS_SFRFX_H
|
||||
|
||||
sfr B = 0xF0;
|
||||
sfr EIP = 0xF8;
|
||||
|
||||
// ------------------------------------
|
||||
// EIP bits
|
||||
// ------------------------------------
|
||||
sbit PUSB = 0xF8 +0;
|
||||
sbit PI2C = 0xF8 +1;
|
||||
sbit EIPX4 = 0xF8 +2;
|
||||
sbit EIPX5 = 0xF8 +3;
|
||||
sbit EIPX6 = 0xF8 +4;
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,240 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
// File: fx2sdly.h
|
||||
// Contents: EZ-USB FX2 Synchronization Delay (SYNCDELAY) Macro
|
||||
//
|
||||
// Enter with _IFREQ = IFCLK in kHz
|
||||
// Enter with _CFREQ = CLKOUT in kHz
|
||||
//
|
||||
// Copyright (c) 2001 Cypress Semiconductor, All rights reserved
|
||||
//-----------------------------------------------------------------------------
|
||||
#include "intrins.h"
|
||||
|
||||
// Registers which require a synchronization delay, see section 15.14
|
||||
// FIFORESET FIFOPINPOLAR
|
||||
// INPKTEND OUTPKTEND
|
||||
// EPxBCH:L REVCTL
|
||||
// GPIFTCB3 GPIFTCB2
|
||||
// GPIFTCB1 GPIFTCB0
|
||||
// EPxFIFOPFH:L EPxAUTOINLENH:L
|
||||
// EPxFIFOCFG EPxGPIFFLGSEL
|
||||
// PINFLAGSxx EPxFIFOIRQ
|
||||
// EPxFIFOIE GPIFIRQ
|
||||
// GPIFIE GPIFADRH:L
|
||||
// UDMACRCH:L EPxGPIFTRIG
|
||||
// GPIFTRIG
|
||||
|
||||
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
|
||||
// ...these have been replaced by GPIFTC[B3:B0] registers
|
||||
|
||||
// _IFREQ can be in the range of: 5000 to 48000
|
||||
#ifndef _IFREQ
|
||||
#define _IFREQ 48000 // IFCLK frequency in kHz
|
||||
#endif
|
||||
|
||||
// CFREQ can be any one of: 48000, 24000, or 12000
|
||||
#ifndef _CFREQ
|
||||
#define _CFREQ 48000 // CLKOUT frequency in kHz
|
||||
#endif
|
||||
|
||||
#if( _IFREQ < 5000 )
|
||||
#error "_IFREQ too small! Valid Range: 5000 to 48000..."
|
||||
#endif
|
||||
|
||||
#if( _IFREQ > 48000 )
|
||||
#error "_IFREQ too large! Valid Range: 5000 to 48000..."
|
||||
#endif
|
||||
|
||||
#if( _CFREQ != 48000 )
|
||||
#if( _CFREQ != 24000 )
|
||||
#if( _CFREQ != 12000 )
|
||||
#error "_CFREQ invalid! Valid values: 48000, 24000, 12000..."
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Synchronization Delay formula: see TRM section 15-14
|
||||
#define _SCYCL ( 3*(_CFREQ) + 5*(_IFREQ) - 1 ) / ( 2*(_IFREQ) )
|
||||
|
||||
#if( _SCYCL == 1 )
|
||||
#define SYNCDELAY _nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 2 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 3 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 4 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 5 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 6 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 7 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 8 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 9 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 10 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 11 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 12 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 13 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 14 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 15 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
|
||||
#if( _SCYCL == 16 )
|
||||
#define SYNCDELAY _nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( ); \
|
||||
_nop_( )
|
||||
#endif
|
||||
@@ -0,0 +1,45 @@
|
||||
#ifndef __FX2_USART_H__
|
||||
#define __FX2_USART_H__
|
||||
|
||||
|
||||
typedef enum _usart_cfg
|
||||
{
|
||||
// -----------------------------------------------------
|
||||
// 11 bit total length configuraations
|
||||
// -----------------------------------------------------
|
||||
uc8n2, // 8 data bit no parity 2 stop bit
|
||||
uc8e1, // 8 data bit even parity 1 stop bit
|
||||
uc8o1, // 8 data bit odd parity 1 stop bit
|
||||
|
||||
// -----------------------------------------------------
|
||||
// 10 bit total length configuraations
|
||||
// -----------------------------------------------------
|
||||
uc8n1, // 8 data bit no parity 1 stop
|
||||
} usart_cfg;
|
||||
|
||||
// USART error codes
|
||||
// -----------------------------------------------------------------------------
|
||||
#define USART_OK 0x00
|
||||
#define USART_ERROR 0x80
|
||||
#define USART_ABORT 0xFF
|
||||
|
||||
|
||||
// I2C state machine states
|
||||
// -----------------------------------------------------------------------------
|
||||
#define USART_IDLE 0x00
|
||||
#define USART_SENDING 0x01
|
||||
#define USART_RECEIVING 0x02
|
||||
//#define I2C_PRIME 0x03
|
||||
//#define I2C_BERROR 0x04
|
||||
//#define I2C_NACK 0x05
|
||||
//#define I2C_STOP 0x06
|
||||
//#define I2C_WAITSTOP 0x07
|
||||
|
||||
|
||||
|
||||
void fx2_usart_init( unsigned int baud, usart_cfg cfg);
|
||||
BYTE fx2_usart_send( BYTE length, BYTE xdata *dat, BYTE xdata *pause);
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,748 @@
|
||||
$NOMOD51 DEBUG
|
||||
;------------------------------------------------------------------------------
|
||||
; This file is part of the RTX-51 TINY Real-Time Operating System Package
|
||||
; Copyright KEIL ELEKTRONIK GmbH and Keil Software, Inc. 1991-2002
|
||||
; Version 2.02
|
||||
;------------------------------------------------------------------------------
|
||||
; CONF_TNY.A51: This code allows the configuration of the
|
||||
; RTX-51 TINY Real-Time Operating System
|
||||
;
|
||||
; Copy this file to your project folder and add the copy to your uVision2
|
||||
; project. You can customize several parameters of RTX51 Tiny within this
|
||||
; configuration file.
|
||||
;
|
||||
; If you use command line tools, translate this file with:
|
||||
;
|
||||
; Ax51 CONF_TNY.A51
|
||||
;
|
||||
; If you use command line tools, link the modified CONF_TNY.OBJ file to
|
||||
; your application with:
|
||||
;
|
||||
; Lx51 <your object file list>, CONF_TNY.OBJ <controls>
|
||||
;
|
||||
;------------------------------------------------------------------------------
|
||||
;
|
||||
; RTX-51 TINY Hardware-Timer
|
||||
; ==========================
|
||||
;
|
||||
; With the following EQU statements the initialization of the RTX-51 TINY
|
||||
; Hardware-Timer can be defined (RTX-51 TINY uses the 8051 Timer 0 for
|
||||
; controlling RTX-51 software timers).
|
||||
;
|
||||
; Note: For Cypress FX2LP it is changed to use Timer 2.
|
||||
;------------------------------------------------------------------------------
|
||||
|
||||
; Define the register bank used for the timer interrupt.
|
||||
INT_REGBANK EQU 1 ; default is Registerbank 1
|
||||
;
|
||||
; Define Hardware-Timer tick time in 8051 machine cycles.
|
||||
INT_CLOCK EQU 40000 ; default is 40000 cycles
|
||||
;
|
||||
; Define Round-Robin Timeout in Hardware-Timer ticks.
|
||||
TIMESHARING EQU 5 ; default is 5 Hardware-Timer ticks.
|
||||
; ; 0 disables Round-Robin Task Switching
|
||||
;
|
||||
; Long User Interrupt Routines: set to 1 if your application contains
|
||||
; user interrupt functions that may take longer than a hardware timer
|
||||
; interval for execution.
|
||||
LONG_USR_INTR EQU 0 ; 0 user interrupts execute fast.
|
||||
; ; 1 user interrupts take long execution times.
|
||||
|
||||
|
||||
;------------------------------------------------------------------------------
|
||||
;
|
||||
; USER CODE FOR 8051 HARDWARE TIMER INTERRUPT
|
||||
; ===========================================
|
||||
;
|
||||
; The following macro defines the code executed on a hardware timer interrupt.
|
||||
; Define instructions executed on a hardware timer interrupt.
|
||||
;------------------------------------------------------------------------------
|
||||
HW_TIMER_CODE MACRO
|
||||
; Empty Macro by default
|
||||
RETI
|
||||
ENDM
|
||||
|
||||
|
||||
;------------------------------------------------------------------------------
|
||||
;
|
||||
; CODE BANKING SUPPORT
|
||||
; ====================
|
||||
;
|
||||
; The following EQU statement controls the code banking support for RTX51 TINY.
|
||||
;
|
||||
; Enable or disable code banking support
|
||||
CODE_BANKING EQU 0 ; 0 (default) application uses no code banking
|
||||
; ; 1 application uses code banking
|
||||
;
|
||||
;------------------------------------------------------------------------------
|
||||
;
|
||||
; RTX-51 TINY Stack Space
|
||||
; =======================
|
||||
;
|
||||
; The following EQU statements defines the size of the internal RAM used
|
||||
; for stack area and the minimum free space on the stack. A macro defines
|
||||
; the code executed when there is there is not enough free stack on the
|
||||
; CPU stack.
|
||||
;
|
||||
; Define the highest RAM address used for CPU stack
|
||||
RAMTOP EQU 0FFH ; default is address (256-1)
|
||||
;
|
||||
FREE_STACK EQU 20 ; default is 20 bytes free space on stack
|
||||
; ; the value 0 disables stack checking
|
||||
;
|
||||
STACK_ERROR MACRO
|
||||
CLR EA ; disable interrupts
|
||||
SJMP $ ; endless loop if stack space is exhausted
|
||||
ENDM
|
||||
;
|
||||
;
|
||||
;------------------------------------------------------------------------------
|
||||
;
|
||||
; 8051 CPU IDLE CODE
|
||||
; ==================
|
||||
;
|
||||
; Many 8051 devices provide an IDLE MODE that reduces power consumption and
|
||||
; EMC. The following macro defines the code executed when there is no
|
||||
; ready task in the system. The code must set the CPU into an IDLE MODE
|
||||
; that stops instruction execution until an 8051 hardware interrupt occurs.
|
||||
;
|
||||
|
||||
; Disable or Enable CPU_IDLE CODE
|
||||
CPU_IDLE_CODE EQU 0 ; 0 CPU_IDLE MACRO is not inserted
|
||||
; 1 CPU_IDLE MACRO is executed
|
||||
|
||||
PCON DATA 087H ; Power Control SFR on most 8051 devices
|
||||
|
||||
; Stop CPU execution until hardware interrupt; executed when there is no
|
||||
; active task in the system.
|
||||
CPU_IDLE MACRO
|
||||
ORL PCON,#1 ; set 8051 CPU to IDLE
|
||||
ENDM
|
||||
;
|
||||
;
|
||||
;------------------------------------------------------------------------------
|
||||
;----------------- !!! End of User Configuration Part !!! ------------------
|
||||
;----------------- !!! Do not modify code sections below !!! ------------------
|
||||
;------------------------------------------------------------------------------
|
||||
|
||||
; SFR Symbols
|
||||
PSW DATA 0D0H
|
||||
ACC DATA 0E0H
|
||||
B DATA 0F0H
|
||||
SP DATA 81H
|
||||
DPL DATA 82H
|
||||
DPH DATA 83H
|
||||
|
||||
TCON DATA 88H
|
||||
TMOD DATA 89H
|
||||
TL0 DATA 8AH
|
||||
TL1 DATA 8BH
|
||||
TH0 DATA 8CH
|
||||
TH1 DATA 8DH
|
||||
|
||||
IE DATA 0A8H
|
||||
|
||||
|
||||
; TCON
|
||||
TF1 BIT 8FH
|
||||
TR1 BIT 8EH
|
||||
TF0 BIT 8DH
|
||||
TR0 BIT 8CH
|
||||
IE1 BIT 8BH
|
||||
IT1 BIT 8AH
|
||||
IE0 BIT 89H
|
||||
IT0 BIT 88H
|
||||
|
||||
EA BIT 0AFH
|
||||
ES BIT 0ACH
|
||||
ET1 BIT 0ABH
|
||||
EX1 BIT 0AAH
|
||||
ET0 BIT 0A9H
|
||||
EX0 BIT 0A8H
|
||||
|
||||
; ---------------------------
|
||||
T2CON DATA 0C8h;
|
||||
RCAP2L DATA 0CAh
|
||||
RCAP2H DATA 0CBh
|
||||
TL2 DATA 0CCh
|
||||
TH2 DATA 0CDh
|
||||
|
||||
ET2 BIT 0A8h +5;
|
||||
T2M BIT 08Eh +5;
|
||||
|
||||
// --------------------------
|
||||
// T2CON bits
|
||||
// --------------------------
|
||||
CP_RL2 BIT 0C8h +0
|
||||
C_T2 BIT 0C8h +1
|
||||
TR2 BIT 0C8h +2
|
||||
TF2 BIT 0C8h +7;
|
||||
|
||||
|
||||
; Check Configuration Values
|
||||
|
||||
|
||||
NAME ?RTX51_TINY_KERNAL
|
||||
|
||||
PUBLIC ?RTX_CURRENTTASK
|
||||
PUBLIC ?RTX_RAMTOP
|
||||
PUBLIC os_switch_task
|
||||
PUBLIC ?RTX?SET_ISR
|
||||
|
||||
EXTRN NUMBER (?RTX_MAXTASKN) ; max Task Number
|
||||
|
||||
?RTX_RAMTOP EQU RAMTOP
|
||||
?RTX_CLOCK EQU -INT_CLOCK
|
||||
|
||||
?RTX_REGISTERBANK EQU INT_REGBANK * 8
|
||||
DSEG AT ?RTX_REGISTERBANK
|
||||
DS 2 ; temporary space
|
||||
?RTX_SAVEACC: DS 1
|
||||
saveacc EQU R2 ; for access in interrupt service routine
|
||||
?RTX_SAVEPSW: DS 1
|
||||
savepsw EQU R3 ; for access in interrupt service routine
|
||||
?RTX_CURRENTTASK: DS 1
|
||||
currenttask EQU R4 ; for access in interrupt service routine
|
||||
|
||||
IF (TIMESHARING <> 0)
|
||||
?RTX_ROBINTIME: DS 1
|
||||
robintime EQU R5 ; for access in interrupt service routine
|
||||
ENDIF
|
||||
|
||||
IF (CODE_BANKING <> 0)
|
||||
EXTRN DATA (?B_CURRENTBANK)
|
||||
EXTRN CODE (?B_RESTORE_BANK)
|
||||
ENDIF
|
||||
|
||||
;------------------------------------------------
|
||||
; Table of Task Entry Pointers
|
||||
;------------------------------------------------
|
||||
PUBLIC ?RTX_TASKENTRY
|
||||
|
||||
?RTX?TASKENT?S SEGMENT CODE
|
||||
RSEG ?RTX?TASKENT?S
|
||||
?RTX_TASKENTRY: DS 2
|
||||
|
||||
;------------------------------------------------
|
||||
; Table of Stack Pointers for each task
|
||||
;------------------------------------------------
|
||||
PUBLIC ?RTX_TASKSP
|
||||
|
||||
?RTX?TASKSP?S SEGMENT IDATA
|
||||
RSEG ?RTX?TASKSP?S
|
||||
?RTX_TASKSP: DS 1
|
||||
|
||||
;------------------------------------------------
|
||||
; Table of Task Timer/State Pointers
|
||||
;------------------------------------------------
|
||||
PUBLIC ?RTX_TASKSTATUS
|
||||
|
||||
?RTX?TASKSTATE?S SEGMENT IDATA
|
||||
RSEG ?RTX?TASKSTATE?S
|
||||
?RTX_TASKSTATUS:
|
||||
TimerVal: DS 1 ; Task Timer (Software Timer for each task)
|
||||
TaskState: DS 1 ; Task Status (state of each Task)
|
||||
|
||||
; Definitions for Bits in Task State
|
||||
; TaskState.0 = Wait for Signal
|
||||
; TaskState.1 = Wait for TimeOut
|
||||
; TaskState.2 = Signal Flag
|
||||
; TaskState.3 = TimeOut Flag
|
||||
; TaskState.4 = Task Ready (Wait for Running)
|
||||
; TaskState.5 = Task Active (enabled with os_create)
|
||||
; TaskState.6 = Round Robin Time Out
|
||||
; TaskState.7 = Run Flag
|
||||
|
||||
; byte mask definitions
|
||||
K_SIG EQU 1
|
||||
K_TMO EQU 2
|
||||
SIG_EVENT EQU 4
|
||||
TMO_EVENT EQU 8
|
||||
K_READY EQU 16
|
||||
K_ACTIVE EQU 32
|
||||
K_ROBIN EQU 64
|
||||
K_IVL EQU 128 ; not a task state bit; only used in os_wait
|
||||
RDY_EVENT EQU 128 ; READY status flag
|
||||
K_RDY EQU 128
|
||||
|
||||
; bit position definitions
|
||||
B_WAITSIG EQU 0
|
||||
B_WAITTIM EQU 1
|
||||
B_SIGNAL EQU 2
|
||||
B_TIMEOUT EQU 3
|
||||
B_READY EQU 4
|
||||
B_ACTIVE EQU 5
|
||||
B_ROBIN EQU 6
|
||||
B_IVL EQU 7 ; not a task state bit; only used in os_wait
|
||||
B_RDY EQU 7
|
||||
|
||||
|
||||
IF (TIMESHARING OR CPU_IDLE_CODE)
|
||||
?RTX?BITS SEGMENT BIT
|
||||
RSEG ?RTX?BITS
|
||||
ENDIF
|
||||
|
||||
IF (TIMESHARING)
|
||||
?RTX_TS_DELAY: DBIT 1 ; Status bit set when task switch in progress
|
||||
ENDIF
|
||||
|
||||
IF (CPU_IDLE_CODE)
|
||||
?RTX_ISR_SIG: DBIT 1 ; Status bit set when interrupt or os_set_signal
|
||||
ENDIF
|
||||
|
||||
|
||||
CSEG AT 02BH
|
||||
JMP TIMERINT
|
||||
|
||||
?RTX?CODE SEGMENT CODE
|
||||
RSEG ?RTX?CODE
|
||||
USING 0 ; Registerbank 0 for following code
|
||||
|
||||
IF (FREE_STACK <> 0)
|
||||
?RTX_STACKERROR:
|
||||
STACK_ERROR ; User defined Stack Error Code
|
||||
ENDIF
|
||||
|
||||
HW_TIMER: HW_TIMER_CODE
|
||||
|
||||
TIMERINT:
|
||||
CLR TF2
|
||||
|
||||
IF (LONG_USR_INTR)
|
||||
PUSH ACC
|
||||
MOV A,PSW
|
||||
ANL A,#018H
|
||||
XRL A,#?RTX_REGISTERBANK
|
||||
JNZ CONT_TIMINT
|
||||
; avoid recursive timer interrupt
|
||||
POP ACC
|
||||
RETI ; Return from Recursive Timer Interrupt
|
||||
CONT_TIMINT: POP ACC
|
||||
|
||||
ENDIF
|
||||
|
||||
CALL HW_TIMER ; Enable Interrupts again.
|
||||
|
||||
MOV ?RTX_SAVEPSW,PSW
|
||||
MOV PSW, #?RTX_REGISTERBANK
|
||||
|
||||
|
||||
MOV saveacc, ACC ; ACC required by some Cygnal devices
|
||||
|
||||
;; ----------------------------------------------------------
|
||||
;; On Cypress FX2LP timer 2 used in 16 bit autoload mode, so
|
||||
;; reloading the timer manualy is not necessary.
|
||||
;; ----------------------------------------------------------
|
||||
; Update 8051 Interrupt Timer
|
||||
;CLR TR0
|
||||
;
|
||||
;MOV A, TL0
|
||||
;ADD A, #LOW (?RTX_CLOCK + 7)
|
||||
;MOV TL0, A
|
||||
;
|
||||
;MOV A, TH0
|
||||
;ADDC A, #HIGH (?RTX_CLOCK + 7)
|
||||
;MOV TH0,A
|
||||
;
|
||||
;SETB TR0
|
||||
;; ----------------------------------------------------------
|
||||
|
||||
IF (FREE_STACK <> 0)
|
||||
; Check if enough free stack is available
|
||||
MOV A,currenttask
|
||||
ADD A,#?RTX?TASKSP?S+1
|
||||
MOV R0,A
|
||||
MOV A,@R0
|
||||
CJNE currenttask,#?RTX_MAXTASKN,checkstack
|
||||
MOV A,#RAMTOP
|
||||
checkstack: CLR C
|
||||
SUBB A,SP
|
||||
CJNE A,#FREE_STACK,$+3
|
||||
JC ?RTX_STACKERROR
|
||||
ENDIF
|
||||
|
||||
; Update & Check Task Timers
|
||||
MOV R1,#?RTX_MAXTASKN+1
|
||||
MOV R0,#?RTX?TASKSTATE?S
|
||||
TIMERLOOP: DEC @R0 ; Decrement timer
|
||||
MOV A,@R0
|
||||
INC R0 ; advance to TaskState
|
||||
JNZ NoTimeout
|
||||
CLR EA
|
||||
MOV A,@R0
|
||||
JNB ACC.B_WAITTIM,NoWaitTimeout
|
||||
ORL A,#(K_READY+TMO_EVENT)
|
||||
MOV @R0,A
|
||||
NoWaitTimeout: SETB EA
|
||||
NoTimeout: INC R0 ; advance to TaskTimer
|
||||
DJNZ R1,TIMERLOOP
|
||||
|
||||
MOV A,saveacc
|
||||
MOV PSW,savepsw
|
||||
USING 0 ; Registerbank 0 for following code
|
||||
|
||||
IF (TIMESHARING == 0)
|
||||
; Round Robin Task Switching not required. System Interrupt ends here
|
||||
?RTX?SET_ISR:
|
||||
IF (CPU_IDLE_CODE)
|
||||
SETB ?RTX_ISR_SIG
|
||||
ENDIF
|
||||
RET
|
||||
ENDIF
|
||||
|
||||
IF (TIMESHARING)
|
||||
; Round Robin Task Switching required. Check if task generates timeout
|
||||
; Check for Round Robin Timeout on the current task
|
||||
JNB ?RTX_TS_DELAY,CheckRobinTime
|
||||
NoRobinTimeout:
|
||||
?RTX?SET_ISR:
|
||||
IF (CPU_IDLE_CODE)
|
||||
SETB ?RTX_ISR_SIG
|
||||
ENDIF
|
||||
RET
|
||||
CheckRobinTime: DJNZ ?RTX_ROBINTIME,NoRobinTimeout
|
||||
|
||||
?RTX_TASKSWITCHING:
|
||||
PUSH ACC
|
||||
PUSH PSW
|
||||
PUSH B
|
||||
PUSH DPH
|
||||
PUSH DPL
|
||||
PUSH AR0
|
||||
PUSH AR1
|
||||
PUSH AR2
|
||||
PUSH AR3
|
||||
PUSH AR4
|
||||
PUSH AR5
|
||||
PUSH AR6
|
||||
PUSH AR7
|
||||
IF (CODE_BANKING <> 0)
|
||||
PUSH ?B_CURRENTBANK
|
||||
ENDIF
|
||||
|
||||
MOV A,?RTX_CURRENTTASK
|
||||
RL A
|
||||
ADD A,#?RTX?TASKSTATE?S+1
|
||||
MOV R0,A
|
||||
MOV A,#K_ROBIN
|
||||
CLR EA
|
||||
ORL A,@R0
|
||||
MOV @R0,A
|
||||
SETB EA
|
||||
IF (CODE_BANKING <> 0)
|
||||
SJMP os_switch_task1
|
||||
ENDIF
|
||||
ENDIF
|
||||
|
||||
;------------------------------------------------
|
||||
; Perform a Task-Switch
|
||||
; void os_switch_task (void)
|
||||
; uchar i;
|
||||
; uchar limit;
|
||||
|
||||
;---- Variable 'current' assigned to Register 'R6' ----
|
||||
;---- Variable 'next' assigned to Register 'R7' ----
|
||||
;---- Variable 'i' assigned to Register 'R0' ----
|
||||
;---- Variable 'limit' assigned to Register 'R5' ----
|
||||
;
|
||||
;------------------------------------------------
|
||||
|
||||
os_switch_task:
|
||||
|
||||
IF (CODE_BANKING <> 0)
|
||||
PUSH ?B_CURRENTBANK
|
||||
ENDIF
|
||||
|
||||
os_switch_task1:
|
||||
|
||||
; next = current;
|
||||
IF (TIMESHARING <> 0)
|
||||
SETB ?RTX_TS_DELAY ; Delay Task Switching
|
||||
ENDIF
|
||||
MOV A,?RTX_CURRENTTASK
|
||||
MOV R7,A
|
||||
; while (1) {
|
||||
RL A
|
||||
ADD A,#?RTX?TASKSTATE?S+1
|
||||
MOV R0,A
|
||||
?C0001:
|
||||
; if (++next == MAXTASKN+1) next = 0;
|
||||
INC R7
|
||||
INC R0
|
||||
INC R0
|
||||
IF (CPU_IDLE_CODE)
|
||||
MOV A,R7
|
||||
CJNE A,?RTX_CURRENTTASK,NoIDLE
|
||||
JBC ?RTX_ISR_SIG,NoIDLE
|
||||
CPU_IDLE ; CPU sleep
|
||||
NoIDLE:
|
||||
ENDIF
|
||||
CJNE R7,#?RTX_MAXTASKN+1,?C0003
|
||||
MOV R7,#0
|
||||
MOV R0,#?RTX?TASKSTATE?S+1
|
||||
?C0003:
|
||||
; if (STATE[next].st & K_READY) break;
|
||||
MOV A,@R0
|
||||
JNB ACC.B_READY,?C0001
|
||||
; }
|
||||
;
|
||||
|
||||
PUBLIC ?RTX_NEXTID
|
||||
PUBLIC ?RTX_NEXTTASK
|
||||
|
||||
?RTX_NEXTID EQU AR7
|
||||
?RTX_NEXTTASK: NOP ; for Debugging
|
||||
|
||||
; while (current < next) {
|
||||
?C0005:
|
||||
MOV A,?RTX_CURRENTTASK
|
||||
CLR C
|
||||
SUBB A,R7
|
||||
JNC ?C0011
|
||||
|
||||
; current++;
|
||||
INC ?RTX_CURRENTTASK
|
||||
; i = STKP[current];
|
||||
MOV A,#?RTX?TASKSP?S
|
||||
ADD A,?RTX_CURRENTTASK
|
||||
MOV R0,A
|
||||
MOV A,@R0
|
||||
MOV R5,A
|
||||
; STKP[current] = SP;
|
||||
MOV @R0,SP
|
||||
; if (current == MAXTASKN) limit = RAMTOP;
|
||||
INC R0
|
||||
MOV A,@R0
|
||||
MOV R6,?RTX_CURRENTTASK
|
||||
CJNE R6,#?RTX_MAXTASKN,?C0007
|
||||
MOV A,#RAMTOP
|
||||
?C0007:
|
||||
XCH A,R5
|
||||
MOV R0,A
|
||||
; else limit = STKP[current+1];
|
||||
;
|
||||
; while (i != limit) {
|
||||
?C0009:
|
||||
MOV A,R0
|
||||
XRL A,R5
|
||||
JZ ?C0005
|
||||
; SP++;
|
||||
; i++;
|
||||
; STACK[SP] = STACK[i];
|
||||
INC R0
|
||||
MOV A,@R0
|
||||
PUSH ACC
|
||||
SJMP ?C0009
|
||||
; }
|
||||
; }
|
||||
?C0011:
|
||||
;
|
||||
; while (current > next) {
|
||||
MOV A,?RTX_CURRENTTASK
|
||||
SETB C
|
||||
SUBB A,R7
|
||||
JC ?C0012
|
||||
|
||||
MOV A,?RTX_CURRENTTASK
|
||||
ADD A,#?RTX?TASKSP?S+1
|
||||
MOV R0,A
|
||||
MOV A,@R0
|
||||
; if (current == (MAXTASKN)) i = RAMTOP;
|
||||
; else i = STKP[current+1];
|
||||
MOV R6,?RTX_CURRENTTASK
|
||||
CJNE R6,#?RTX_MAXTASKN,?C0013
|
||||
MOV A,#RAMTOP
|
||||
?C0013:
|
||||
MOV R5,A
|
||||
; limit = STKP[current];
|
||||
DEC R0
|
||||
MOV A,@R0
|
||||
XCH A,R5
|
||||
MOV R0,A
|
||||
;
|
||||
; while (SP != limit) {
|
||||
?C0015:
|
||||
MOV A,SP
|
||||
XRL A,R5
|
||||
JZ ?C0016
|
||||
; STACK[i] = STACK[SP];
|
||||
; i--;
|
||||
; SP--;
|
||||
POP ACC
|
||||
MOV @R0,A
|
||||
DEC R0
|
||||
|
||||
SJMP ?C0015
|
||||
?C0016:
|
||||
; }
|
||||
; STKP[current] = i;
|
||||
MOV A,?RTX_CURRENTTASK
|
||||
ADD A,#?RTX?TASKSP?S
|
||||
XCH A,R0
|
||||
MOV @R0,A
|
||||
; current--;
|
||||
DEC ?RTX_CURRENTTASK
|
||||
SJMP ?C0011
|
||||
?C0012:
|
||||
; }
|
||||
|
||||
; RoundRobinTime = ?RTX_TIMESHARING
|
||||
IF (TIMESHARING)
|
||||
MOV ?RTX_ROBINTIME,#TIMESHARING
|
||||
ENDIF
|
||||
|
||||
; if (STATE[current].st & K_ROBIN) goto RobinOn;
|
||||
MOV A,?RTX_CURRENTTASK
|
||||
RL A
|
||||
ADD A,#?RTX?TASKSTATE?S+1
|
||||
MOV R0,A
|
||||
MOV R7,#SIG_EVENT
|
||||
CLR EA
|
||||
MOV A,@R0
|
||||
IF (TIMESHARING)
|
||||
JBC ACC.B_ROBIN,RobinOn
|
||||
ENDIF
|
||||
; if ((STATE[current].st & K_SIG) && (STATE[current].st & SIG_EVENT)
|
||||
; goto SignalOn;
|
||||
JNB ACC.B_WAITSIG,SignalOff
|
||||
JBC ACC.B_SIGNAL,SignalOn
|
||||
SignalOff:
|
||||
; if ((STATE[current].st & K_TMO) && (STATE[current].st & TMO_EVENT)
|
||||
; goto TimeOutOn;
|
||||
MOV R7,#0 ; No Event
|
||||
JNB ACC.B_WAITTIM,NoEvent
|
||||
JNB ACC.B_TIMEOUT,NoEvent
|
||||
TimeOutOn:
|
||||
MOV R7,#TMO_EVENT
|
||||
ANL A,#0F4H
|
||||
SignalOn:
|
||||
NoEvent: ANL A,#NOT (K_RDY + K_TMO + K_SIG) ; Clear RDY + Wait bits
|
||||
XCH A,@R0
|
||||
SETB EA
|
||||
|
||||
ANL A,#K_RDY
|
||||
ORL AR7,A
|
||||
IF (TIMESHARING <> 0)
|
||||
IF (CODE_BANKING)
|
||||
POP ACC
|
||||
CALL ?B_RESTORE_BANK
|
||||
ENDIF
|
||||
CLR ?RTX_TS_DELAY
|
||||
RET
|
||||
ELSE
|
||||
IF (CODE_BANKING)
|
||||
POP ACC
|
||||
JMP ?B_RESTORE_BANK
|
||||
ENDIF
|
||||
RET
|
||||
ENDIF
|
||||
|
||||
|
||||
|
||||
;------------------------------------------------
|
||||
IF (TIMESHARING <> 0)
|
||||
RobinOn: MOV @R0,A
|
||||
SETB EA
|
||||
IF (CODE_BANKING)
|
||||
POP ACC
|
||||
CALL ?B_RESTORE_BANK
|
||||
ENDIF
|
||||
POP AR7
|
||||
POP AR6
|
||||
POP AR5
|
||||
POP AR4
|
||||
POP AR3
|
||||
POP AR2
|
||||
POP AR1
|
||||
POP AR0
|
||||
POP DPL
|
||||
POP DPH
|
||||
POP B
|
||||
POP PSW
|
||||
POP ACC
|
||||
CLR ?RTX_TS_DELAY
|
||||
RET ; Restart Task
|
||||
ENDIF
|
||||
; }
|
||||
; }
|
||||
|
||||
|
||||
|
||||
;;; ===========================================================================
|
||||
;;; Start RTX-51 Tiny Kernel
|
||||
;;; ===========================================================================
|
||||
EXTRN CODE (?C_STARTUP)
|
||||
|
||||
|
||||
PUBLIC main
|
||||
|
||||
main:
|
||||
MOV R0, #?RTX?TASKSP?S
|
||||
MOV @R0, SP
|
||||
MOV A, #?RTX_MAXTASKN
|
||||
JZ main2
|
||||
|
||||
MOV R7, A
|
||||
main1: INC R0
|
||||
MOV @R0,#RAMTOP
|
||||
DJNZ R7,main1
|
||||
|
||||
main2: MOV R7,#?RTX_MAXTASKN+1
|
||||
CLR A
|
||||
MOV R0,#?RTX?TASKSTATE?S
|
||||
|
||||
main1x:
|
||||
MOV @R0, A
|
||||
INC R0
|
||||
MOV @R0, A
|
||||
INC R0
|
||||
DJNZ R7,main1x
|
||||
|
||||
MOV R0, #?RTX?TASKSTATE?S+1
|
||||
MOV @R0, #K_ACTIVE+K_READY
|
||||
MOV DPTR, #?RTX?TASKENT?S
|
||||
MOV A, #1
|
||||
MOVC A, @A+DPTR
|
||||
PUSH ACC
|
||||
CLR A
|
||||
MOVC A,@A+DPTR
|
||||
PUSH ACC
|
||||
|
||||
IF (TIMESHARING <> 0)
|
||||
MOV ?RTX_ROBINTIME, #TIMESHARING
|
||||
ENDIF
|
||||
|
||||
; -------------------------------------------------
|
||||
; Initialize Timer 2
|
||||
; -------------------------------------------------
|
||||
MOV RCAP2L, #LOW (?RTX_CLOCK)
|
||||
MOV RCAP2H, #HIGH(?RTX_CLOCK)
|
||||
|
||||
MOV TL2, RCAP2L
|
||||
MOV TH2, RCAP2H
|
||||
|
||||
MOV T2CON, #00H
|
||||
|
||||
SETB ET2
|
||||
SETB TR2
|
||||
|
||||
; Timer 0 initialization
|
||||
; ORL TMOD, #01H ; Timer 0 Mode 1
|
||||
; MOV TL0, #LOW (?RTX_CLOCK)
|
||||
; MOV TH0, #HIGH(?RTX_CLOCK)
|
||||
; SETB TR0
|
||||
; SETB ET0
|
||||
|
||||
; -------------------------------------------------
|
||||
; Start task 0 by enabling interrupts
|
||||
; -------------------------------------------------
|
||||
SETB EA
|
||||
RET
|
||||
|
||||
|
||||
;------------------------------------------------
|
||||
|
||||
PUBLIC ?RTX_TASKIDX
|
||||
?RTX_TASKIDX: DB ?RTX_MAXTASKN ; for Debugging
|
||||
|
||||
END
|
||||
@@ -0,0 +1,23 @@
|
||||
#include <fx2.h>
|
||||
#include <fx2_regs.h>
|
||||
|
||||
extern void FX2_Delay1ms();
|
||||
|
||||
// ============================================================================
|
||||
// FX2_Delay
|
||||
// ============================================================================
|
||||
void FX2_Delay( WORD ms)
|
||||
{
|
||||
// ----------------------------------------------------
|
||||
// Adjust the delay based on the CPU clock.
|
||||
// FX2_Delay1ms() assumes a 24 MHz clock.
|
||||
// ----------------------------------------------------
|
||||
if((CPUCS & bmCLKSPD) == 0) // 12 MHz
|
||||
ms = (ms +1) >> 1;
|
||||
|
||||
else if(( CPUCS & bmCLKSPD) == bmCLKSPD1) // 48 MHz
|
||||
ms = ms << 1;
|
||||
|
||||
while(ms--)
|
||||
FX2_Delay1ms();
|
||||
}
|
||||
@@ -0,0 +1,29 @@
|
||||
NAME DELAY1MS
|
||||
PUBLIC FX2_Delay1ms
|
||||
|
||||
FX2LP segment code
|
||||
|
||||
rseg FX2LP
|
||||
|
||||
DPS DATA 086H
|
||||
|
||||
;; ====================================================================
|
||||
;; Delay for 1 millisecond (1000 microseconds).
|
||||
;; 10 cycles * 166.6 ns per cycle is 1.66 microseconds per loop.
|
||||
;; 1000 microseconds / 1.66 = 602 [assumes 24 MHz clock].
|
||||
;; ====================================================================
|
||||
FX2_Delay1ms:
|
||||
mov a, #0
|
||||
mov DPS, a
|
||||
mov dptr,#(0ffffh -602)
|
||||
mov r4,#5
|
||||
|
||||
loop:
|
||||
inc dptr ; 3 cycles
|
||||
mov a, dpl ; 2 cycles
|
||||
orl a, dph ; 2 cycles
|
||||
jnz loop ; 3 cycles
|
||||
|
||||
ret
|
||||
|
||||
END
|
||||
@@ -0,0 +1,35 @@
|
||||
#include <fx2.h>
|
||||
#include <fx2_regs.h>
|
||||
|
||||
// ============================================================================
|
||||
// FX2_Disconnect
|
||||
// ============================================================================
|
||||
void FX2_Disconnect(bool renum)
|
||||
{
|
||||
// ----------------------------------------------------
|
||||
// If renumerate (i.e. 8051 will handle SETUP commands)
|
||||
// disconnect from USB and set the renumerate bit.
|
||||
// ----------------------------------------------------
|
||||
if(renum)
|
||||
USBCS |= (bmDISCON | bmRENUM);
|
||||
else
|
||||
USBCS |= bmDISCON;
|
||||
|
||||
// ----------------------------------------------------
|
||||
// Wait 1500 ms
|
||||
// ----------------------------------------------------
|
||||
FX2_Delay(1500);
|
||||
|
||||
// ----------------------------------------------------
|
||||
// Clear any pending interrupt requests. They are for
|
||||
// our old life.
|
||||
// ----------------------------------------------------
|
||||
USBIRQ = 0xFF;
|
||||
EPIRQ = 0xFF;
|
||||
USB_IRQ_CLEAR();
|
||||
|
||||
// ----------------------------------------------------
|
||||
// Reconnect USB
|
||||
// ----------------------------------------------------
|
||||
USBCS &= ~bmDISCON;
|
||||
}
|
||||
@@ -0,0 +1,123 @@
|
||||
#include <fx2.h>
|
||||
#include <fx2_i2c.h>
|
||||
|
||||
#define EEPROM_ADDR 0x51
|
||||
|
||||
BYTE xdata buffer[34];
|
||||
WORD xdata address;
|
||||
|
||||
|
||||
// ================================================================================================
|
||||
// Read EEPROM data
|
||||
// ================================================================================================
|
||||
BYTE FX2_EEPROM_Read( WORD page, BYTE offset, BYTE length, BYTE xdata *dat)
|
||||
{
|
||||
BYTE rc;
|
||||
|
||||
address = (page << 5) + (offset & 0x1F);
|
||||
length = (length > 32) ? 32 : length;
|
||||
|
||||
if((rc = fx2_i2c_write( EEPROM_ADDR, 2, (BYTE xdata *) &address)) == I2C_OK)
|
||||
rc = fx2_i2c_read( EEPROM_ADDR, length, dat);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
// ================================================================================================
|
||||
// Write EEPROM data
|
||||
// ================================================================================================
|
||||
BYTE FX2_EEPROM_Write( WORD page, BYTE offset, BYTE length, BYTE xdata *dat)
|
||||
{
|
||||
BYTE rc = 0xcc;
|
||||
WORD i;
|
||||
|
||||
length = (length > 32) ? 32 : length;
|
||||
*(WORD xdata*)buffer = (page << 5) + (offset & 0x1F);
|
||||
|
||||
for( i=0; i<length; i++)
|
||||
buffer[i+2] = dat[i];
|
||||
|
||||
if((rc = fx2_i2c_write( EEPROM_ADDR, length+2, buffer)) == I2C_OK)
|
||||
rc = fx2_i2c_wait( EEPROM_ADDR);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
// ================================================================================================
|
||||
// Read EEPROM data from page #0
|
||||
// ================================================================================================
|
||||
BYTE FX2_EEPROM_ReadPage0( BYTE addr, BYTE length, BYTE xdata *dat)
|
||||
{
|
||||
BYTE rc;
|
||||
|
||||
if( (addr +length) <= 32)
|
||||
{
|
||||
address = addr;
|
||||
|
||||
if((rc = fx2_i2c_write( EEPROM_ADDR, 2, (BYTE xdata *) &address)) == I2C_OK)
|
||||
rc = fx2_i2c_read( EEPROM_ADDR, length, dat);
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
// ================================================================================================
|
||||
// Write EEPROM data to page #0
|
||||
// ================================================================================================
|
||||
BYTE FX2_EEPROM_WritePage0( BYTE addr, BYTE length, BYTE xdata *dat)
|
||||
{
|
||||
WORD i;
|
||||
BYTE rc = 0;
|
||||
|
||||
if( addr +length <= 32)
|
||||
{
|
||||
*(WORD xdata *)buffer = addr;
|
||||
|
||||
for( i=0; i<length; i++)
|
||||
buffer[i+2] = dat[i];
|
||||
|
||||
if((rc = fx2_i2c_write( EEPROM_ADDR, length+2, buffer)) == I2C_OK)
|
||||
rc = fx2_i2c_wait( EEPROM_ADDR);
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
// ================================================================================================
|
||||
// Read EEPROM data from page N
|
||||
// ================================================================================================
|
||||
BYTE FX2_EEPROM_ReadPage( WORD page, BYTE length, BYTE xdata *dat)
|
||||
{
|
||||
BYTE rc;
|
||||
|
||||
address = page << 5;
|
||||
length = (length > 32) ? 32 : length;
|
||||
|
||||
if((rc = fx2_i2c_write( EEPROM_ADDR, 2, (BYTE xdata *) &address)) == I2C_OK)
|
||||
rc = fx2_i2c_read( EEPROM_ADDR, length, dat);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
// ================================================================================================
|
||||
// Write EEPROM data to page N
|
||||
// ================================================================================================
|
||||
BYTE FX2_EEPROM_WritePage( WORD page, BYTE length, BYTE xdata *dat)
|
||||
{
|
||||
BYTE rc = 0xcc;
|
||||
WORD i;
|
||||
|
||||
length = (length > 32) ? 32 : length;
|
||||
*(WORD xdata*)buffer = page << 5;
|
||||
|
||||
for( i=0; i<length; i++)
|
||||
buffer[i+2] = dat[i];
|
||||
|
||||
if((rc = fx2_i2c_write( EEPROM_ADDR, length+2, buffer)) == I2C_OK)
|
||||
rc = fx2_i2c_wait( EEPROM_ADDR);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,9 @@
|
||||
#define ALLOCATE_EXTERN 1
|
||||
|
||||
#include <fx2.h>
|
||||
#include <fx2_regs.h>
|
||||
|
||||
xdata bool Sleep;
|
||||
xdata bool GotSUD;
|
||||
xdata bool Rwuen;
|
||||
xdata bool SelfPower;
|
||||
@@ -0,0 +1,107 @@
|
||||
#include <fx2.h>
|
||||
#include <fx2_regs.h>
|
||||
#include <fx2_syncdelay.h>
|
||||
|
||||
#include <fx2_gpif.h>
|
||||
|
||||
extern const char code InitData[];
|
||||
extern const char code WaveData[];
|
||||
extern const char code FlowStates[];
|
||||
|
||||
// ============================================================================
|
||||
// Init
|
||||
//
|
||||
// todo:
|
||||
// PORTC bits (GPIF address bits)
|
||||
|
||||
// ============================================================================
|
||||
void fx2_gpif_init()
|
||||
{
|
||||
int i;
|
||||
|
||||
unsigned char code *ptr1;
|
||||
unsigned char xdata *ptr2;
|
||||
|
||||
// ---------------------------------------------------------
|
||||
// 8051 doesn't have access to waveform memories until the
|
||||
// part is in GPIF mode.
|
||||
//
|
||||
// bit[7] (IFCLKSRC) = 1 : internal clock source
|
||||
// bit[6] (xMHz) = 1 : 48 MHz
|
||||
// bit[5] (IFCLKOE) = 1 : enable IFCLK output
|
||||
// bit[4] (IFCLKPOL) = 0 : don't invert IFCLK
|
||||
// bit[3] (ASYNC) = 0 : master synchronous
|
||||
// bit[2] (GSTATE) = 1 : GPIF state -> PORTE[2:0]
|
||||
// bit[1:0] (IFCFG) = 2 : GPIF mode
|
||||
// ---------------------------------------------------------
|
||||
IFCONFIG = 0xe2;
|
||||
|
||||
// ---------------------------------------------------------
|
||||
// abort any waveforms pending
|
||||
// ---------------------------------------------------------
|
||||
GPIFABORT = 0xFF;
|
||||
|
||||
// ---------------------------------------------------------
|
||||
// setup GPIF
|
||||
// ---------------------------------------------------------
|
||||
GPIFREADYCFG = InitData[0];
|
||||
GPIFCTLCFG = InitData[1];
|
||||
GPIFIDLECS = InitData[2];
|
||||
GPIFIDLECTL = InitData[3];
|
||||
GPIFWFSELECT = InitData[5];
|
||||
GPIFREADYSTAT = InitData[6];
|
||||
|
||||
// ---------------------------------------------------------
|
||||
// use dual autopointer feature
|
||||
// ---------------------------------------------------------
|
||||
// AUTOPTRSETUP = 7; // increment both pointers
|
||||
// warning: this introduces pdata
|
||||
// holes at E67B (XAUTODAT1)
|
||||
// and E67C (XAUTODAT2)
|
||||
|
||||
// ---------------------------------------------------------
|
||||
// transfer waveform data
|
||||
// ---------------------------------------------------------
|
||||
ptr1 = WaveData;
|
||||
ptr2 = 0xE400;
|
||||
|
||||
for( i=0; i<128; i++)
|
||||
ptr2[i] = ptr1[i];
|
||||
|
||||
// ---------------------------------------------------------
|
||||
// configure GPIF address pins
|
||||
// ---------------------------------------------------------
|
||||
// PORTCCFG = 0xFF; // PC[7:0] -> GPIFADR[7:0]
|
||||
// PORTECFG |= 0x80; // PE[8] -> GPIFADR[8]
|
||||
//
|
||||
// OEC = 0xFF; // PC[7:0] output
|
||||
// OEE |= 0x80; // PE[8] output
|
||||
|
||||
// ---------------------------------------------------------
|
||||
// GPIF address pins update when GPIFADRH/L writen
|
||||
// ---------------------------------------------------------
|
||||
// GPIFADRH = 0x00; SYNCDELAY;
|
||||
// GPIFADRL = 0x00; SYNCDELAY;
|
||||
|
||||
// ---------------------------------------------------------
|
||||
// configure GPIF flowstate registers for Wave 0
|
||||
// ---------------------------------------------------------
|
||||
fx2_gpif_flowstate(0);
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// ============================================================================
|
||||
void fx2_gpif_flowstate( int sel)
|
||||
{
|
||||
if( sel >= 0 && sel <4)
|
||||
{
|
||||
FLOWSTATE = FlowStates[sel*9+0]; SYNCDELAY;
|
||||
FLOWLOGIC = FlowStates[sel*9+1]; SYNCDELAY;
|
||||
FLOWEQ0CTL = FlowStates[sel*9+2]; SYNCDELAY;
|
||||
FLOWEQ1CTL = FlowStates[sel*9+3]; SYNCDELAY;
|
||||
FLOWHOLDOFF = FlowStates[sel*9+4]; SYNCDELAY;
|
||||
FLOWSTB = FlowStates[sel*9+5]; SYNCDELAY;
|
||||
FLOWSTBEDGE = FlowStates[sel*9+6]; SYNCDELAY;
|
||||
FLOWSTBHPERIOD = FlowStates[sel*9+7]; SYNCDELAY;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,484 @@
|
||||
#include <fx2.h>
|
||||
#include <fx2_regs.h>
|
||||
#include <fx2_i2c.h>
|
||||
//#include <fx2_critical.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
BYTE length;
|
||||
BYTE count;
|
||||
BYTE status;
|
||||
|
||||
BYTE i2caddr; //
|
||||
BYTE subaddr[2]; // for read with repeated start condition
|
||||
|
||||
BYTE address; // SMBus address
|
||||
BYTE cmd; // SMBus command
|
||||
|
||||
BYTE xdata *dat;
|
||||
} I2CPACKET;
|
||||
|
||||
I2CPACKET volatile I2CPacket;
|
||||
|
||||
static bool i2c_read( BYTE addr, BYTE length, BYTE xdata *dat);
|
||||
static bool i2c_write( BYTE addr, BYTE length, BYTE xdata *dat);
|
||||
|
||||
static bool i2c_read_rsw( BYTE addr, WORD subaddr,BYTE length, BYTE xdata *dat);
|
||||
|
||||
|
||||
|
||||
// =================================================================================================
|
||||
// Init
|
||||
// =================================================================================================
|
||||
void fx2_i2c_init()
|
||||
{
|
||||
I2CPacket.length= 0;
|
||||
I2CPacket.count = 0;
|
||||
I2CPacket.status= I2C_IDLE;
|
||||
|
||||
I2CTL &= ~bm400KHZ; // 100 kHz
|
||||
|
||||
// I2CTL |= bm400KHZ; // 400 kHz
|
||||
// I2CTL |= bmSTOPIE; // Enable I2C STOP interrupt
|
||||
|
||||
PI2C = 1;
|
||||
EI2C = 1; // Enable I2C interrupt
|
||||
}
|
||||
|
||||
// =================================================================================================
|
||||
// wait for I2C operation finish
|
||||
// =================================================================================================
|
||||
static BYTE i2c_wait()
|
||||
{
|
||||
while( true)
|
||||
{
|
||||
switch( I2CPacket.status)
|
||||
{
|
||||
case I2C_IDLE:
|
||||
return I2C_OK;
|
||||
|
||||
case I2C_ABORT:
|
||||
I2CPacket.status = I2C_IDLE;
|
||||
return I2C_ABORT;
|
||||
|
||||
case I2C_NACK:
|
||||
I2CPacket.status = I2C_IDLE;
|
||||
return I2C_NACK;
|
||||
|
||||
case I2C_BERROR:
|
||||
I2CPacket.status = I2C_IDLE;
|
||||
return I2C_BERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// =================================================================================================
|
||||
// Read with Repeated Start condition (16 bit subaddress)
|
||||
// =================================================================================================
|
||||
BYTE fx2_i2c_read_rsw( BYTE addr, WORD subaddr, BYTE length, BYTE xdata *dat)
|
||||
{
|
||||
BYTE rc = I2C_ERROR;
|
||||
|
||||
if( i2c_read_rsw( addr, subaddr, length, dat))
|
||||
rc = i2c_wait();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
// =================================================================================================
|
||||
// Read
|
||||
// =================================================================================================
|
||||
BYTE fx2_i2c_read( BYTE addr, BYTE length, BYTE xdata *dat)
|
||||
{
|
||||
BYTE rc = I2C_ERROR;
|
||||
|
||||
if( i2c_read( addr, length, dat))
|
||||
rc = i2c_wait();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
// =================================================================================================
|
||||
// Write
|
||||
// =================================================================================================
|
||||
BYTE fx2_i2c_write( BYTE addr, BYTE length, BYTE xdata *dat)
|
||||
{
|
||||
BYTE rc = I2C_ERROR;
|
||||
|
||||
if( i2c_write( addr, length, dat))
|
||||
{
|
||||
while( true)
|
||||
{
|
||||
switch( I2CPacket.status)
|
||||
{
|
||||
case I2C_IDLE:
|
||||
return I2C_OK;
|
||||
|
||||
case I2C_NACK:
|
||||
I2CPacket.status = I2C_IDLE;
|
||||
return I2C_NACK;
|
||||
|
||||
case I2C_BERROR:
|
||||
I2CPacket.status = I2C_IDLE;
|
||||
return I2C_BERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
// =================================================================================================
|
||||
// Wait
|
||||
// =================================================================================================
|
||||
BYTE fx2_i2c_wait( BYTE addr)
|
||||
{
|
||||
BYTE cnt;
|
||||
BYTE rc;
|
||||
|
||||
cnt = 200; // "timeout" is 200 cycles
|
||||
EI2C = 0; // disable i2c interrupts
|
||||
|
||||
while( I2CS & bmSTOP)
|
||||
;
|
||||
|
||||
do
|
||||
{
|
||||
// --------------------------------------
|
||||
// Generate START condition and send I2C
|
||||
// address.
|
||||
// --------------------------------------
|
||||
I2CS = I2CS | bmSTART;
|
||||
I2DAT = addr << 1;
|
||||
|
||||
// --------------------------------------
|
||||
// Wait for end of sending.
|
||||
// --------------------------------------
|
||||
while( !(I2CS & bmDONE))
|
||||
;
|
||||
|
||||
// --------------------------------------
|
||||
// Generate STOP condition
|
||||
// --------------------------------------
|
||||
I2CS = I2CS | bmSTOP;
|
||||
|
||||
// --------------------------------------
|
||||
// Wait for stop condition finishing.
|
||||
// --------------------------------------
|
||||
while( (I2CS & bmSTOP))
|
||||
;
|
||||
|
||||
// --------------------------------------
|
||||
// Decrement "timeout" counter.
|
||||
// --------------------------------------
|
||||
cnt--;
|
||||
} while( !(I2CS & bmACK) && cnt);
|
||||
|
||||
I2CPacket.status = I2C_IDLE;
|
||||
|
||||
rc = (I2CS & bmACK) ? I2C_OK : I2C_NACK;
|
||||
|
||||
EI2C = 1; // enable I2C interrupts
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
//
|
||||
// SMBus implementation
|
||||
//
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
BYTE fx2_sm_readword( BYTE addr, BYTE command, BYTE xdata *dat)
|
||||
{
|
||||
BYTE rc = I2C_ERROR;
|
||||
|
||||
while(I2CS & bmSTOP)
|
||||
;
|
||||
|
||||
if( I2CPacket.status == I2C_IDLE)
|
||||
{
|
||||
I2CS |= bmSTART;
|
||||
I2DAT = addr << 1;
|
||||
|
||||
I2CPacket.address = addr;
|
||||
I2CPacket.count = 0;
|
||||
I2CPacket.cmd = command;
|
||||
I2CPacket.dat = dat;
|
||||
I2CPacket.length = 2;
|
||||
I2CPacket.status = SMB_CMD_READWORD;
|
||||
|
||||
|
||||
while( true)
|
||||
{
|
||||
switch( I2CPacket.status)
|
||||
{
|
||||
case I2C_IDLE:
|
||||
return I2C_OK;
|
||||
|
||||
case I2C_ABORT:
|
||||
I2CPacket.status = I2C_IDLE;
|
||||
return I2C_ABORT;
|
||||
|
||||
case I2C_NACK:
|
||||
I2CPacket.status = I2C_IDLE;
|
||||
return I2C_NACK;
|
||||
|
||||
case I2C_BERROR:
|
||||
I2CPacket.status = I2C_IDLE;
|
||||
return I2C_BERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
//
|
||||
// INTERNAL ROUTINES
|
||||
//
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
// =================================================================================================
|
||||
// i2c_write
|
||||
// =================================================================================================
|
||||
static bool i2c_write( BYTE addr, BYTE length, BYTE xdata *dat)
|
||||
{
|
||||
while( I2CS & bmSTOP)
|
||||
;
|
||||
|
||||
if( I2CPacket.status == I2C_IDLE)
|
||||
{
|
||||
I2CS |= bmSTART;
|
||||
I2DAT = addr << 1;
|
||||
|
||||
I2CPacket.count = 0;
|
||||
I2CPacket.dat = dat;
|
||||
I2CPacket.length = length;
|
||||
I2CPacket.status = I2C_SENDING;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// =================================================================================================
|
||||
// i2c_read
|
||||
// =================================================================================================
|
||||
static bool i2c_read( BYTE addr, BYTE length, BYTE xdata *dat)
|
||||
{
|
||||
while( I2CS & bmSTOP)
|
||||
;
|
||||
|
||||
if( I2CPacket.status == I2C_IDLE)
|
||||
{
|
||||
I2CS |= bmSTART;
|
||||
I2DAT = (addr << 1) | 0x01;
|
||||
|
||||
I2CPacket.count = 0;
|
||||
I2CPacket.dat = dat;
|
||||
I2CPacket.length = length;
|
||||
I2CPacket.status = I2C_PRIME;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// =================================================================================================
|
||||
// i2c_read_rs
|
||||
// =================================================================================================
|
||||
static bool i2c_read_rsw( BYTE addr, WORD subaddr, BYTE length, BYTE xdata *dat)
|
||||
{
|
||||
while( I2CS & bmSTOP)
|
||||
;
|
||||
|
||||
if( I2CPacket.status == I2C_IDLE)
|
||||
{
|
||||
I2CS |= bmSTART;
|
||||
I2DAT = addr << 1;
|
||||
|
||||
I2CPacket.i2caddr = addr;
|
||||
|
||||
I2CPacket.subaddr[0]= subaddr >> 8;
|
||||
I2CPacket.subaddr[1]= subaddr;
|
||||
|
||||
I2CPacket.count = 0;
|
||||
I2CPacket.dat = dat;
|
||||
I2CPacket.length = length;
|
||||
I2CPacket.status = I2C_SUBADDR_HI;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
//
|
||||
// I2C INTERRUPT HANDLER
|
||||
//
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
// =================================================================================================
|
||||
// i2c_isr
|
||||
//
|
||||
// TODO: IMplement I2C_ABORT
|
||||
// =================================================================================================
|
||||
void i2c_isr() interrupt 9
|
||||
{
|
||||
BYTE PEC;
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
// BUS error. Arbitration lost.
|
||||
// ------------------------------------------------------------------------
|
||||
if( I2CS & bmBERR)
|
||||
{
|
||||
I2CS |= bmSTOP;
|
||||
I2CPacket.status = I2C_BERROR;
|
||||
}
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
// NACK
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
else if((!(I2CS & bmACK)) && (I2CPacket.status != I2C_RECEIVING))
|
||||
{
|
||||
I2CS |= bmSTOP;
|
||||
I2CPacket.status = I2C_NACK;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
switch( I2CPacket.status)
|
||||
{
|
||||
case SMB_CMD_READWORD:
|
||||
I2CPacket.count = 0;
|
||||
I2CPacket.status = SMB_READWORD;
|
||||
I2DAT = I2CPacket.cmd;
|
||||
break;
|
||||
|
||||
case SMB_READWORD:
|
||||
switch( I2CPacket.count)
|
||||
{
|
||||
case 0:
|
||||
I2CPacket.count = 1;
|
||||
I2CS |= bmSTART;
|
||||
I2DAT = (I2CPacket.address << 1) | 0x01;
|
||||
break;
|
||||
|
||||
// address sent, trigger next byte read with a dummy read
|
||||
case 1:
|
||||
I2CPacket.count = 2;
|
||||
I2CPacket.dat[0] = I2DAT;
|
||||
break;
|
||||
|
||||
// read low byte
|
||||
case 2:
|
||||
I2CPacket.count = 3;
|
||||
I2CPacket.dat[0] = I2DAT;
|
||||
break;
|
||||
|
||||
// read high byte
|
||||
case 3:
|
||||
I2CPacket.count = 4;
|
||||
I2CPacket.dat[1] = I2DAT;
|
||||
break;
|
||||
|
||||
case 4:
|
||||
I2CS |= bmSTOP;
|
||||
PEC = I2DAT;
|
||||
I2CPacket.status = I2C_IDLE;
|
||||
break;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case I2C_SENDING:
|
||||
I2DAT = I2CPacket.dat[I2CPacket.count++];
|
||||
|
||||
if( I2CPacket.count == I2CPacket.length)
|
||||
I2CPacket.status = I2C_STOP;
|
||||
|
||||
break;
|
||||
|
||||
case I2C_PRIME:
|
||||
I2CPacket.dat[I2CPacket.count] = I2DAT;
|
||||
I2CPacket.status = I2C_RECEIVING;
|
||||
|
||||
if( I2CPacket.length == 1)
|
||||
I2CS |= bmLASTRD;
|
||||
|
||||
break;
|
||||
|
||||
case I2C_RECEIVING:
|
||||
if( I2CPacket.count == I2CPacket.length -2)
|
||||
I2CS |= bmLASTRD;
|
||||
|
||||
if( I2CPacket.count == I2CPacket.length -1)
|
||||
{
|
||||
I2CS |= bmSTOP;
|
||||
I2CPacket.status = I2C_IDLE;
|
||||
}
|
||||
|
||||
I2CPacket.dat[I2CPacket.count++] = I2DAT;
|
||||
break;
|
||||
|
||||
// read with repeated start
|
||||
// ---------------------------------------------
|
||||
case I2C_SUBADDR_HI:
|
||||
I2DAT = I2CPacket.subaddr[0];
|
||||
I2CPacket.status = I2C_SUBADDR_LO;
|
||||
break;
|
||||
|
||||
case I2C_SUBADDR_LO:
|
||||
I2DAT = I2CPacket.subaddr[1];
|
||||
I2CPacket.status = I2C_RESTART;
|
||||
break;
|
||||
|
||||
case I2C_RESTART:
|
||||
I2CS |= bmSTART;
|
||||
I2DAT = (I2CPacket.i2caddr << 1) | 0x01;
|
||||
|
||||
I2CPacket.status = I2C_PRIME;
|
||||
break;
|
||||
|
||||
|
||||
// ---------------------------------------------
|
||||
case I2C_STOP:
|
||||
I2CS |= bmSTOP;
|
||||
I2CPacket.status = I2C_IDLE;
|
||||
break;
|
||||
|
||||
case I2C_WAITSTOP:
|
||||
I2CPacket.status = I2C_IDLE;
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
EXIF &= ~0x20;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,61 @@
|
||||
#include <fx2.h>
|
||||
#include <fx2_regs.h>
|
||||
#include <fx2_syncdelay.h>
|
||||
|
||||
// ============================================================================
|
||||
// FX2_Init
|
||||
//
|
||||
// Standard FX2 initialization.
|
||||
// ============================================================================
|
||||
bool FX2_Init(void)
|
||||
{
|
||||
// --------------------------------------------------------------
|
||||
// Initialize hardware
|
||||
//
|
||||
// - Set CPU clock to 48 MHz.
|
||||
//
|
||||
// bmCLKSPD0: 24 MHz
|
||||
// bmCLKSPD1: 48 MHz
|
||||
// --------------------------------------------------------------
|
||||
CPUCS |= bmCLKSPD1; SYNCDELAY;
|
||||
|
||||
// --------------------------------------------------------------
|
||||
// - Set IFCLK to CLK (internal clock is 48 MHz)
|
||||
// - Set PORT mode on all pin.
|
||||
// --------------------------------------------------------------
|
||||
IFCONFIG = bmIFCLKSRC | bm3048MHZ; SYNCDELAY; // 48 MHz
|
||||
IFCONFIG |= 0x20; SYNCDELAY; // Enable IFCLK
|
||||
IFCONFIG &= 0xFC; SYNCDELAY; // Port mode
|
||||
|
||||
// --------------------------------------------------------------
|
||||
// No endpoints are used
|
||||
// --------------------------------------------------------------
|
||||
EP1INCFG = 0x20; SYNCDELAY; // invalid, in, bulk, 64, 1x
|
||||
EP1OUTCFG = 0x20; SYNCDELAY; // invalid, out, bulk, 64, 1x
|
||||
|
||||
EP2CFG = 0x22; SYNCDELAY; // invalid, out, bulk, 512, 2x
|
||||
EP6CFG = 0x22; SYNCDELAY; // invalid, out, bulk, 512, 2x
|
||||
EP4CFG = 0x20; SYNCDELAY; // invalid, out, bulk, 512, 2x
|
||||
EP8CFG = 0x20; SYNCDELAY; // invalid, out, bulk, 512, 2x
|
||||
|
||||
// --------------------------------------------------------------
|
||||
// FIFO configuration
|
||||
//
|
||||
// (temp: switch off WORDWIDE bit)
|
||||
// --------------------------------------------------------------
|
||||
EP2FIFOCFG = 0x00;
|
||||
EP4FIFOCFG = 0x00;
|
||||
EP6FIFOCFG = 0x00;
|
||||
EP8FIFOCFG = 0x00;
|
||||
|
||||
// --------------------------------------------------------------
|
||||
// IO PORTA Alternate Configuration
|
||||
//
|
||||
// PA7 - standard IO, not FALGD nor SLCS
|
||||
// PA1 - standard IO, not INT1
|
||||
// PA0 - standard IO, not INT0
|
||||
// --------------------------------------------------------------
|
||||
PORTACFG = 0x00; SYNCDELAY;
|
||||
|
||||
return true;
|
||||
}
|
||||
@@ -0,0 +1,109 @@
|
||||
ISR MACRO routine
|
||||
ljmp routine
|
||||
nop
|
||||
ENDM
|
||||
|
||||
NAME UsbJmpTbl
|
||||
|
||||
EXTRN code (ISR_sudav, ISR_sof, ISR_sutok, ISR_susp, ISR_ures)
|
||||
EXTRN code (ISR_highspeed, ISR_ep0ack, ISR_stub, ISR_ibn, ISR_errorlimit)
|
||||
EXTRN code (ISR_ep0in, ISR_ep0out, ISR_ep1in, ISR_ep1out)
|
||||
EXTRN code (ISR_ep2inout, ISR_ep4inout, ISR_ep6inout, ISR_ep8inout)
|
||||
|
||||
EXTRN code (ISR_ep0pingnak, ISR_ep1pingnak)
|
||||
|
||||
EXTRN code (ISR_ep2pingnak, ISR_ep4pingnak, ISR_ep6pingnak, ISR_ep8pingnak)
|
||||
EXTRN code (ISR_ep2piderror, ISR_ep4piderror,ISR_ep6piderror,ISR_ep8piderror)
|
||||
EXTRN code (ISR_ep2pflag, ISR_ep4pflag, ISR_ep6pflag, ISR_ep8pflag)
|
||||
EXTRN code (ISR_ep2eflag, ISR_ep4eflag, ISR_ep6eflag, ISR_ep8eflag)
|
||||
EXTRN code (ISR_ep2fflag, ISR_ep4fflag, ISR_ep6fflag, ISR_ep8fflag)
|
||||
|
||||
EXTRN code (ISR_gpifcomplete)
|
||||
EXTRN code (ISR_gpifwaveform)
|
||||
|
||||
;; --------------------------------------------------------------------
|
||||
;; Interrupt vectors
|
||||
;; --------------------------------------------------------------------
|
||||
cseg at 43h
|
||||
ljmp JumpTable ; Autovector will replace byte at 45h
|
||||
|
||||
cseg at 53h
|
||||
ljmp JumpTable ; Autovector will replace byte at 55h
|
||||
|
||||
;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
;;
|
||||
;; USB Jump Table
|
||||
;;
|
||||
;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
;; ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
USBJT segment code page
|
||||
rseg USBJT
|
||||
|
||||
JumpTable:
|
||||
;; --------------------------------------------------------------------
|
||||
;; INT2 - USB Interrupts
|
||||
;; --------------------------------------------------------------------
|
||||
ISR ISR_sudav ;(00) Setup Data Available
|
||||
ISR ISR_sof ;(04) Start of Frame
|
||||
ISR ISR_sutok ;(08) Setup Data Loading
|
||||
ISR ISR_susp ;(0C) Global Suspend
|
||||
ISR ISR_ures ;(10) USB Reset
|
||||
ISR ISR_highspeed ;(14) Entered High Speed
|
||||
ISR ISR_ep0ack ;(18) EP0ACK
|
||||
ISR ISR_stub ;(1C) reserved
|
||||
|
||||
ISR ISR_ep0in ;(20) EP0 In
|
||||
ISR ISR_ep0out ;(24) EP0 Out
|
||||
ISR ISR_ep1in ;(28) EP1 In
|
||||
ISR ISR_ep1out ;(2C) EP1 Out
|
||||
ISR ISR_ep2inout ;(30) EP2 In/Out
|
||||
ISR ISR_ep4inout ;(34) EP4 In/Out
|
||||
ISR ISR_ep6inout ;(38) EP6 In/Out
|
||||
ISR ISR_ep8inout ;(3C) EP8 In/Out
|
||||
|
||||
ISR ISR_ibn ;(40) IBN (IN-Bulk-NAK [any IN endpoint])
|
||||
ISR ISR_stub ;(44) reserved
|
||||
|
||||
ISR ISR_ep0pingnak ;(48) EP0 out was pinged and it NAK'd
|
||||
ISR ISR_ep1pingnak ;(4C) EP1 out was pinged and it NAK'd
|
||||
ISR ISR_ep2pingnak ;(50) EP2 out was pinged and it NAK'd
|
||||
ISR ISR_ep4pingnak ;(54) EP4 out was pinged and it NAK'd
|
||||
ISR ISR_ep6pingnak ;(58) EP6 out was pinged and it NAK'd
|
||||
ISR ISR_ep8pingnak ;(5C) EP8 out was pinged and it NAK'd
|
||||
|
||||
ISR ISR_errorlimit ;(60) Bus errors exceeded the programmed limit
|
||||
|
||||
ISR ISR_stub ;(64) reserved
|
||||
ISR ISR_stub ;(68) reserved
|
||||
ISR ISR_stub ;(6C) reserved
|
||||
|
||||
ISR ISR_ep2piderror ;(70) EP2 ISO Pid Sequence Error
|
||||
ISR ISR_ep4piderror ;(74) EP4 ISO Pid Sequence Error
|
||||
ISR ISR_ep6piderror ;(78) EP6 ISO Pid Sequence Error
|
||||
ISR ISR_ep8piderror ;(7C) EP8 ISO Pid Sequence Error
|
||||
|
||||
;; --------------------------------------------------------------------
|
||||
;; INT4 - FIFO/GPIF Interrupts
|
||||
;; --------------------------------------------------------------------
|
||||
ISR ISR_ep2pflag ;(80) EP2 Programmable Flag
|
||||
ISR ISR_ep4pflag ;(84) EP4 Programmable Flag
|
||||
ISR ISR_ep6pflag ;(88) EP6 Programmable Flag
|
||||
ISR ISR_ep8pflag ;(8C) EP8 Programmable Flag
|
||||
|
||||
ISR ISR_ep2eflag ;(90) EP2 Empty Flag
|
||||
ISR ISR_ep4eflag ;(94) EP4 Empty Flag
|
||||
ISR ISR_ep6eflag ;(98) EP6 Empty Flag
|
||||
ISR ISR_ep8eflag ;(9C) EP8 Empty Flag
|
||||
|
||||
ISR ISR_ep2fflag ;(A0) EP2 Full Flag
|
||||
ISR ISR_ep4fflag ;(A4) EP4 Full Flag
|
||||
ISR ISR_ep6fflag ;(A8) EP6 Full Flag
|
||||
ISR ISR_ep8fflag ;(AC) EP8 Full Flag
|
||||
|
||||
ISR ISR_gpifcomplete ;(B0) GPIF Operation Complete
|
||||
ISR ISR_gpifwaveform ;(B4) GPIF Waveform
|
||||
|
||||
END
|
||||
@@ -0,0 +1,198 @@
|
||||
$NOMOD51
|
||||
;------------------------------------------------------------------------------
|
||||
; This file is part of the C51 Compiler package
|
||||
; Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc.
|
||||
; Version 8.01
|
||||
;
|
||||
; *** <<< Use Configuration Wizard in Context Menu >>> ***
|
||||
;------------------------------------------------------------------------------
|
||||
; STARTUP.A51: This code is executed after processor reset.
|
||||
;
|
||||
; To translate this file use A51 with the following invocation:
|
||||
;
|
||||
; A51 STARTUP.A51
|
||||
;
|
||||
; To link the modified STARTUP.OBJ file to your application use the following
|
||||
; Lx51 invocation:
|
||||
;
|
||||
; Lx51 your object file list, STARTUP.OBJ controls
|
||||
;
|
||||
;------------------------------------------------------------------------------
|
||||
;
|
||||
; User-defined <h> Power-On Initialization of Memory
|
||||
;
|
||||
; With the following EQU statements the initialization of memory
|
||||
; at processor reset can be defined:
|
||||
;
|
||||
; <o> IDATALEN: IDATA memory size <0x0-0x100>
|
||||
; <i> Note: The absolute start-address of IDATA memory is always 0
|
||||
; <i> The IDATA space overlaps physically the DATA and BIT areas.
|
||||
IDATALEN EQU 80H
|
||||
;
|
||||
; <o> XDATASTART: XDATA memory start address <0x0-0xFFFF>
|
||||
; <i> The absolute start address of XDATA memory
|
||||
XDATASTART EQU 0
|
||||
;
|
||||
; <o> XDATALEN: XDATA memory size <0x0-0xFFFF>
|
||||
; <i> The length of XDATA memory in bytes.
|
||||
XDATALEN EQU 0
|
||||
;
|
||||
; <o> PDATASTART: PDATA memory start address <0x0-0xFFFF>
|
||||
; <i> The absolute start address of PDATA memory
|
||||
PDATASTART EQU 0H
|
||||
;
|
||||
; <o> PDATALEN: PDATA memory size <0x0-0xFF>
|
||||
; <i> The length of PDATA memory in bytes.
|
||||
PDATALEN EQU 0H
|
||||
;
|
||||
;</h>
|
||||
;------------------------------------------------------------------------------
|
||||
;
|
||||
;<h> Reentrant Stack Initialization
|
||||
;
|
||||
; The following EQU statements define the stack pointer for reentrant
|
||||
; functions and initialized it:
|
||||
;
|
||||
; <h> Stack Space for reentrant functions in the SMALL model.
|
||||
; <q> IBPSTACK: Enable SMALL model reentrant stack
|
||||
; <i> Stack space for reentrant functions in the SMALL model.
|
||||
IBPSTACK EQU 0 ; set to 1 if small reentrant is used.
|
||||
; <o> IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF>
|
||||
; <i> Set the top of the stack to the highest location.
|
||||
IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
|
||||
; </h>
|
||||
;
|
||||
; <h> Stack Space for reentrant functions in the LARGE model.
|
||||
; <q> XBPSTACK: Enable LARGE model reentrant stack
|
||||
; <i> Stack space for reentrant functions in the LARGE model.
|
||||
XBPSTACK EQU 0 ; set to 1 if large reentrant is used.
|
||||
; <o> XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF>
|
||||
; <i> Set the top of the stack to the highest location.
|
||||
XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1
|
||||
; </h>
|
||||
;
|
||||
; <h> Stack Space for reentrant functions in the COMPACT model.
|
||||
; <q> PBPSTACK: Enable COMPACT model reentrant stack
|
||||
; <i> Stack space for reentrant functions in the COMPACT model.
|
||||
PBPSTACK EQU 0 ; set to 1 if compact reentrant is used.
|
||||
;
|
||||
; <o> PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF>
|
||||
; <i> Set the top of the stack to the highest location.
|
||||
PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
|
||||
; </h>
|
||||
;</h>
|
||||
;------------------------------------------------------------------------------
|
||||
;
|
||||
; Memory Page for Using the Compact Model with 64 KByte xdata RAM
|
||||
; <e>Compact Model Page Definition
|
||||
;
|
||||
; <i>Define the XDATA page used for PDATA variables.
|
||||
; <i>PPAGE must conform with the PPAGE set in the linker invocation.
|
||||
;
|
||||
; Enable pdata memory page initalization
|
||||
PPAGEENABLE EQU 0 ; set to 1 if pdata object are used.
|
||||
;
|
||||
; <o> PPAGE number <0x0-0xFF>
|
||||
; <i> uppermost 256-byte address of the page used for PDATA variables.
|
||||
PPAGE EQU 0
|
||||
;
|
||||
; <o> SFR address which supplies uppermost address byte <0x0-0xFF>
|
||||
; <i> most 8051 variants use P2 as uppermost address byte
|
||||
PPAGE_SFR DATA 0A0H
|
||||
;
|
||||
; </e>
|
||||
;------------------------------------------------------------------------------
|
||||
|
||||
; Standard SFR Symbols
|
||||
ACC DATA 0E0H
|
||||
B DATA 0F0H
|
||||
SP DATA 81H
|
||||
DPL DATA 82H
|
||||
DPH DATA 83H
|
||||
|
||||
NAME ?C_STARTUP
|
||||
|
||||
|
||||
?C_C51STARTUP SEGMENT CODE
|
||||
?STACK SEGMENT IDATA
|
||||
|
||||
RSEG ?STACK
|
||||
DS 1
|
||||
|
||||
EXTRN CODE (?C_START)
|
||||
PUBLIC ?C_STARTUP
|
||||
|
||||
CSEG AT 0
|
||||
?C_STARTUP: LJMP STARTUP1
|
||||
|
||||
RSEG ?C_C51STARTUP
|
||||
|
||||
STARTUP1:
|
||||
|
||||
IF IDATALEN <> 0
|
||||
MOV R0,#IDATALEN - 1
|
||||
CLR A
|
||||
IDATALOOP: MOV @R0,A
|
||||
DJNZ R0,IDATALOOP
|
||||
ENDIF
|
||||
|
||||
IF XDATALEN <> 0
|
||||
MOV DPTR,#XDATASTART
|
||||
MOV R7,#LOW (XDATALEN)
|
||||
IF (LOW (XDATALEN)) <> 0
|
||||
MOV R6,#(HIGH (XDATALEN)) +1
|
||||
ELSE
|
||||
MOV R6,#HIGH (XDATALEN)
|
||||
ENDIF
|
||||
CLR A
|
||||
XDATALOOP: MOVX @DPTR,A
|
||||
INC DPTR
|
||||
DJNZ R7,XDATALOOP
|
||||
DJNZ R6,XDATALOOP
|
||||
ENDIF
|
||||
|
||||
IF PPAGEENABLE <> 0
|
||||
MOV PPAGE_SFR,#PPAGE
|
||||
ENDIF
|
||||
|
||||
IF PDATALEN <> 0
|
||||
MOV R0,#LOW (PDATASTART)
|
||||
MOV R7,#LOW (PDATALEN)
|
||||
CLR A
|
||||
PDATALOOP: MOVX @R0,A
|
||||
INC R0
|
||||
DJNZ R7,PDATALOOP
|
||||
ENDIF
|
||||
|
||||
IF IBPSTACK <> 0
|
||||
EXTRN DATA (?C_IBP)
|
||||
|
||||
MOV ?C_IBP,#LOW IBPSTACKTOP
|
||||
ENDIF
|
||||
|
||||
IF XBPSTACK <> 0
|
||||
EXTRN DATA (?C_XBP)
|
||||
|
||||
MOV ?C_XBP,#HIGH XBPSTACKTOP
|
||||
MOV ?C_XBP+1,#LOW XBPSTACKTOP
|
||||
ENDIF
|
||||
|
||||
IF PBPSTACK <> 0
|
||||
EXTRN DATA (?C_PBP)
|
||||
MOV ?C_PBP,#LOW PBPSTACKTOP
|
||||
ENDIF
|
||||
|
||||
MOV SP,#?STACK-1
|
||||
|
||||
; This code is required if you use L51_BANK.A51 with Banking Mode 4
|
||||
;<h> Code Banking
|
||||
; <q> Select Bank 0 for L51_BANK.A51 Mode 4
|
||||
#if 0
|
||||
; <i> Initialize bank mechanism to code bank 0 when using L51_BANK.A51 with Banking Mode 4.
|
||||
EXTRN CODE (?B_SWITCH0)
|
||||
CALL ?B_SWITCH0 ; init bank mechanism to code bank 0
|
||||
#endif
|
||||
;</h>
|
||||
LJMP ?C_START
|
||||
|
||||
END
|
||||
@@ -0,0 +1,51 @@
|
||||
#include <fx2.h>
|
||||
#include <fx2_regs.h>
|
||||
|
||||
// =================================================================================================
|
||||
// init
|
||||
// =================================================================================================
|
||||
//void fx2_tmr_init( void)
|
||||
//{
|
||||
// ---------------------------------------------------------------
|
||||
// timer 0: system tick (1 ms @ 48 MHz)
|
||||
// ---------------------------------------------------------------
|
||||
|
||||
// CT0 = 0; // souce = system clock
|
||||
// T0M = 0; // freq. = 4 MHz (48 MHz / 12)
|
||||
|
||||
// TL0 = 0x60; // divider
|
||||
// TH0 = 0xF0; //
|
||||
|
||||
// M10 = 0; // 16 bit counter mode
|
||||
// M00 = 1; //
|
||||
|
||||
// ET0 = 1; // enable interrupt
|
||||
// TR0 = 1; // enable timer
|
||||
|
||||
// PD7 = 1;
|
||||
// ---------------------------------------------------------------
|
||||
// timer 1: baud rate generator for serial ports (128 pin only)
|
||||
// ---------------------------------------------------------------
|
||||
//}
|
||||
|
||||
// =================================================================================================
|
||||
// timer 0 interrupt service routine
|
||||
// =================================================================================================
|
||||
void tmr_isr() interrupt 2
|
||||
{
|
||||
// ---------------------------------------------------------------
|
||||
// update timer
|
||||
// ---------------------------------------------------------------
|
||||
TR0 = 0; // disable timer
|
||||
//
|
||||
TL0 = 0x60; // divider
|
||||
TH0 = 0xF0; //
|
||||
//
|
||||
TR0 = 1; // enable timer
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
//
|
||||
// ---------------------------------------------------------------
|
||||
PD7 = 1;//(PD7) ? 0 : 1;
|
||||
|
||||
}
|
||||
@@ -0,0 +1,44 @@
|
||||
NAME FX2_TIMER
|
||||
PUBLIC fx2_tmr_init
|
||||
|
||||
;; ---------------------------------------------------
|
||||
;; interrupt vectors
|
||||
;; ---------------------------------------------------
|
||||
cseg at 0bh
|
||||
ljmp isr_tm0
|
||||
|
||||
|
||||
|
||||
|
||||
TIMER segment code page
|
||||
rseg TIMER
|
||||
|
||||
fx2_tmr_init:
|
||||
; clr CT0
|
||||
; clr T0M
|
||||
|
||||
mov TL0, #060h
|
||||
mov TH0, #0F0h
|
||||
|
||||
orl TMOD,#01H ; Timer 0 Mode 1
|
||||
|
||||
setb TR0
|
||||
setb ET0
|
||||
|
||||
; setb PD7
|
||||
|
||||
ret
|
||||
|
||||
isr_tm0: clr TR0
|
||||
|
||||
mov TL0, #060h
|
||||
mov TH0, #0F0h
|
||||
|
||||
setb TR0
|
||||
|
||||
|
||||
|
||||
|
||||
reti
|
||||
|
||||
end
|
||||
@@ -0,0 +1,228 @@
|
||||
#include <fx2.h>
|
||||
#include <fx2_regs.h>
|
||||
#include <fx2_usart.h>
|
||||
#include <fx2_syncdelay.h>
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
BYTE length;
|
||||
BYTE count;
|
||||
BYTE status;
|
||||
BYTE xdata *dat;
|
||||
BYTE xdata *pause;
|
||||
} USART_PACKET;
|
||||
|
||||
static USART_PACKET volatile UsartPacket;
|
||||
/*
|
||||
I2CPacket.length= 0;
|
||||
I2CPacket.count = 0;
|
||||
I2CPacket.status= I2C_IDLE;
|
||||
|
||||
I2CTL &= ~bm400KHZ; // 100 kHz
|
||||
|
||||
PI2C = 1;
|
||||
EI2C = 1; // Enable I2C interrupt
|
||||
*/
|
||||
|
||||
static bool usart_send( BYTE length, BYTE xdata *dat, BYTE xdata *pause);
|
||||
|
||||
static unsigned short usart0_baud;
|
||||
static usart_cfg usart0_cfg;
|
||||
|
||||
// =================================================================================================
|
||||
// fx2_usart_init
|
||||
// =================================================================================================
|
||||
void fx2_usart_init( unsigned short baud, usart_cfg cfg)
|
||||
{
|
||||
usart0_baud = baud;
|
||||
usart0_cfg = cfg;
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
// Initialize packet
|
||||
// ---------------------------------------------------------------
|
||||
UsartPacket.dat = 0;
|
||||
UsartPacket.length = 0;
|
||||
UsartPacket.count = 0;
|
||||
UsartPacket.status = USART_IDLE;
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
// Setup TMR1 as a baudrate generator. Timer mode 2.
|
||||
//
|
||||
// Reload values (TH1) for 48 MHz CLKOUt:
|
||||
//
|
||||
// 57600 : 0xF3 ( 57692 +0.16%)
|
||||
// 38400 : 0xEC ( 37500 -2.34%)
|
||||
// 19200 : 0xD9 ( 19230 +0.16%)
|
||||
// 9600 : 0xB2 ( 9615 +0.16%)
|
||||
// 4800 : 0x64 ( 4807 +0.16%)
|
||||
// ---------------------------------------------------------------
|
||||
// CT1 = 0; SYNCDELAY; // source = system clock
|
||||
// T1M = 0; SYNCDELAY; // freq. = 4 MHz (48 MHz / 12)
|
||||
// T0M = 0;
|
||||
|
||||
// M11 = 0; SYNCDELAY; // 8 bit mode with auto reload (mode 2)
|
||||
// M01 = 1; SYNCDELAY; //
|
||||
|
||||
|
||||
|
||||
switch( baud)
|
||||
{
|
||||
case 57600 : TH1 = 0xF3; break;
|
||||
case 38400 : TH1 = 0xEC; break;
|
||||
case 19200 : TH1 = 0xD9; break;
|
||||
case 9600 : TH1 = 0xB2; break;
|
||||
case 4800 : TH1 = 0x64; break;
|
||||
|
||||
default : TH1 = 0xB2; break;
|
||||
}
|
||||
|
||||
SMOD1 = 1;
|
||||
|
||||
CKCON = 0x38; SYNCDELAY;
|
||||
TMOD = 0x20; SYNCDELAY;
|
||||
|
||||
TR1 = 1; // enable timer
|
||||
|
||||
// ---------------------------------------------------------------
|
||||
// setup USART 0
|
||||
// ---------------------------------------------------------------
|
||||
// TCLK = 0; SYNCDELAY; // use TMR1 as transmit clock
|
||||
// RCLK = 0; SYNCDELAY; // use TMR1 as receive clock
|
||||
|
||||
SCON1 = 0xC8;
|
||||
// SCON0 = 0xD0;
|
||||
//
|
||||
// if( cfg == uc8n1) // 10 bit mode
|
||||
// {
|
||||
// SM0 = 0; // usart mode 1
|
||||
// SM1 = 1;
|
||||
// }
|
||||
//
|
||||
// else // 11 bit modes
|
||||
// {
|
||||
// SM0 = 1; // usart mode 3
|
||||
// SM1 = 1; //
|
||||
//
|
||||
// SM2 = 0; // no multiprocessor communication
|
||||
// }
|
||||
|
||||
// if( cfg == uc8n1) // 10 bit mode
|
||||
// {
|
||||
// SM01 = 0; // usart mode 1
|
||||
// SM11 = 1;
|
||||
// }
|
||||
//
|
||||
// else // 11 bit modes
|
||||
// {
|
||||
// SM01 = 1; // usart mode 3
|
||||
// SM11 = 1; //
|
||||
//
|
||||
// SM2 = 0; // no multiprocessor communication
|
||||
// }
|
||||
|
||||
ES1 = 1; // enable usart1 interrupt
|
||||
//PS1 = 1;
|
||||
}
|
||||
|
||||
|
||||
static void usart_send_byte( BYTE byte, usart_cfg cfg)
|
||||
{
|
||||
switch( cfg)
|
||||
{
|
||||
case uc8n2:
|
||||
TB81 = 1;
|
||||
break;
|
||||
|
||||
case uc8e1:
|
||||
ACC = byte;
|
||||
TB81 = (P) ? 1 : 0;
|
||||
break;
|
||||
|
||||
case uc8o1:
|
||||
ACC = byte;
|
||||
TB81 = (P) ? 0 : 1;
|
||||
break;
|
||||
}
|
||||
|
||||
SBUF1 = byte;
|
||||
}
|
||||
|
||||
|
||||
BYTE fx2_usart_send( BYTE length, BYTE xdata *dat, BYTE xdata *pause)
|
||||
{
|
||||
BYTE rc = USART_ERROR;
|
||||
|
||||
if( usart_send( length, dat, pause))
|
||||
while( UsartPacket.status != USART_IDLE)
|
||||
;
|
||||
|
||||
return USART_ERROR;
|
||||
}
|
||||
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
//
|
||||
// INTERNAL ROUTINES
|
||||
//
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
|
||||
|
||||
// =================================================================================================
|
||||
// usart_send
|
||||
// =================================================================================================
|
||||
static bool usart_send( BYTE length, BYTE xdata *dat, BYTE xdata *pause)
|
||||
{
|
||||
if( UsartPacket.status == USART_IDLE)
|
||||
{
|
||||
usart_send_byte( *dat++, usart0_cfg);
|
||||
|
||||
UsartPacket.count = 0;
|
||||
UsartPacket.length = length;
|
||||
UsartPacket.dat = dat;
|
||||
UsartPacket.pause = pause;
|
||||
|
||||
UsartPacket.status = USART_SENDING;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
extern void FX2_Delay( WORD ms);
|
||||
|
||||
// =================================================================================================
|
||||
// usart interrupt service routine
|
||||
// =================================================================================================
|
||||
void usart_isr() interrupt 7
|
||||
{
|
||||
BYTE pause;
|
||||
|
||||
if( UsartPacket.status == USART_SENDING)
|
||||
{
|
||||
if( UsartPacket.pause)
|
||||
{
|
||||
pause = *UsartPacket.pause++;
|
||||
|
||||
if( pause)
|
||||
FX2_Delay(pause);
|
||||
}
|
||||
|
||||
if( UsartPacket.length == 1)
|
||||
UsartPacket.status = USART_IDLE;
|
||||
|
||||
else
|
||||
{
|
||||
UsartPacket.length--;
|
||||
usart_send_byte( *UsartPacket.dat++, usart0_cfg);
|
||||
}
|
||||
}
|
||||
|
||||
TI1 = 0;
|
||||
|
||||
}
|
||||
@@ -0,0 +1,263 @@
|
||||
#pragma NOIV // Do not generate interrupt vectors
|
||||
|
||||
#include <fx2.h>
|
||||
#include <fx2_regs.h>
|
||||
#include <fx2_syncdelay.h>
|
||||
|
||||
xdata CONFIG_DSCR xdata *pDscrMainConfig;
|
||||
xdata CONFIG_DSCR xdata *pDscrOthrConfig;
|
||||
|
||||
xdata CONFIG_DSCR xdata *pDscrFsConfig;
|
||||
xdata CONFIG_DSCR xdata *pDscrHsConfig;
|
||||
|
||||
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
//
|
||||
// USB Interrupt handler routines.
|
||||
//
|
||||
// These routines are used in AutoVector mode. Autovector mode is preferred.
|
||||
//
|
||||
// DO NOT HANDLE IMPORTANT USB REQUEST VIA TASKS !
|
||||
// IT TAKES TIME TO SIGNAL A TASK !!!!
|
||||
//
|
||||
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
// ============================================================================
|
||||
// USB interrupt hooks
|
||||
// ============================================================================
|
||||
void (*sudav) (void) = 0;
|
||||
|
||||
void (*ep0ack) (void) = 0;
|
||||
void (*ep0out) (void) = 0;
|
||||
void (*ep0in ) (void) = 0;
|
||||
|
||||
void (*ep1out) (void) = 0;
|
||||
void (*ep1in ) (void) = 0;
|
||||
|
||||
void (*ep2inout)(void) = 0;
|
||||
void (*ep4inout)(void) = 0;
|
||||
void (*ep6inout)(void) = 0;
|
||||
void (*ep8inout)(void) = 0;
|
||||
|
||||
// ============================================================================
|
||||
// (00) Setup Data Available interrupt handler
|
||||
// ============================================================================
|
||||
void ISR_sudav() interrupt 0
|
||||
{
|
||||
if( sudav)
|
||||
sudav();
|
||||
|
||||
USB_IRQ_CLEAR();
|
||||
USBIRQ = bmSUDAV;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// (04) Start of Frame
|
||||
// ============================================================================
|
||||
void ISR_sof() interrupt 0
|
||||
{
|
||||
USB_IRQ_CLEAR();
|
||||
USBIRQ = bmSOF;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// (08) Setup Token interrupt handler
|
||||
// ============================================================================
|
||||
void ISR_sutok() interrupt 0
|
||||
{
|
||||
USB_IRQ_CLEAR();
|
||||
USBIRQ = bmSUTOK;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// (0C) Global Suspend
|
||||
// ============================================================================
|
||||
void ISR_susp() interrupt 0
|
||||
{
|
||||
USB_IRQ_CLEAR();
|
||||
USBIRQ = bmSUSP;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// (10) USB Reset
|
||||
// ============================================================================
|
||||
void ISR_ures() interrupt 0
|
||||
{
|
||||
// ----------------------------------------------------
|
||||
// Whenever we get a USB reset, we should revert to
|
||||
// full speed mode.
|
||||
// ----------------------------------------------------
|
||||
pDscrMainConfig = pDscrFsConfig;
|
||||
pDscrOthrConfig = pDscrHsConfig;
|
||||
|
||||
pDscrMainConfig->type = DSCR_CONFIG;
|
||||
pDscrOthrConfig->type = DSCR_OTHERSPEED;
|
||||
|
||||
USB_IRQ_CLEAR();
|
||||
USBIRQ = bmURES;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// (14) Entered High Speed
|
||||
// ============================================================================
|
||||
void ISR_highspeed() interrupt 0
|
||||
{
|
||||
pDscrMainConfig = pDscrHsConfig;
|
||||
pDscrOthrConfig = pDscrFsConfig;
|
||||
|
||||
pDscrMainConfig->type = DSCR_CONFIG;
|
||||
pDscrOthrConfig->type = DSCR_OTHERSPEED;
|
||||
|
||||
USB_IRQ_CLEAR();
|
||||
USBIRQ = bmHSGRANT;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// (18) EP0ACK
|
||||
// ============================================================================
|
||||
void ISR_ep0ack() interrupt 0
|
||||
{
|
||||
if( ep0ack)
|
||||
ep0ack();
|
||||
|
||||
USB_IRQ_CLEAR();
|
||||
USBIRQ = bmEP0ACK;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// (20) EP0IN
|
||||
// ============================================================================
|
||||
void ISR_ep0in() interrupt 0
|
||||
{
|
||||
if( ep0in)
|
||||
ep0in();
|
||||
|
||||
USB_IRQ_CLEAR();
|
||||
EPIRQ = bmEP0IN;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// (24) EP0OUT
|
||||
// ============================================================================
|
||||
void ISR_ep0out() interrupt 0
|
||||
{
|
||||
if( ep0out)
|
||||
ep0out();
|
||||
|
||||
USB_IRQ_CLEAR();
|
||||
EPIRQ = bmEP0OUT;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// (28) EP1IN
|
||||
// ============================================================================
|
||||
void ISR_ep1in() interrupt 0
|
||||
{
|
||||
if( ep1in)
|
||||
ep1in();
|
||||
|
||||
USB_IRQ_CLEAR();
|
||||
EPIRQ = bmEP1IN;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// (2C) EP1OUT
|
||||
// ============================================================================
|
||||
void ISR_ep1out() interrupt 0
|
||||
{
|
||||
if( ep1out)
|
||||
ep1out();
|
||||
|
||||
USB_IRQ_CLEAR();
|
||||
EPIRQ = bmEP1OUT;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// (30) EP2
|
||||
// ============================================================================
|
||||
void ISR_ep2inout() interrupt 0
|
||||
{
|
||||
if( ep2inout)
|
||||
ep2inout();
|
||||
|
||||
USB_IRQ_CLEAR();
|
||||
EPIRQ = bmEP2;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// (34) EP4
|
||||
// ============================================================================
|
||||
void ISR_ep4inout() interrupt 0
|
||||
{
|
||||
if( ep4inout)
|
||||
ep4inout();
|
||||
|
||||
USB_IRQ_CLEAR();
|
||||
EPIRQ = bmEP4;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// (38) EP6
|
||||
// ============================================================================
|
||||
void ISR_ep6inout() interrupt 0
|
||||
{
|
||||
if( ep6inout)
|
||||
ep6inout();
|
||||
|
||||
USB_IRQ_CLEAR();
|
||||
EPIRQ = bmEP6;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// (3C) EP8
|
||||
// ============================================================================
|
||||
void ISR_ep8inout() interrupt 0
|
||||
{
|
||||
if( ep8inout)
|
||||
ep8inout();
|
||||
|
||||
USB_IRQ_CLEAR();
|
||||
EPIRQ = bmEP8;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// Dummy handlers
|
||||
// ============================================================================
|
||||
void ISR_ep0pingnak() interrupt 0 {}
|
||||
void ISR_ep1pingnak() interrupt 0 {}
|
||||
void ISR_ep2pingnak() interrupt 0 {}
|
||||
void ISR_ep4pingnak() interrupt 0 {}
|
||||
void ISR_ep6pingnak() interrupt 0 {}
|
||||
void ISR_ep8pingnak() interrupt 0 {}
|
||||
|
||||
|
||||
void ISR_ep2piderror() interrupt 0 {}
|
||||
void ISR_ep4piderror() interrupt 0 {}
|
||||
void ISR_ep6piderror() interrupt 0 {}
|
||||
void ISR_ep8piderror() interrupt 0 {}
|
||||
|
||||
void ISR_ep2pflag() interrupt 0 {}
|
||||
void ISR_ep4pflag() interrupt 0 {}
|
||||
void ISR_ep6pflag() interrupt 0 {}
|
||||
void ISR_ep8pflag() interrupt 0 {}
|
||||
|
||||
void ISR_ep2eflag() interrupt 0 {}
|
||||
void ISR_ep4eflag() interrupt 0 {}
|
||||
void ISR_ep6eflag() interrupt 0 {}
|
||||
void ISR_ep8eflag() interrupt 0 {}
|
||||
|
||||
void ISR_ep2fflag() interrupt 0 {}
|
||||
void ISR_ep4fflag() interrupt 0 {}
|
||||
void ISR_ep6fflag() interrupt 0 {}
|
||||
void ISR_ep8fflag() interrupt 0 {}
|
||||
|
||||
void ISR_ibn() interrupt 0 {}
|
||||
void ISR_errorlimit() interrupt 0 {}
|
||||
|
||||
void ISR_gpifcomplete() interrupt 0 {}
|
||||
void ISR_gpifwaveform() interrupt 0 {}
|
||||
|
||||
void ISR_stub() interrupt 0 {}
|
||||
@@ -0,0 +1,6 @@
|
||||
#include <fx2.h>
|
||||
#include <fx2_regs.h>
|
||||
|
||||
void job_sleep(void)
|
||||
{
|
||||
}
|
||||
@@ -0,0 +1,171 @@
|
||||
// ============================================================================
|
||||
// IMPORTANT
|
||||
//
|
||||
// The project specific descriptor table must exist !!!
|
||||
// It declares the following symbols:
|
||||
// - DscrString
|
||||
// - DscrDevice
|
||||
// - DscrDeviceQual
|
||||
// - DscrHsConfig
|
||||
// - DscrFsConfig
|
||||
// ============================================================================
|
||||
#include <fx2.h>
|
||||
#include <fx2_regs.h>
|
||||
|
||||
xdata DEVICE_DSCR xdata *pDscrDevice;
|
||||
xdata DEVICEQUAL_DSCR xdata *pDscrDeviceQual;
|
||||
|
||||
extern xdata CONFIG_DSCR xdata *pDscrMainConfig;
|
||||
extern xdata CONFIG_DSCR xdata *pDscrOthrConfig;
|
||||
extern xdata CONFIG_DSCR xdata *pDscrFsConfig;
|
||||
extern xdata CONFIG_DSCR xdata *pDscrHsConfig;
|
||||
|
||||
|
||||
data STRING_DSCR xdata *pDscrString;
|
||||
|
||||
STRING_DSCR xdata * GetStringDscr( BYTE index);
|
||||
|
||||
bool (*DR_VendorCommand)() = 0;
|
||||
|
||||
// ============================================================================
|
||||
// SUDAV (device request parser)
|
||||
//
|
||||
// The following commands have no default implementation:
|
||||
// - SC_GET_INTERFACE
|
||||
// - SC_SET_INTERFACE
|
||||
// - SC_GET_CONFIGURATION
|
||||
// - SC_SET_CONFIGURATION
|
||||
//
|
||||
// These commands usually result in changing the hardware configuration, which
|
||||
// is different in most device.
|
||||
// ============================================================================
|
||||
void tri_sudav()
|
||||
{
|
||||
STRING_DSCR xdata *ptr;
|
||||
BYTE xdata cfg;
|
||||
|
||||
switch( SETUPDAT[1])
|
||||
{
|
||||
// ------------------------------------------------
|
||||
// Get Descriptor
|
||||
// ------------------------------------------------
|
||||
case SC_GET_DESCRIPTOR:
|
||||
switch( SETUPDAT[3])
|
||||
{
|
||||
case GD_DEVICE:
|
||||
SUDPTRH = MSB(pDscrDevice);
|
||||
SUDPTRL = LSB(pDscrDevice);
|
||||
break;
|
||||
|
||||
case GD_DEVICE_QUALIFIER:
|
||||
// Only for HighSpeed capable devices
|
||||
SUDPTRH = MSB(pDscrDeviceQual);
|
||||
SUDPTRL = LSB(pDscrDeviceQual);
|
||||
break;
|
||||
|
||||
case GD_CONFIGURATION:
|
||||
SUDPTRH = MSB(pDscrMainConfig);
|
||||
SUDPTRL = LSB(pDscrMainConfig);
|
||||
break;
|
||||
|
||||
case GD_OTHER_SPEED_CONFIG:
|
||||
SUDPTRH = MSB(pDscrOthrConfig);
|
||||
SUDPTRL = LSB(pDscrOthrConfig);
|
||||
break;
|
||||
|
||||
case GD_STRING:
|
||||
if( ptr = GetStringDscr(SETUPDAT[2]))
|
||||
{
|
||||
SUDPTRH = MSB(ptr);
|
||||
SUDPTRL = LSB(ptr);
|
||||
}
|
||||
else
|
||||
FX2_STALL_EP0();
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
FX2_STALL_EP0();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
// ------------------------------------------------
|
||||
// Get Status
|
||||
// ------------------------------------------------
|
||||
case SC_GET_STATUS:
|
||||
switch( SETUPDAT[0])
|
||||
{
|
||||
case GS_DEVICE:
|
||||
// EP0BUF[0] = ((BYTE)Rwuen << 1) | (BYTE)SelfPower;
|
||||
EP0BUF[0] = 0;
|
||||
EP0BUF[1] = 0;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 2;
|
||||
break;
|
||||
|
||||
case GS_INTERFACE:
|
||||
EP0BUF[0] = 0;
|
||||
EP0BUF[1] = 0;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 2;
|
||||
break;
|
||||
|
||||
case GS_ENDPOINT:
|
||||
// EP0BUF[0] = (*(BYTE xdata *)epcs(SETUPDAT[4])) & bmEPSTALL;
|
||||
EP0BUF[0] = 0;
|
||||
EP0BUF[1] = 0;
|
||||
EP0BCH = 0;
|
||||
EP0BCL = 2;
|
||||
break;
|
||||
|
||||
default:
|
||||
FX2_STALL_EP0();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
// ------------------------------------------------
|
||||
// Set Configuration
|
||||
// ------------------------------------------------
|
||||
case SC_SET_CONFIGURATION:
|
||||
cfg = SETUPDAT[2];
|
||||
break;
|
||||
|
||||
// ------------------------------------------------
|
||||
// Vendor command
|
||||
// ------------------------------------------------
|
||||
default:
|
||||
if( !DR_VendorCommand)
|
||||
{
|
||||
}
|
||||
|
||||
else if( !DR_VendorCommand())
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
// --------------------------------------------------------------
|
||||
// Acknowledge handshake phase of device request.
|
||||
// --------------------------------------------------------------
|
||||
EP0CS |= bmHSNAK;
|
||||
}
|
||||
|
||||
// ============================================================================
|
||||
// GetStringDscr
|
||||
// ============================================================================
|
||||
STRING_DSCR xdata * GetStringDscr( BYTE index)
|
||||
{
|
||||
STRING_DSCR xdata * dscr = pDscrString;
|
||||
|
||||
while( dscr->type == DSCR_STRING)
|
||||
{
|
||||
if( !index--)
|
||||
return dscr;
|
||||
|
||||
dscr = (STRING_DSCR xdata *)((WORD)dscr +dscr->length);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user