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Added palette JFET opamp

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This commit is contained in:
Roka Miklos
2026-07-01 13:27:32 +02:00
parent 15c03659da
commit efc9995164
23 changed files with 1061 additions and 0 deletions
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veriloga/mr/bf862.va
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`include "constants.vams"
`include "disciplines.vams"
module bf862_noise (d, g, s);
inout d, g, s;
electrical d, g, s;
// ==================== BF862 Core Parameters ====================
parameter real VTO = -0.70; // Pinch-off voltage (typical)
parameter real BETA = 0.030; // Transconductance parameter (A/V²)
parameter real LAMBDA = 0.035; // Channel length modulation (1/V)
parameter real RD = 5.0; // Drain resistance
parameter real RS = 5.0; // Source resistance
// Flicker noise
parameter real KF = 5.0e-16; // Flicker noise coefficient (drain current)
parameter real AF = 1.0;
// Capacitances
parameter real CGS = 3.5e-12; // Gate-Source capacitance
parameter real CGD = 1.8e-12; // Gate-Drain capacitance
// ==================== Package Parameters (SOT-23) ====================
parameter real Ld = 1.1e-9; // Drain lead inductance
parameter real Lg = 1.0e-9; // Gate lead inductance
parameter real Ls = 1.25e-9; // Source lead inductance
parameter real Rd_pkg = 0.08; // Drain package resistance
parameter real Rg_pkg = 0.08; // Gate package resistance
parameter real Rs_pkg = 0.08; // Source package resistance
electrical di, gi, si; // Internal chip nodes
real vgs, vds, id, gm;
real T;
analog begin
T = $temperature;
vgs = V(gi, si);
vds = V(di, si);
// ==================== JFET Current (Square Law + Early) ====================
if (vgs > VTO) begin
id = 0; // Cutoff
end else begin
id = BETA * (vgs - VTO)*(vgs - VTO) * (1 + LAMBDA * vds);
end
// Transconductance (for noise calculation)
gm = 2 * BETA * (vgs - VTO) * (1 + LAMBDA * vds);
// ==================== Package Parasitics ====================
V(d, di) <+ Ld * ddt(I(d, di)) + Rd_pkg * I(d, di);
V(g, gi) <+ Lg * ddt(I(g, gi)) + Rg_pkg * I(g, gi);
V(s, si) <+ Ls * ddt(I(s, si)) + Rs_pkg * I(s, si);
// ==================== Internal Resistances ====================
V(di, di) <+ RD * I(di);
V(si, si) <+ RS * I(si);
// ==================== Drain Current ====================
I(di, si) <+ id;
// ==================== NOISE SOURCES ====================
// 1. Thermal channel noise (dominant in JFETs)
if (gm > 0) begin
I(di, si) <+ white_noise( (4.0/3.0) * `P_K * T * gm , "thermal");
end
// 2. Flicker (1/f) noise on drain current
if (KF > 0 && id > 0) begin
I(di, si) <+ flicker_noise(KF * pow(id, AF), 1.0, "flicker");
end
// 3. Gate shot noise (very small in JFETs)
I(g, gi) <+ white_noise(2 * `P_Q * 1e-12, "gate_shot"); // ~1pA leakage
// ==================== Capacitances ====================
I(gi, si) <+ ddt( CGS * V(gi, si) );
I(gi, di) <+ ddt( CGD * V(gi, di) );
end
endmodule
veriloga/mr/mr_opamp.va
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// (setq tab-width 4)
`include "constants.h"
`include "discipline.h"
`define dB2dec(x) pow(10,x/20)
`include "mr_diode.va"
module va_opamp(inp, inn, out, vdd, vss);
inout inp, inn, out, vdd, vss;
electrical inp, inn, out, vdd, vss;
// default parameters are for a typical uA741.
parameter real Aol = 200e3 from (0 : inf); // Open loop DC gain [V/V] 200e3
parameter real GBW = 1e6 from (1 : inf); // Gain bandwidth product [Hz] 10e6
parameter real Rin = 2e6 from [0.01 : inf]; // Differential Input resistance [Ohm]
parameter real Rout = 75 from [0.01 : inf]; // Output resistance [Ohm]
parameter real VRailp = 1 from [0 : inf]; // Positive output voltage limit [V]
parameter real VRailn = 1 from [0 : inf]; // Negative output voltage limit [V]
parameter real Vos = 1.0e-3 from [0 : inf]; // Input voltage offset [V]
parameter real Ios = 20.0e-9 from [1e-20 : inf]; // Input offset current [A]
parameter real Ib = 80.0e-9 from [-inf : inf]; // Input bias current [A]
parameter real Cin = 1.4e-12 from [1e-20 : inf]; // Differential input capacitance [F]
parameter real SRp = 500e3 from [1 : inf]; // Positive slew rate [V/s]
parameter real SRn = 500e3 from [1 : inf]; // Negative slew rate [V/s]
// parameter real fp2 = 3e6 from [0.01 : inf]; // Secod pole frequency [Hz]
// parameter real CMR = 90 from [1 : inf]; // Common mode rejection ratio at DC [dB]
// parameter real FCM = 200 from [0.01 : inf]; // Common mode zero corner frequency [Hz]
// parameter real Io_maxp = 35e-3 from [1e-09 : inf]; // Positive output voltage limit [V]
// parameter real Io_maxn = -35e-3 from [-inf : 0]; // Negative output voltage limit [V]
// parameter real CScale = 50 from [0 : inf]; // Current limit scaling factor
electrical net_s1;
electrical net_ref;
electrical net_limp;
electrical net_limn;
branch (net_s1, net_ref) cur_s1, res_s1, cap_s1;
branch (net_s1, net_limp) res_limp, cap_limp;
branch (net_limn, net_s1) res_limn, cap_limn;
// ---
real Vin;
// -------------------------------------------------------------------------
// first stage (gain, pole, slew)
// -------------------------------------------------------------------------
real I1;
real Ig1;
real fp1;
real Kp1;
real Rp1;
real Cp1;
// -------------------------------------------------------------------------
// simplified diode model parameters
// the diodes used in voltage limit subcircuits
// -------------------------------------------------------------------------
real is = 10f; // saturation current [A] 10f
real tf = 1u; // forward transit tim [s]
real cjo = 10f; // zero-bias junction capacitance [F]
real phi = 0.7; // built-in junction potential [V]
// -------------------------------------------------------------------------
// output voltage limitation
// -------------------------------------------------------------------------
real Vo_max; // maximum positive output voltage
real Vo_min; // maximum negative output voltage
real qdp; // positive output voltage limit diode charge
real qdn; // negative output voltage limit diode charge
analog
begin
@(initial_step)
begin
I1 = 0.01;
fp1 = GBW / Aol;
Cp1 = I1 / SRp;
Rp1 = 1 / (2 * `M_PI * fp1 * Cp1);
Kp1 = Aol / (I1 * Rp1);
Vo_max = V(vdd) - VRailp;
Vo_min = V(vss) + VRailn;
$display("\n");
$display("--------------------------------------");
$display("GBW = %12.3f Hz", GBW);
$display("SRp = %12.3f V/s", SRp);
$display("--------------------------------------");
$display("I1 = %12.3f mA", I1 *1e3);
$display("fp1 = %12.3f Hz", fp1);
$display("Cp1 = %12.3f nF", Cp1 *1e9);
$display("Rp1 = %12.3f kOhm", Rp1 /1000);
$display("Kp1 = %12.3f V/V", Kp1);
$display("--------------------------------------");
$display("Vdd = %12.3f V", V(vdd));
$display("Vss = %12.3f V", V(vss));
$display("Vo_max = %12.3f V", Vo_max);
$display("Vo_min = %12.3f V", Vo_min);
end;
// -----------------------------------------------------------
// set fix net voltages
// -----------------------------------------------------------
V(net_ref) <+ (V(vdd) +V(vss)) / 2;
V(net_limp) <+ Vo_max - phi;
V(net_limn) <+ Vo_min + phi;
// -----------------------------------------------------------
// input bias and offset currents, offset voltage
// -----------------------------------------------------------
Vin = V(inp,inn) + Vos; // Input offset voltage
I(inp) <+ Ib; // Input bias current
I(inn) <+ Ib; // Input bias current
I(inp,inn) <+ Ios / 2; // Input offset current
I(inp,inn) <+ Vin / Rin; // Input stage current
// -----------------------------------------------------------
// gain, pole 1, slew
// -----------------------------------------------------------
I(cur_s1) <+ -I1 * tanh( Kp1 * Vin);;
V(res_s1) <+ Rp1 * I(res_s1);
/*
if( analysis("ic"))
$display("-> IC");
else if( analysis("dc"))
$display("-> DC");
else if( analysis("ac"))
$display("-> AC");
else if(analysis("static"))
$display("-> STATIC");
else if( analysis("tran"))
$display("-> TRAN");
else if( analysis("noise"))
$display("-> NOISE");
else
$display("-> unknown");
*/
if( analysis("ic"))
begin
V(cap_s1) <+ 0;
V(cap_limp) <+ 0;
V(cap_limn) <+ 0;
end
else if( analysis("dc"))
I(cap_s1) <+ 0;
else
I(cap_s1) <+ Cp1 * ddt( V(cap_s1));
if( !analysis("ac"))
begin
// -----------------------------------------------------------------
// positive output voltage limiting
// -----------------------------------------------------------------
qdp = tf * I(res_limp) - 2 * cjo * phi * sqrt(1 -V(cap_limp)/phi);
I(res_limp) <+ is * (limexp( V(res_limp)/$vt) -1);
I(cap_limp) <+ ddt(qdp);
// -----------------------------------------------------------------
// negative output voltage limiting
// -----------------------------------------------------------------
qdn = tf * I(res_limn) - 2 * cjo * phi * sqrt(1 -V(cap_limn)/phi);
I(res_limn) <+ is * (limexp( V(res_limn)/$vt) -1);
I(cap_limn) <+ ddt(qdn);
end;
V(out) <+ V(cap_s1);
end
endmodule
veriloga/mr/opamps/opamps.va
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`include "constants.h"
`include "discipline.h"
// uA741
// AD822
// LTC1050
// TL071
// NE5534
// OPA627
// ---------------------------------------------------------
// uA741
// ---------------------------------------------------------
module uA741( inp, inn, out, vdd, vss);
inout inp, inn, out, vdd, vss;
electrical inp, inn, out, vdd, vss;
va_opamp opa( inp, inn, out, vdd, vss);
endmodule
// ---------------------------------------------------------
// TLC2272
// ---------------------------------------------------------
module TLC2272( inp, inn, out, vdd, vss);
inout inp, inn, out, vdd, vss;
electrical inp, inn, out, vdd, vss;
va_opamp #( .Aol(50e3),
.GBW(2.18e6),
.Rin(10e12),
.Rout(140),
.VRailp(0.25),
.VRailn(0.25),
.Vos(950e-6),
.Ios(100e-12),
.Ib(100e-12),
.Cin(8),
.SRp(3.5e6),
.SRn(3.5e6)
)
opa( inp, inn, out, vdd, vss);
endmodule
// ---------------------------------------------------------
// NJM2068
//
// .Rout(),
// .Cin(),
// ---------------------------------------------------------
module NJM2068( inp, inn, out, vdd, vss);
inout inp, inn, out, vdd, vss;
electrical inp, inn, out, vdd, vss;
va_opamp #( .Aol(750e3),
.GBW(27e6),
.Rin(300e3),
.VRailp(1.5),
.VRailn(1.5),
.Vos(3e-3),
.Ios(200e-9),
.Ib(1e-6),
.SRp(6e6),
.SRn(6e6)
)
opa( inp, inn, out, vdd, vss);
endmodule
// ---------------------------------------------------------
// NJM4058 (50 mA)
//
// .Rin()
// .Rout()
// .Cin()
// ---------------------------------------------------------
module NJM4058( inp, inn, out, vdd, vss);
inout inp, inn, out, vdd, vss;
electrical inp, inn, out, vdd, vss;
va_opamp #( .Aol(750e3),
.GBW(15e6),
.VRailp(1.5),
.VRailn(1.5),
.Vos(3e-3),
.Ios(200e-9),
.Ib(500e-9),
.SRp(5e6),
.SRn(5e6)
)
opa( inp, inn, out, vdd, vss);
endmodule
// ---------------------------------------------------------
// LT1001
//
// .Rout()
// .Cin()
// ---------------------------------------------------------
module LT1001( inp, inn, out, vdd, vss);
inout inp, inn, out, vdd, vss;
electrical inp, inn, out, vdd, vss;
va_opamp #( .Aol(8e5),
.GBW(8e5),
.Rin(80e6),
.VRailp(1),
.VRailn(1),
.Vos(60e-6),
.Ios(1e-9),
.Ib(1e-9),
.SRp(0.25e6),
.SRn(0.25e6)
)
opa( inp, inn, out, vdd, vss);
endmodule
// ---------------------------------------------------------
// LT1007
//
// .Cin()
// ---------------------------------------------------------
module LT1007( inp, inn, out, vdd, vss);
inout inp, inn, out, vdd, vss;
electrical inp, inn, out, vdd, vss;
va_opamp #( .Aol(20e6),
.GBW(8e6),
.Rin(5e9),
.Rout(70),
.VRailp(1.5),
.VRailn(1.5),
.Vos(60e-6),
.Ios(50e-9),
.Ib(50e-9),
.SRp(2.5e6),
.SRn(2.5e6)
)
opa( inp, inn, out, vdd, vss);
endmodule
// ---------------------------------------------------------
// OPA627
// ---------------------------------------------------------
module OPA627( inp, inn, out, vdd, vss);
inout inp, inn, out, vdd, vss;
electrical inp, inn, out, vdd, vss;
va_opamp #( .Aol(1e6),
.GBW(16e6),
.Rin(10e13),
.Rout(55),
.VRailp(2.7),
.VRailn(2.7),
.Vos(100e-6),
.Ios(1e-12),
.Ib(2e-12),
.Cin(8e-12),
.SRp(55e6),
.SRn(55e6)
)
opa( inp, inn, out, vdd, vss);
endmodule
// ---------------------------------------------------------
// LTC1050
// ---------------------------------------------------------
module LTC1050( inp, inn, out, vdd, vss);
inout inp, inn, out, vdd, vss;
electrical inp, inn, out, vdd, vss;
va_opamp #( .Aol(1e6),
.GBW(2.5e6),
.Rin(1e13),
.Rout(50),
.VRailp(0.15),
.VRailn(0.15),
.Vos(5e-6),
.Ios(60e-12),
.Ib(30e-12),
.Cin(8e-12),
.SRp(4e6),
.SRn(4e6)
)
opa( inp, inn, out, vdd, vss);
endmodule
// ---------------------------------------------------------
// TL071
// ---------------------------------------------------------
module TL071( inp, inn, out, vdd, vss);
inout inp, inn, out, vdd, vss;
electrical inp, inn, out, vdd, vss;
va_opamp #( .Aol(200e3),
.GBW(3e6),
.Rin(1e12),
.VRailp(1.5),
.VRailn(1.5),
.Vos(3e-3),
.Ios(5e-12),
.Ib(65e-12),
.SRp(13e6),
.SRn(13e6)
)
opa( inp, inn, out, vdd, vss);
endmodule
// ---------------------------------------------------------
// LM324
// ---------------------------------------------------------
module LM324( inp, inn, out, vdd, vss);
inout inp, inn, out, vdd, vss;
electrical inp, inn, out, vdd, vss;
va_opamp #( .Aol(100e3),
.GBW(1e6),
.VRailp(1.5),
.VRailn(0.01),
.Vos(2e-3),
.Ios(5e-9),
.Ib(-45e-9),
.SRp(1.2e6),
.SRn(1.2e6)
)
opa( inp, inn, out, vdd, vss);
endmodule
// ---------------------------------------------------------
// NE5534
// ---------------------------------------------------------
module NE5534( inp, inn, out, vdd, vss);
inout inp, inn, out, vdd, vss;
electrical inp, inn, out, vdd, vss;
va_opamp #( .Aol(101e3),
.GBW(10e6),
.Rin(100e3),
.Rout(0.3),
.VRailp(2),
.VRailn(2),
.Vos(0.5e-3),
.Ios(20e-9),
.Ib(500e-9),
.SRp(13e6),
.SRn(13e6)
)
opa( inp, inn, out, vdd, vss);
endmodule
// ---------------------------------------------------------
// AD822
// ---------------------------------------------------------
module AD822( inp, inn, out, vdd, vss);
inout inp, inn, out, vdd, vss;
electrical inp, inn, out, vdd, vss;
va_opamp #( .Aol(1e6),
.GBW(1.8e6),
.Rin(1e13),
.Rout(20),
.VRailp(0.1),
.VRailn(0.1),
.Vos(0.5e-3), // 0.5e-3
.Ios(10e-12),
.Ib(10e-12),
.Cin(0.5e-12),
.SRp(3e6),
.SRn(3e6)
)
opa( inp, inn, out, vdd, vss);
endmodule
/*
parameter real Aol = 200e3 from (0 : inf); // Open loop DC gain [V/V] 200e3
parameter real GBW = 1e6 from (1 : inf); // Gain bandwidth product [Hz] 10e6
parameter real Rin = 2e6 from [0.01 : inf]; // Differential Input resistance [Ohm]
parameter real Rout = 75 from [0.01 : inf]; // Output resistance [Ohm]
parameter real VRailp = 1 from [0 : inf]; // Positive output voltage limit [V]
parameter real VRailn = 1 from [0 : inf]; // Negative output voltage limit [V]
parameter real Vos = 1.0e-3 from [0 : inf]; // Input voltage offset [V]
parameter real Ios = 20.0e-9 from [1e-20 : inf]; // Input offset current [A]
parameter real Ib = 80.0e-9 from [1e-20 : inf]; // Input bias current [A]
parameter real Cin = 1.4e-12 from [1e-20 : inf]; // Differential input capacitance [F]
parameter real SRp = 500e3 from [1 : inf]; // Positive slew rate [V/s]
parameter real SRn = 500e3 from [1 : inf]; // Negative slew rate [V/s]
va_opamp #( .Aol(),
.GBW(),
.Rin(),
.Rout(),
.VRailp(),
.VRailn(),
.Vos(),
.Ios(),
.Ib(),
.Cin(),
.SRp(),
.SRn()
)
opa( inp, inn, out, vdd, vss);
*/