 roka
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efc9995164
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Added palette JFET opamp
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2026-07-01 13:27:45 +02:00 |
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roka
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15c03659da
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Added BJT models
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2026-06-30 17:38:40 +02:00 |
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roka
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51f17e5c2d
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Added Diode component with standard and verilog model (diode, led, zener)
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2026-06-30 17:24:07 +02:00 |
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roka
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c0c3de344a
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Fixed capacitor ael file
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2026-06-30 17:23:00 +02:00 |
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roka
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20e94f3dfa
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Added capacitor and inductor components
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2026-06-30 16:26:36 +02:00 |
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roka
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d8edd68938
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Added JFET component with 1 model
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2026-06-30 15:54:18 +02:00 |
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roka
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0175490365
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Added BJT component with 2 models
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2026-06-29 20:18:44 +02:00 |
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roka
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5c458d5a63
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Added resistor component with 3 different simulation model including Verilog-A
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2026-06-29 10:58:24 +02:00 |
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roka
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2562ba7a10
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Expand verilog model search path with the folder where the cells are located
Then the verilog model can live with the cell itself
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2026-06-28 13:12:16 +02:00 |
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roka
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3957277454
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Absolute minimal initial checkin
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2026-06-27 17:33:25 +02:00 |
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