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roka
5c458d5a63
Added resistor component with 3 different simulation model including Verilog-A
2026-06-29 10:58:24 +02:00
circuit
/ael
Added resistor component with 3 different simulation model including Verilog-A
2026-06-29 10:58:24 +02:00
de
/ael
Expand verilog model search path with the folder where the cells are located
2026-06-28 13:12:16 +02:00
mrModels
Added resistor component with 3 different simulation model including Verilog-A
2026-06-29 10:58:24 +02:00
mrModels_tech
Absolute minimal initial checkin
2026-06-27 17:33:25 +02:00
.gitignore
Absolute minimal initial checkin
2026-06-27 17:33:25 +02:00
lib_ro.defs
Absolute minimal initial checkin
2026-06-27 17:33:25 +02:00
lib_rw.defs
Absolute minimal initial checkin
2026-06-27 17:33:25 +02:00
S
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98.1%
Java
1.9%
