Commit Graph

3 Commits

Author SHA1 Message Date
roka 5c458d5a63 Added resistor component with 3 different simulation model including Verilog-A 2026-06-29 10:58:24 +02:00
roka 2562ba7a10 Expand verilog model search path with the folder where the cells are located
Then the verilog model can live with the cell itself
2026-06-28 13:12:16 +02:00
roka 3957277454 Absolute minimal initial checkin 2026-06-27 17:33:25 +02:00